JPH0540552A - Standby circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Not only the circuit that supports the operation to automatically return to normal operation when the main circuit returns from low current consumption operation to normal operation, but there is also a standby release command. , It can also be used for circuits that do not support automatic return to normal operation. [Structure] A standby circuit for reducing current consumption of a main circuit includes a standby input control circuit and a latch circuit, and the standby input control circuit is provided with an auto release enable terminal as an input terminal.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a standby circuit.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional standby circuit has four input terminals of a standby input control circuit 1.
Since there is no automatic release enable terminal for inputting the fifth input signal, the latch output terminal 17 of the latch circuit 2
The signal fed back from the feedback terminal 9 to the feedback terminal 9 is not controlled by another control signal line. Therefore, in order for the main circuit 3 having the standby selection terminal 18 to return from the low current consumption operation to the normal operation, data is supplied to the standby state setting terminal 11 of the standby input control circuit 1 and data is written to the latch circuit 2. The main circuit 3 was always automatically restored without performing the operation of.

[0003]

However, in the conventional technique, the main circuit is always automatically restored when the low current consumption operation is restored to the normal operation. Therefore, the standby state setting terminal of the standby input control circuit 1 is used. It cannot be used when an operation of supplying data to 11 and writing data to the latch circuit 2 is required. Specifically, for example, the data given to the standby state setting terminal 11 is created by sending an instruction for returning to normal operation (hereinafter referred to as a standby release instruction) to the microcomputer and decoding this instruction. It Therefore, there is a problem that the conventional standby circuit cannot be used in a circuit that does not support the operation of automatically returning to the normal operation although the standby cancel instruction exists. Therefore, the present invention solves such a conventional problem, and an object thereof is to support an operation of automatically returning to the normal operation when the main circuit returns from the low current consumption operation to the normal operation. There is a standby release command as well as the circuit
The purpose is to make it available for circuits that do not support the operation of automatically returning to normal operation.

[0004]

The standby circuit of the present invention uses the following means.

(1) In a standby circuit for reducing current consumption of the main circuit, a feedback terminal for receiving a first input signal, a standby state setting terminal for receiving a second input signal,
A standby input control circuit having a write terminal for receiving a third input signal, an enable terminal for receiving a fourth input signal as input terminals, and a standby mode terminal, a standby write terminal as output terminals, and a first input signal. A latch circuit having a data input terminal for receiving and a clock terminal for receiving a second input signal as input terminals and a latch output terminal as output terminals, and a standby mode terminal of the standby input control circuit and the latch circuit. Of the standby input circuit, the standby write terminal of the standby input control circuit and the clock terminal of the latch circuit, and the feedback terminal of the standby input control circuit and the latch output terminal of the latch circuit, Input the fifth input signal to the standby input control circuit Rukoto by characterized by providing an automatic release enable terminal for determining either of the useful signal or disable signal to said first input signal of the standby input control circuit as an input terminal. (2) The standby circuit according to claim 1, wherein the standby input control circuit receives the first input signal which is an output signal of the latch circuit in which a state signal of a main circuit is stored and held, Output as the first input signal to the data input terminal of the latch circuit by the second input signal which is a signal for determining the state of the main circuit and the input signal of The third input signal, which is an original signal generated from the second input signal input from the clock terminal that is paired with the first input signal of the circuit, and the third input signal, which is a valid signal. Alternatively, it has a logic circuit for generating an output signal of the standby write terminal according to the fourth input signal which is determined to be either an invalid signal.

[0006]

The present invention will be described in more detail with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 1 is a standby input control circuit having five input terminals and two output terminals. A latch circuit 2 receives the output of the standby input control circuit 1 and stores and holds data. A main circuit 3 receives the output of the latch circuit 2 and has a standby selection terminal. Standby selection terminal 18
When is high, the main circuit 3 is in an operating state with low current consumption.

First, the signal output relationship between the input terminal and the output terminal of the standby input control circuit 1 will be described below based on the truth table 1 of the standby input control circuit.

[0008]

[Table 1]

When the auto release enable terminal 21 is high and the feedback terminal 9 is low, the signal set to the standby mode terminal 13 is input to the standby state setting terminal 11 by the operation of the inverter circuit 8 and the AND circuit 7. The signal is output directly. In addition, the standby write terminal 14
The signal output to is when the enable terminal 10 is high,
The signal input to the write terminal 12 is directly output, and when it is low, it is forced to be high. The input / output relationship of these signals excluding the feedback terminal 9 is the same as that of the standby input control circuit 1 of the conventional semiconductor integrated circuit shown in FIG.

When the automatic release enable terminal 21 is high and the feedback terminal 9 is high, the signal output to the standby mode terminal 13 is forced to be low. As for the signal output to the standby write terminal 14, the signal of the write terminal 12 is directly output regardless of the state of the enable terminal 10.

When the automatic release enable terminal 21 is low, the function is the same as when the automatic release enable terminal 21 is high and the feedback terminal 9 is low, regardless of the state of the feedback terminal 9.

Next, with respect to the signal output relationship between the input terminal and the output terminal of the latch circuit 2, a truth table of the latch circuit 2
Based on

[0013]

[Table 2]

The latch output terminal 17 has a clock terminal 1
At the rising edge of the signal input from 6, the signal of the data input terminal 15 is output, and at the falling edge,
The data stored on the previous rising edge is retained.

First, the circuit operation when the automatic release enable terminal 21 of the standby input control circuit 1 is high, that is, in the mode of automatically returning from the low current consumption operation to the normal operation will be described.

To shift the main circuit 3 from the normal operation to the low current consumption operation, the enable terminal 10 and the standby state setting terminal 11 of the standby input control circuit 1 are set to high and the write terminal 12 is set to high, low, and high. All you have to do is input a signal. The feedback control terminal 9 is connected to the latch output terminal 17 of the latch circuit 2, and during normal operation, a low signal is input because a low is stored and held in the latch circuit 2. Therefore, from the operation of the standby input control circuit 1,
Since high data is written in the latch circuit 2, the main circuit 3 operates in low current consumption.

In order to return from the low current consumption operation to the normal operation, the write terminal 11 of the standby input control circuit 1
It is sufficient to input high, low, and high signals to. During low current consumption operation, the signal appearing at the latch output terminal 17 of the latch circuit 2 is high, so the feedback control terminal 9 of the peripheral control terminal 1
To the standby mode terminal 13
Is forced low. Further, since the signal input to the write selection terminal 12 is directly transmitted to the standby write terminal 14, a low is written in the latch circuit 2, and the main circuit 3 returns from the low current consumption operation to the normal operation.

Next, consider the case where the automatic release enable terminal 21 of the standby input control circuit 1 is low. As shown in Table 1, since the function is the same as when the auto release enable terminal 21 is high and the feedback terminal 9 is low,
The function of automatically returning from the normal operation disappears, and the operation to return to the normal operation by the standby release command becomes possible.

[0019]

As described above, according to the present invention, in the standby circuit of the present invention, the main circuit is lowered by providing the standby input control circuit with the automatic cancel enable terminal and switching the signal applied to the terminal. When returning from the consumption current operation to the normal operation, the circuit can support not only the operation of automatically returning to the normal operation but also the operation of returning to the normal operation by the standby release command.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional standby circuit.

[Explanation of symbols]

 1: Standby input control circuit 2: Latch circuit 3: Main circuit 4: Logical sum circuit 5: Negative product circuit 6, 7, 20: Logical product circuit 8: Inverter circuit 9: Feedback terminal 10: Enable terminal 11: Standby state setting Terminal 12: Writing terminal 13: Standby mode terminal 14: Standby writing terminal 15: Data input terminal 16: Clock terminal 17: Latch output terminal 18: Standby selection terminal 21: Auto release enable terminal

Claims (2)

[Claims] 1. A feedback circuit for receiving a first input signal in a standby circuit for reducing current consumption of a main circuit, and a second circuit.
A standby state setting terminal for receiving an input signal, a write terminal for receiving a third input signal, an enable terminal for receiving a fourth input signal as input terminals, and a standby input having a standby mode terminal and a standby write terminal as output terminals. The standby circuit includes a control circuit, a data input terminal that receives a first input signal, a latch circuit that has a clock terminal that receives a second input signal as input terminals, and a latch output terminal as an output terminal. A standby mode terminal of the control circuit and a data input terminal of the latch circuit, a standby write terminal of the standby input control circuit and a clock terminal of the latch circuit, and a feedback terminal of the standby input control circuit and a latch output terminal of the latch circuit. In each connected standby circuit, An automatic release enable terminal that determines whether the first input signal of the standby input control circuit is a valid signal or an invalid signal by inputting a fifth input signal to the standby input control circuit is provided as an input terminal. Stand-by circuit characterized by that. 2. The standby circuit according to claim 1, wherein the standby input control circuit receives the first input signal which is an output signal of the latch circuit in which a state signal of a main circuit is stored and held, The first input signal and the second input signal, which is a signal for determining the state of the main circuit, are output as the first input signal to the data input terminal of the latch circuit, and the first input signal and The first of the latch circuits
The third input signal, which is an original signal generated from the second input signal input from the clock terminal that is paired with the second input signal.
And a logic circuit for generating an output signal of the standby write terminal according to the fourth input signal for determining whether the third input signal is a valid signal or an invalid signal. circuit.