JPH0540652A - Microprocessor - Google Patents

Abstract

PURPOSE:To reduce the cost of equipment of a microprocessor by providing a clock generator which is controlled by the signal inputted to an external test terminal and a reset signal generator which is controlled by the input signal and the clock and initializes an internal circuit. CONSTITUTION:When an inactive signal is inputted to a test terminal 1, a transfer gate G1 is turned on with a transfer gate G2 turned off respectively. When an active signal is inputted to the terminal 1, the gates G1 and G2 are respectively turned off and on. Then the output value of an inverter In is inputted to an internal clock driver 4 as a clock that actuates the internal circuit of a microprocessor. The output value of a reset signal generator 3 is counted up one by one with each input of a clock after an active signal is inputted to a counter resetter. The output value of the generator 3 is used as a signal to reset the internal circuit of a tested microprocessor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit test, and more particularly to a microprocessor (hereinafter referred to as MPU).
Regarding the closed BT test in the reliability acceleration test of.

[0002]

2. Description of the Related Art The BT test (Burn In Test) in the MPU reliability acceleration test is to evaluate the reliability of the MPU by supplying a bias power to the MPU under test for a long time in a high temperature environment. It is a test. A high temperature environment is a special furnace (usually
It is called BT furnace. It is realized by inserting an MPU under test mounted on a test board called a BT board into the bracket.

However, the present-day MPU can be integrated on a large scale, and is usually composed of millions of transistors and has a BT.
If only the bias power supply is supplied during the test, the value input to the internal dynamic circuit or ratio circuit becomes undefined, and more current may flow than during normal use. In that case, an MPU that uses a large amount of dynamic circuits, ratio circuits, etc., may have a large current flowing during the BT test, and the internal wiring and bonding wires may be destroyed by the heat generated by the large current flowing. is there.

For the above reason, recently, by inputting a clock and a reset signal from the outside at the time of the BT test, the value input to the gate of the dynamic circuit or the ratio circuit used internally is fixed, and the MPU at the time of the BT test. It reduces the current flowing through. There are several methods for generating the external clock and the reset signal, and the generally used method is to test the M under test from the outside of the BT furnace.
This is a method of inputting a clock and a reset signal to the MPU under test to the OU. This circuit diagram is shown in FIG.

[0005] Similarly, a method often used is BT.
Mount the oscillator and counter together with the MPU on the board, input the clock output from the oscillator to the counter, divide the clock in the counter, and reset the result to the clock to actually operate the MPU under test. Enter as. This circuit diagram is shown in FIG.

[0006]

[Problems to be Solved by the Invention] clocked BT
At times, equipment for inputting a clock and a reset signal to the MPU under test from the outside of the BT furnace is very expensive, which hinders cost reduction in product development. Also,
When the oscillator for generating the clock mounted on the BT board together with the MPU under test or the counter fails before the MPU under test, the supply of the clock to the MPU under test stops and the inside of the MPU under test stops. There is a possibility that a large current will be generated and the internal circuit will be destroyed.

It is an object of the present invention to provide a microprocessor which can reduce the production equipment cost.

[0008]

A microprocessor according to the present invention comprises an external test terminal, a clock generator for generating a clock for operating an internal circuit when an active signal is input to the external test terminal, and a clock having an arbitrary phase. A clock driver for converting to, and a reset signal generator for generating a reset signal for initializing an internal circuit, and a clock generated by the clock generator when an active signal is input to an external test terminal, It has a function of operating an internal circuit according to a reset signal generated by a reset signal generator.

In addition to the circuit described above, a shift register for dividing the clock generated by the clock generator and a path connecting the data input / output terminal and the shift register are provided, and input to the shift register and the data input / output terminal. It has a function of programming the frequency of the clock generated inside the MPU using the existing value.

[0010]

EXAMPLE A first example of the present invention will be described with reference to FIG. When an inactive signal (logical value “0”) is input to the test terminal 1, the transfer gate G
1 is turned on and the transfer gate G2 is turned off. At this time, as the final output O1 of the clock generator 2, the output of P1 is a plurality of stages of inverters (In to I).
1: n is an odd number). That is, I
The logical value “1” is input as the input of 1, and the output value of In is the logical value “0” because the inverters in the odd stages are interposed.
Is input and an odd number of stages of inverters are input, so I
The output value of n becomes the logical value "0". Therefore, the output O1 of the clock generator 2 has the logical value "0".

Next, when an active signal (logical value "1") is input to the test terminal 1, the transfer gate G
1 is turned off, and the transfer gate G2 is turned on. At this time, the input of I1 is the value output from In, and the logical value "0" is input. Then, the output of In through the odd-numbered inverters becomes the logical value "1" and the value is input to I1, and the value of O1 becomes the logical value "1".

Next, since the input of I1 changes from the logical value "0" to the logical value "1", the outputs of In and O1 become the logical value "0" accordingly. By repeating the above operation, the output of O1 oscillates as 0 → 1 → 0 → 1 → 0 → 1 → 0 → 1 ...

Paying attention to the value of O1, the test terminal 1
It can be considered that the clock is being generated in the clock generator 2 while the active signal is input to the clock generator 2. Here, the output value of In is input to the internal clock driver 4 as a clock for operating the internal circuit of the MPU under test. (When the logic value "0" is input to the test terminal 1, the clock is input from the outside of the MPU under test through the clock terminal.) The reason why the circuit has a plurality of inverters (odd stages) Is to stabilize the circuit operation by delaying the output value of In input to I1, and to secure the high width / low width of the waveform of the clock finally output to some extent.

Next, the reset signal generator 3 will be described. This reset signal generator 3 has a k-ary up counter (k
= 2m: m is a natural number, and the circuit diagram is shown in FIG. ),
When the input value of the test terminal 1 is input via the delay element as the counter reset input and the active signal (when the logical value "0" is input to the test terminal 1) is input to the counter reset, the initial state is output. Value (Dm, D
The values of m-1, ..., D1, D0) are (0, 0, ..., 0,
0).

Next, an active signal for counter reset (when a logical value "1" is input to the test terminal 1)
When is input, the output value is 1 each time the clock is input.
When the clock is input in the state of (1, 1, ..., 1,1), the state returns to the state of (0, 0, ..., 0, 0), and while the clock is being input, the above The transition of m states is in progress.

Of the outputs of this reset signal generator 3,
Focusing on the output of Dm, it can be regarded as a signal divided into a width of 2 ^m times the input clock, and the output value of Dm is used as a signal for resetting the internal circuit of the MPU under test. (If the reset signal is active high, the logical sum is calculated with the value input to the external reset terminal, and if the active signal is low, the logical product is calculated with the value input to the external reset terminal. Is used as a final reset signal to reset the internal circuit. In this embodiment, the reset signal is active low.)
By preparing an arbitrary combinational circuit using the output value of each bit of the reset signal generator 3, the signal width of the reset signal and the generation timing can be freely changed. FIG. 3 shows a timing chart in the first embodiment.
Shown in.

A second embodiment of the present invention will be described with reference to FIG. The circuit diagram of FIG. 4 is similar to the circuit diagram of FIG. 1 except that the shift register 5 (having the same circuit configuration as the counter circuit. The circuit diagram is shown in FIG. 5) and the data bus terminal and the shift register 5 are connected. The path is added.

First, it is assumed that the value (01010101) is loaded from the data bus terminal into the shift register 5 (for simplification of description, the shift register 5 is composed of 8 bits). (The above data transfer is realized by wiring from the toggle switch of the BT board to the data bus terminal.) When an active signal (logical value "1") is input to the test terminal 1, the clock generator 2 outputs it. The value of the shift register 5 is rotated (to the right or to the left) every time the clock is input (rotate to the left in this embodiment). At this time, paying attention to the output value of any one bit (the leftmost bit in this embodiment) of the shift register 5, the output value transits like 1 → 0 → 1 → 0 → 1 → 0 → 1 ... To go. By inputting this value to the internal clock driver 4, the internal circuit of the MPU under test is operated. The method of generating the reset signal is the same as that shown in the first embodiment.

The advantage of this embodiment is that the operating frequency can be controlled to some extent by the value loaded in the shift register 5. For example, comparing the case where the value (0101 ... 0101) is loaded and the case where the value (0011 ... 0011) is loaded, the latter has an operating frequency of 1/2. Therefore, by varying the value loaded in the shift register 5, it is possible to estimate the relationship between the operating frequency and the withstand current of the internal circuit during the clocked BT test. The timing chart in this embodiment is shown in FIG.

[0020]

As described in the first embodiment of the present invention, when the MPU under test receives the active signal at the external test terminal, the clock for operating the internal circuit and the reset signal for initializing the internal circuit. Since it can be generated internally, the expensive equipment for inputting the clock reset signal to the MPU under test from the outside of the BT furnace becomes unnecessary, and the production equipment cost can be reduced.

Further, in the case where the oscillator and the counter, etc., which are problematic in the method of inserting the oscillator and the counter into the BT furnace together with the MPU to be tested, fail before the MPU to be tested, they are supplied to the MPU to be tested. The clock reset signal should not be supplied, and there is no possibility that the internal circuit will be destroyed by the MPU under test generating a large current, and the production yield of the MPU can be improved.

Further, as shown in the second embodiment of the present invention, a shift register for dividing the clock generated by the clock generator and a path connecting the data input / output terminal and the shift register are provided. By having the function of programming the frequency of the clock generated inside the MPU under test by using the values input to the shift register and the data input / output terminal, various properties (logic) Threshold, channel length, etc.), and cl
Conditions for locked / BT test (power supply voltage, external temperature, etc.)
Corresponding to the above, since the MPU under test can be operated at the frequency that operates at the most stable current value, it is possible to further improve the production yield as compared with the MPU shown in the first embodiment.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a reset signal generator in FIG.

3 is an operation waveform diagram in FIG.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

5 is an internal circuit diagram of the shift register in FIG.

FIG. 6 is a circuit diagram for each bit in FIG.

7 is an operation waveform diagram in FIG.

FIG. 8 is a circuit diagram showing a conventional example.

FIG. 9 is a circuit diagram showing another conventional example.

[Explanation of symbols]

 1 Test terminal 2 Clock generator 3 Reset signal generator 4 Internal clock driver

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G06F 7/00 11/22 330 B 9072-5B 15/78 510 K 7530-5L

Claims (2)

[Claims] 1. An external clock input terminal, an external test terminal, a clock generator controlled by a signal input to the external test terminal, and a signal input to the external test terminal and a clock generator. And a reset signal generator which is controlled by a clock and initializes an internal circuit. 2. A shift register for dividing a clock generated by a clock generator, and a path for loading arbitrary data from a data input / output terminal to the shift register are provided. 1. The microprocessor according to 1.