JPH0540802A - Layout design method - Google Patents

Abstract

(57) [Summary] [Purpose] To shorten the turnaround time to obtain the optimal placement. [Arrangement] Arrangement means 2 for arranging on the basis of logical connection information, rough wiring means 3 for obtaining a rough route based on the arrangement result, and delay analysis means 4 for inputting the result of rough wiring and performing delay analysis processing. As a result of delay analysis, delay analysis violation information output means 5 including information on paths that violate the delay constraint value and blocks forming the paths, and delay violation information are input, and the placement result of related blocks and blocks around them. Violating block clearing means 6 for clearing, and block rearranging means 7 for rearranging the block whose layout result has been cleared.
A layout design method characterized by including and.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design system for arranging blocks such as LSI and printed boards.

[0002]

2. Description of the Related Art A conventional layout designing method of this type focuses on the information obtained during layout processing, that is, the sum of virtual wiring lengths and the value of the histogram of connection demands, and then evaluates the layout. Detailed wiring was performed, the number of undistributed lines and delay violations were checked, and if not possible, the process was returned to the layout process and layout was performed again (reference: "CAD of logic device" IPSJ March 20, 1981). Issued day).

[0003]

In the above-described conventional layout design method, since the general wiring and the detailed wiring are proceeded after the layout design is completed, the accurate delay analysis information can be found only after the detailed wiring. Therefore, it is necessary for the designer to see it again, return to the layout design, change the parameters, specify the layout position of the specific block, repeat the layout / wiring process, and confirm the result.

However, in the detailed wiring, the processing time increases as the design scale increases, so the turnaround time until the final delay analysis information is obtained increases.
At the same time, it has the drawback of increasing the machine resources.

[0005]

The method of the present invention is based on the LS
In a layout design method for arranging blocks that are layout units of I, a printed board, etc., a layout means for performing layout based on logical connection information, a rough wiring means for obtaining a rough route based on the layout result, and a rough wiring result The delay analysis means for performing the delay analysis processing, the delay analysis result output means including the result of the delay analysis, the path violating the delay constraint value and the information of the blocks constituting the delay analysis value, and the delay violation information. , A violating block clearing means for clearing the placement result of the related block and the blocks around it and a block rearranging means for relocating the block whose placement result is cleared.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a layout design example for explaining the operation of this embodiment, and FIG. 3 shows delay violation information in this layout design example. Show. The following processing is composed of several processing procedures, which are controlled by the control procedure 1.

First, all the blocks are arranged by the arranging means 2 on the basis of the logical connection information 8 and the general route is generated by the general wiring means 3. The result is the placement result 9 respectively.
And the rough wiring result 10 is stored in a table or the like.

FIG. 2A shows a part of the logical connection information 7, which is arranged and subjected to a rough wiring process. FIG. 2B shows a rough wiring result.

Blocks 22 to 27 shown in FIG. 2A are arranged at positions (2, 1) to FIG. 2B, respectively.
It is arranged between (4, 2) and is roughly wired.
Although this rough wiring does not show a more accurate wiring route than the detailed wiring, it is much closer to the actual wiring route than the Manhattan length, and it is possible to obtain a much more accurate result in terms of line length and estimation. ..

Further, the rough wiring process has a feature that the processing time is much shorter than that of the detailed wiring process. Therefore, it can be said that performing the details of the placement based on the result of the rough wiring process is very effective in reducing the turnaround time.

Next, the delay analysis processing means 4 inputs the rough wiring result and performs delay analysis. The result is stored as a delay analysis result 11 in a table or the like. Here, delay analysis processing is performed for all paths.

Further, the delay analysis violation information output means 5 compares all the path information stored in the delay analysis result 11 with the delay constraint value, and the path information which does not satisfy the constraint value is the block name constituting it, It is output as the delay violation information 12 together with the net name. FIG. 3A shows a part of the delay violation information. Paths 1 to 3 are detected as violation information, and the block names of "from" and "to" forming the path, the names of transit blocks, and the like are described.

Further, by violating block clearing means 6,
Information is input from the delay violation information 12, the path of the block to be rearranged is determined, and the rearranged block information 13 is output by clearing the block and surrounding layout information.

Next, the block rearrangement means 7 rearranges only the blocks of the rearranged block information 13, outputs the result to the arrangement result 9, and repeats the processes after the above-described rough wiring means 3.

The result of the rearrangement and the schematic wiring is shown in FIG. Here, the blocks 22 to 27 are rearranged and rough wiring is performed. Further, delay violation information after block rearrangement is shown in FIG. Here, the delay violation information is displayed as "NONE", indicating that there is no violation at all. From this, it can be predicted that there will be no delay violation even in the final wiring result.

Further, as a result of evaluating the delay violation after the rearrangement by the above method, if the delay violation path still exists, the rearrangement block information 13 is output to repeat the above processing, It is possible to base the placement result obtained by eliminating the delay violation at the stage of the rough wiring process.

[0018]

As described above, according to the present invention, the delay analysis result is evaluated based on the rough wiring result information, the rearrangement block is obtained from the result, the arrangement of the block is cleared and the rearrangement is performed again, By repeating the rough wiring and evaluating the delay analysis result, there is an effect that the layout correction according to the detailed wiring result is unnecessary and the optimum layout can be obtained in a much shorter turnaround time.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 shows a wiring design example for explaining the operation of the embodiment shown in FIG.

3 shows delay violation information in the layout design example shown in FIG.

[Explanation of symbols]

 1 Control Means 2 Arrangement Means 3 General Wiring Means 4 Delay Analysis Means 5 Delay Analysis Information Output Means 6 Violation Block Clear Means 7 Block Rearrangement Means 8 Logical Connection Information 9 Placement Results 10 General Wiring Results 11 Delay Analysis Results 12 Delay Violation Information 13 Relocation block information 21 External terminals 22 to 27 blocks

Claims (1)

[Claims] 1. A layout design method for arranging blocks, which are layout units of an LSI, a printed circuit board, etc., and a layout means for performing layout based on logical connection information, and a rough wiring means for determining a rough route based on the layout result. , Delay analysis means for inputting the result of rough wiring and performing delay analysis processing, delay analysis violation information output means including information of paths that violate the delay constraint value and delay constraint values, and blocks constituting the delay analysis result, and delay Arrangement characterized by including violation block clearing means for inputting violation information and clearing the arrangement result of the related block and blocks around it, and block rearranging means for rearranging the block whose arrangement result has been cleared Design method.