JPH0541377A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0541377A JPH0541377A JP19634491A JP19634491A JPH0541377A JP H0541377 A JPH0541377 A JP H0541377A JP 19634491 A JP19634491 A JP 19634491A JP 19634491 A JP19634491 A JP 19634491A JP H0541377 A JPH0541377 A JP H0541377A
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- pellet
- semiconductor
- semiconductor device
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
半導体ペレットの周辺部に配置した金属配線部の構造に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a metal wiring portion arranged around a semiconductor pellet.
【0002】[0002]
【従来の技術】従来の半導体装置では、図3に示すよう
に、金属配線はLOCOS法により形成した厚いフィー
ルド酸化膜23上に複数の層間絶縁膜を積層した平坦部
に配置されることが多く、特に半導体ペレットの周辺部
に配置される信号線のバスラインや、電源線、GND線
として使用される金属配線は、回路ブロックの入出力線
となるポリシリコン配線やシリサイド配線の引き込み線
と交差する以外には、下地に凹凸のない平坦部に配置さ
れていた。2. Description of the Related Art In a conventional semiconductor device, as shown in FIG. 3, metal wiring is often arranged in a flat portion in which a plurality of interlayer insulating films are laminated on a thick field oxide film 23 formed by the LOCOS method. In particular, the bus lines of signal lines arranged in the peripheral portion of the semiconductor pellet, the metal wiring used as the power supply line and the GND line intersect with the lead-in lines of the polysilicon wiring and the silicide wiring which are the input / output lines of the circuit block. Other than that, it was arranged on a flat portion with no unevenness on the base.
【0003】金属配線上には物理的な衝撃や水分の侵入
による化学的な侵蝕から配線を保護するための、SiO
2 やPSG膜、Si3 N4 膜SiONなどで形成される
パッシベーション膜24が設けられている。On the metal wiring, SiO is used for protecting the wiring from physical impact and chemical corrosion due to invasion of moisture.
A passivation film 24 formed of 2 , PSG film, Si 3 N 4 film SiON, or the like is provided.
【0004】[0004]
【発明が解決しようとする課題】この従来の半導体装置
では、モールドパッケージに組み立てた場合、周囲の温
度変化に対する耐量を調べる温度サイクル試験を行なう
と、パッシベーション膜は封入樹脂と半導体ペレットと
で熱膨張率が異なるため、温度変化により封入樹脂と半
導体ペレットの界面に発生したズレ応力により、ペレッ
トコーナー部や、ペレット周辺部でパッシベーション膜
のクラックが発生し、耐湿性の低下をまねくという問題
があった。さらにひどい場合には、金属配線がずれたり
する不良もあった。In this conventional semiconductor device, when assembled in a mold package, when a temperature cycle test is carried out to check the resistance to ambient temperature changes, the passivation film is thermally expanded by the encapsulating resin and the semiconductor pellet. Due to different rates, the stress generated at the interface between the encapsulating resin and the semiconductor pellets due to temperature changes caused cracks in the passivation film at the pellet corners and pellet periphery, which led to a decrease in moisture resistance. . In the worst case, there was a defect that the metal wiring was displaced.
【0005】この不良は、集積度の向上と共にペレット
サイズが大きくなるほど顕著になってきており、信頼性
が悪化する、あるいはペレットコーナー部や周辺部に
は、金属配線を配置できないという不都合が生じてい
た。This defect becomes more remarkable as the pellet size becomes larger as the degree of integration is improved, and the reliability is deteriorated, or the metal wiring cannot be arranged at the pellet corner portion or the peripheral portion. It was
【0006】例えばペレットサイズが6μm×15μm
の場合、ペレットコーナー部から400μm以内、ペレ
ットの辺から100μm以内に金属配線を配置すること
ができないので、半導体ペレットの面積効率がよくない
という問題点があった。For example, the pellet size is 6 μm × 15 μm
In this case, since the metal wiring cannot be arranged within 400 μm from the pellet corner portion and within 100 μm from the side of the pellet, there is a problem that the area efficiency of the semiconductor pellet is not good.
【0007】[0007]
【課題を解決するための手段】本発明は、半導体ペレッ
トの絶縁膜上に設けられた金属配線と、前記金属配線を
覆うパッシベーション膜とを有する半導体装置におい
て、前記半導体ペレットの周辺部の前記金属配線の下部
に段差を設けたというものである。According to the present invention, in a semiconductor device having a metal wiring provided on an insulating film of a semiconductor pellet and a passivation film covering the metal wiring, the metal in the peripheral portion of the semiconductor pellet is provided. It is said that a step is provided below the wiring.
【0008】[0008]
【実施例】次に本発明の実施例について図面を参照して
説明する。Embodiments of the present invention will now be described with reference to the drawings.
【0009】図1は本発明の第1の実施例の半導体ペレ
ットの断面図である。1は金属配線,2は半導体基板,
3はフィールド酸化膜,4は層間膜、5はパッシベーシ
ョン膜を示す。FIG. 1 is a sectional view of a semiconductor pellet according to the first embodiment of the present invention. 1 is metal wiring, 2 is a semiconductor substrate,
3 is a field oxide film, 4 is an interlayer film, and 5 is a passivation film.
【0010】本実施例では、半導体基板2上に形成され
たフィールド酸化膜3を局所的に形成しないことにより
凹部を設け、その凹部によってできた段差上に、電源配
線などの金属配線1を形成してある。樹脂と半導体ペレ
ットの界面で生じる横方向のズレ応力を、段差部で受け
とめることによりパッシベーション膜5のクラックの発
生を防止し、さらに金属配線1のズレを防ぐことができ
る。従って、半導体装置の信頼性の改善ができる。ある
いは、ペレットコーナー部から400μm以内、ペレッ
トの辺から100μm以内の周辺部に金属配線を設ける
ことが可能となり、半導体ペレットの面積効率を改善も
可能である。In this embodiment, the field oxide film 3 formed on the semiconductor substrate 2 is not locally formed to form a recess, and the metal wiring 1 such as a power supply wiring is formed on the step formed by the recess. I am doing it. By receiving the lateral displacement stress generated at the interface between the resin and the semiconductor pellet at the step portion, it is possible to prevent cracking of the passivation film 5 and further prevent the displacement of the metal wiring 1. Therefore, the reliability of the semiconductor device can be improved. Alternatively, it is possible to provide metal wiring within 400 μm from the corner portion of the pellet and within 100 μm from the side of the pellet, thereby improving the area efficiency of the semiconductor pellet.
【0011】なお、前述の凹部は、金属配線1の幅の半
分程度の幅で、金属配線に沿った溝にしてもよいが、必
ずしも連続した溝とする必要はない。The above-mentioned recess may be a groove having a width of about half the width of the metal wiring 1 and extending along the metal wiring, but it is not always required to be a continuous groove.
【0012】図2は本発明の第2の実施例の半導体ペレ
ットの断面図である。11は金属配線,12は半導体基
板,13はフィールド酸化膜,14は層間膜,15はパ
ッシベーション膜,16は多結晶シリコン膜を示す。FIG. 2 is a sectional view of a semiconductor pellet according to the second embodiment of the present invention. Reference numeral 11 is a metal wiring, 12 is a semiconductor substrate, 13 is a field oxide film, 14 is an interlayer film, 15 is a passivation film, and 16 is a polycrystalline silicon film.
【0013】本実施例では、半導体基板12上に金属配
線11より幅の細い、厚さ0.2μm程度の多結晶シリ
コン膜13を形成し、その上をおおうように金属配線1
1を形成する。多結晶シリコン膜13による段差によ
り、樹脂とペレットの界面で生じる横方向にズレ応力を
段差部で受けとめることにより、パッシベーション膜の
クラックを防止し、さらに金属配線11のズレを防ぐこ
とができる。また、多結晶シリコン膜13ではなくて
も、金属配線11の下層に設けられるものであれば絶縁
膜でもよい。In this embodiment, a polycrystalline silicon film 13 having a thickness of about 0.2 μm, which is narrower than the metal wiring 11 is formed on the semiconductor substrate 12, and the metal wiring 1 is formed so as to cover the polycrystalline silicon film 13.
1 is formed. By the step due to the step due to the polycrystalline silicon film 13, the lateral stress generated at the interface between the resin and the pellet is received at the step, so that the crack of the passivation film can be prevented and the deviation of the metal wiring 11 can be prevented. Further, instead of the polycrystalline silicon film 13, an insulating film may be used as long as it is provided in the lower layer of the metal wiring 11.
【0014】[0014]
【発明の効果】以上説明したように本発明は、応力集中
の大きいペレット周辺部の金属配線の下に、少なくとも
1つの段差を設けることにより、段差部で金属配線に加
わる横方向の応力をささえるので、パッシベーション膜
のクラックや金属配線のズレ等を防ぐことができ、半導
体ペレットの面積効率の改善あるいは半導体装置の信頼
性の向上がもたらされる効果がある。As described above, according to the present invention, by providing at least one step below the metal wiring around the pellet where the stress concentration is large, the lateral stress applied to the metal wiring at the step is suppressed. Therefore, it is possible to prevent cracks in the passivation film, deviations in the metal wiring, etc., and it is possible to improve the area efficiency of the semiconductor pellet or the reliability of the semiconductor device.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明の第1の実施例を示す断面図である。FIG. 1 is a cross-sectional view showing a first embodiment of the present invention.
【図2】本発明の第2の実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the present invention.
【図3】従来例を示す断面図である。FIG. 3 is a cross-sectional view showing a conventional example.
1,11,21 金属配線 2,12,22 半導体基板 3,13,23 フィールド酸化膜 4,14 層間膜 5,15,24 パッシベーション膜 16 多結晶シリコン膜 1,11,21 Metal wiring 2,12,22 Semiconductor substrate 3,13,23 Field oxide film 4,14 Interlayer film 5,15,24 Passivation film 16 Polycrystalline silicon film
Claims (2)
金属配線と、前記金属配線を覆うパッシベーション膜と
を有する半導体装置において、前記半導体ペレットの周
辺部の前記金属配線の下部に段差を設けたことを特徴と
する半導体装置。1. A semiconductor device having a metal wiring provided on an insulating film of a semiconductor pellet and a passivation film covering the metal wiring, wherein a step is provided below the metal wiring in a peripheral portion of the semiconductor pellet. A semiconductor device characterized by the above.
部による段差部を覆って金属配線を設けた請求項1記載
の半導体装置。2. The semiconductor device according to claim 1, wherein the metal wiring is provided so as to cover the step portion formed by the concave portion locally formed in the field oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19634491A JPH0541377A (en) | 1991-08-06 | 1991-08-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19634491A JPH0541377A (en) | 1991-08-06 | 1991-08-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0541377A true JPH0541377A (en) | 1993-02-19 |
Family
ID=16356277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19634491A Pending JPH0541377A (en) | 1991-08-06 | 1991-08-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0541377A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007012712A (en) * | 2005-06-28 | 2007-01-18 | Rohm Co Ltd | Semiconductor device and manufacturing method of semiconductor device |
| JP2009027139A (en) * | 2007-04-30 | 2009-02-05 | Infineon Technologies Ag | Fixing structure and mating structure |
| US8575764B2 (en) | 2004-11-16 | 2013-11-05 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US9076821B2 (en) | 2007-04-30 | 2015-07-07 | Infineon Technologies Ag | Anchoring structure and intermeshing structure |
| CN119517844A (en) * | 2025-01-21 | 2025-02-25 | 粤芯半导体技术股份有限公司 | Semiconductor device and method for manufacturing the same |
-
1991
- 1991-08-06 JP JP19634491A patent/JPH0541377A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9601441B2 (en) | 2004-11-16 | 2017-03-21 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US12057362B2 (en) | 2004-11-16 | 2024-08-06 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US9111819B2 (en) | 2004-11-16 | 2015-08-18 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US8575764B2 (en) | 2004-11-16 | 2013-11-05 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US8786106B2 (en) | 2004-11-16 | 2014-07-22 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US8928156B2 (en) | 2004-11-16 | 2015-01-06 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US9312228B2 (en) | 2004-11-16 | 2016-04-12 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US11069591B2 (en) | 2004-11-16 | 2021-07-20 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US10431516B2 (en) | 2004-11-16 | 2019-10-01 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| JP2007012712A (en) * | 2005-06-28 | 2007-01-18 | Rohm Co Ltd | Semiconductor device and manufacturing method of semiconductor device |
| JP2009027139A (en) * | 2007-04-30 | 2009-02-05 | Infineon Technologies Ag | Fixing structure and mating structure |
| US9076821B2 (en) | 2007-04-30 | 2015-07-07 | Infineon Technologies Ag | Anchoring structure and intermeshing structure |
| JP2012119711A (en) * | 2007-04-30 | 2012-06-21 | Infineon Technologies Ag | Anchoring structure and fitting structure |
| CN119517844A (en) * | 2025-01-21 | 2025-02-25 | 粤芯半导体技术股份有限公司 | Semiconductor device and method for manufacturing the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19991130 |