JPH0541386A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0541386A JPH0541386A JP3195593A JP19559391A JPH0541386A JP H0541386 A JPH0541386 A JP H0541386A JP 3195593 A JP3195593 A JP 3195593A JP 19559391 A JP19559391 A JP 19559391A JP H0541386 A JPH0541386 A JP H0541386A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- impurity concentration
- epitaxial wafer
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bipolar Transistors (AREA)
Abstract
(57)【要約】 (修正有)
【目的】エピタキシャル成長のために不純物濃度に制約
のある基板を有するエピタキシャルウエーハを用いた場
合に、裏面上に形成される金属電極との間に良好なオー
ミック接触がとれる半導体素子の製造方法を提供する。
【構成】エピタキシャルウエーハ1の比抵抗の高い基板
11の裏面にイオン注入することによって、基板裏面の
1μm程度の深さの表面層の不純物濃度を1020cm-3程度
にすることにより、金属電極との良好なオーム接触が形
成でき、素子のオン電圧を改善する。
(57) [Summary] (Modified) [Purpose] Good ohmic contact with the metal electrode formed on the back surface when an epitaxial wafer having a substrate with a restricted impurity concentration for epitaxial growth is used. Provided is a method for manufacturing a semiconductor device capable of obtaining the above. [Structure] By implanting ions into the back surface of the substrate 11 having a high resistivity of the epitaxial wafer 1, the impurity concentration of the surface layer at a depth of about 1 μm on the back surface of the substrate is set to about 10 20 cm −3 , whereby the metal electrode is formed. A good ohmic contact with can be formed, improving the on-voltage of the device.
Description
【0001】[0001]
【産業上の利用分野】本発明は、第一導電型の半導体基
板上に第二導電型の半導体層をエピタキシャル成長させ
たエピタキシャルウエーハを用いる半導体素子の製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using an epitaxial wafer in which a semiconductor layer of a second conductivity type is epitaxially grown on a semiconductor substrate of a first conductivity type.
【0002】[0002]
【従来の技術】エピタキシャル法を用いれば、半導体基
板の上に任意の不純物濃度で任意の導電型の半導体層を
任意の厚さで形成でき、内部欠陥の少ない結晶層を得る
ことができるので、エピタキシャルウエーハを半導体素
子の製造に用いることがしばしば行われる。2. Description of the Related Art If an epitaxial method is used, a semiconductor layer of an arbitrary conductivity type and an arbitrary thickness can be formed on a semiconductor substrate, and a crystal layer with few internal defects can be obtained. Epitaxial wafers are often used for manufacturing semiconductor devices.
【0003】[0003]
【発明が解決しようとする課題】しかし、基板と異なる
導電型の層をエピタキシャル成長させる場合には、基板
の不純物濃度が高いと、成長中の不純物拡散によりエピ
タキシャル層の不純物濃度にばらつきが生じ、導電型あ
るいは不純物濃度を所期のようにすることが難しくなる
ので、基板の不純物濃度を十分に高くすることができな
いことがある。このため、基板の比抵抗が基板の裏面上
に形成される金属電極とオーミック接触をとれるほど低
くできない問題が生ずる。従って製造された半導体素子
の導通時の素子電極間の電圧降下、すなわちオン電圧を
低くすることができなくなる。However, when a layer of a conductivity type different from that of the substrate is epitaxially grown, if the impurity concentration of the substrate is high, the impurity concentration of the epitaxial layer varies due to diffusion of impurities during growth, and the conductivity Since it is difficult to set the mold or the impurity concentration to a desired level, it may not be possible to sufficiently increase the impurity concentration of the substrate. For this reason, there arises a problem that the specific resistance of the substrate cannot be low enough to make ohmic contact with the metal electrode formed on the back surface of the substrate. Therefore, it becomes impossible to reduce the voltage drop between the device electrodes when the manufactured semiconductor device is conductive, that is, the on-voltage.
【0004】本発明の目的は、エピタキシャル成長のた
めに不純物濃度に制約のある基板を有するエピタキシャ
ルウエーハを用いた場合に、裏面上に形成される金属電
極との間に良好なオーミック接触のとれる半導体素子の
製造方法を提供することにある。An object of the present invention is to provide a semiconductor device which can obtain good ohmic contact with a metal electrode formed on the back surface when an epitaxial wafer having a substrate with a restricted impurity concentration is used for epitaxial growth. It is to provide a manufacturing method of.
【0005】[0005]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、第一導電型の半導体基板の一面上に第
二導電型の半導体層を成長させたエピタキシャルウエー
ハを用いる半導体素子の製造方法において、基板の他面
からイオン注入を行う工程を含むものとする。そして、
エピタキシャルウエーハ基板の不純物濃度が1×1019cm
-3以下であり、イオン注入される表面層の不純物濃度が
8×1019cm-3以上であることが効果的である。また半導
体素子が絶縁ゲート型バイポーラトランジスタ (以下I
GBTと記す) であることが有効である。In order to achieve the above object, the present invention provides a semiconductor device using an epitaxial wafer in which a semiconductor layer of the second conductivity type is grown on one surface of a semiconductor substrate of the first conductivity type. In the manufacturing method of 1., the step of performing ion implantation from the other surface of the substrate is included. And
The impurity concentration of the epitaxial wafer substrate is 1 × 10 19 cm
-3 or less, and it is effective that the impurity concentration of the ion-implanted surface layer is 8 × 10 19 cm -3 or more. In addition, the semiconductor element is an insulated gate bipolar transistor (hereinafter referred to as I
(Referred to as GBT) is effective.
【0006】[0006]
【作用】エピタキシャルウエーハの半導体基板エピタキ
シャル層と反対側の裏面にイオン注入することにより、
半導体基板の抵抗が高くても基板の裏面上の金属電極と
良好なオーミック接触をとることができる。[Operation] By implanting ions into the back surface of the epitaxial wafer on the side opposite to the semiconductor substrate epitaxial layer,
Even if the resistance of the semiconductor substrate is high, good ohmic contact can be made with the metal electrode on the back surface of the substrate.
【0007】[0007]
【実施例】図1は本発明の一実施例により製造されたI
GBTを示す。このIGBTの製造には、不純物濃度10
19cm-3程度のp型基板11の上n- 層12を成長させたシリ
コンエピタキシャルウエーハ1を用いる。このウエーハ
のn- 層12の上に絶縁膜を介して多結晶シリコンからな
るゲート電極2のパターンを形成し、このゲート電極2
をマスクとして利用してのイオン注入, 熱拡散によりp
ウエル3およびその表面層内のn+ ソース領域4を形成
する。このpウエル3およびn+ 領域4は図示しないソ
ース電極をオーミック接触させるためその表面不純物濃
度が1×1020cm-3程度以上になるようにする。一方、図
示しないドレイン電極の接触するp基板11の裏面には基
板の不純物濃度に応じてほう素イオン5を50〜100keVの
加速電圧、1×1015〜1×1016cm-2のドーズ量で注入
し、表面から1μm程度の深さの表面層の不純物濃度
を、1×1020cm-3程度、少なくとも8×1019cm-3以上に
なるようにする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an I manufactured according to an embodiment of the present invention.
Shows GBT. For manufacturing this IGBT, the impurity concentration is 10
A silicon epitaxial wafer 1 having an n − layer 12 grown on a p-type substrate 11 of about 19 cm −3 is used. A pattern of the gate electrode 2 made of polycrystalline silicon is formed on the n − layer 12 of this wafer through an insulating film.
Is used as a mask for ion implantation and thermal diffusion.
The well 3 and the n + source region 4 in the surface layer thereof are formed. The p-well 3 and the n + region 4 have a surface impurity concentration of about 1 × 10 20 cm −3 or more in order to make ohmic contact with a source electrode (not shown). On the other hand, on the back surface of the p-substrate 11 which is in contact with the drain electrode (not shown), boron ions 5 are accelerated at a accelerating voltage of 50 to 100 keV and a dose amount of 1 × 10 15 to 1 × 10 16 cm -2 depending on the impurity concentration of the substrate. And the impurity concentration of the surface layer having a depth of about 1 μm from the surface is set to about 1 × 10 20 cm −3 , at least 8 × 10 19 cm −3 or more.
【0008】図2はほう素イオン注入のドーズ量とでき
上がった定格600 V, 50AのIGBTのオン電圧との関
係を示す。これによると従来のエピタキシャルウエーハ
を用いて製造したIGBTにくらべて電圧が約40%低下
し、1.7Vになった。また、オン電圧のばらつきも、従
来のIGBTでは平均値の40%程度であったものが、本
発明の実施例によるIGBTでは20%に抑えることがで
きた。なお、上記の実施例はnチャネルIGBTを製造
したが、pチャネルIGBTでも同様に実施でき、その
場合はりんイオンを同程度のドーズ量で注入する。FIG. 2 shows the relationship between the dose amount of boron ion implantation and the ON voltage of the completed IGBT of rated 600 V and 50 A. According to this, compared with the IGBT manufactured using the conventional epitaxial wafer, the voltage decreased by about 40% to 1.7V. Further, the variation of the ON voltage was about 40% of the average value in the conventional IGBT, but could be suppressed to 20% in the IGBT according to the embodiment of the present invention. In addition, although an n-channel IGBT is manufactured in the above-described embodiment, a p-channel IGBT can be similarly implemented, and in that case, phosphorus ions are implanted at a similar dose amount.
【0009】[0009]
【発明の効果】本発明によれば、異なる導電型のエピタ
キシャル層への不純物の混入を防ぐために不純物濃度を
抑えた基板を有するエピタキシャルウエーハの基板裏面
の表面層にイオン注入することにより、基板裏面への金
属電極の良好なオーミック接触が得ることができた。こ
れにより、オン電圧が低く、そのばらつきの少ない半導
体素子を従来の設備を用いて製造することが可能になっ
た。According to the present invention, in order to prevent impurities from being mixed into epitaxial layers of different conductivity types, ions are implanted into the surface layer on the back surface of the substrate of an epitaxial wafer having a substrate with a reduced impurity concentration, so that the back surface of the substrate is Good ohmic contact of the metal electrode to the can be obtained. As a result, it has become possible to manufacture a semiconductor element having a low on-voltage and a small variation in the on-voltage using conventional equipment.
【図1】本発明の一実施例によって製造されたIGBT
の断面図FIG. 1 is an IGBT manufactured according to an embodiment of the present invention.
Cross section
【図2】エピタキシャルウエーハ裏面へのイオン注入ド
ーズ量と製造されたIGBTのオン電圧との関係線図FIG. 2 is a diagram showing the relationship between the dose of ion implantation on the back surface of an epitaxial wafer and the on-voltage of a manufactured IGBT.
1 エピタキシャルウエーハ 11 p基板 12 n- エピタキシャル層 2 ゲート電極 3 pウエル 4 n+ ソース領域 5 ほう素イオン1 Epitaxial Wafer 11 p Substrate 12 n - Epitaxial Layer 2 Gate Electrode 3 p Well 4 n + Source Region 5 Boron Ion
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/784 9168−4M H01L 29/78 321 J ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication H01L 29/784 9168-4M H01L 29/78 321 J
Claims (3)
電型の半導体層を成長させたエピタキシャルウエーハを
用いる半導体素子の製造方法において、基板の他面から
イオン注入を行う工程を含むことを特徴とする半導体素
子の製造方法。1. A method of manufacturing a semiconductor device using an epitaxial wafer in which a semiconductor layer of a second conductivity type is grown on one surface of a semiconductor substrate of a first conductivity type, including a step of implanting ions from the other surface of the substrate. A method of manufacturing a semiconductor device, comprising:
が1×1019cm-3以下であり、イオン注入される表面層の
不純物濃度が8×1019cm-3以上である請求項1記載の半
導体素子の製造方法。2. The semiconductor device according to claim 1, wherein the epitaxial wafer substrate has an impurity concentration of 1 × 10 19 cm −3 or less, and the ion-implanted surface layer has an impurity concentration of 8 × 10 19 cm −3 or more. Manufacturing method.
ンジスタである請求項1あるいは2記載の半導体素子の
製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is an insulated gate bipolar transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3195593A JPH0541386A (en) | 1991-08-06 | 1991-08-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3195593A JPH0541386A (en) | 1991-08-06 | 1991-08-06 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0541386A true JPH0541386A (en) | 1993-02-19 |
Family
ID=16343733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3195593A Pending JPH0541386A (en) | 1991-08-06 | 1991-08-06 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0541386A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7740519B2 (en) | 2003-04-16 | 2010-06-22 | Kabushiki Kaisha Topcon | Method for processing chamfering of eyeglass lens and apparatus for processing the same |
-
1991
- 1991-08-06 JP JP3195593A patent/JPH0541386A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7740519B2 (en) | 2003-04-16 | 2010-06-22 | Kabushiki Kaisha Topcon | Method for processing chamfering of eyeglass lens and apparatus for processing the same |
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