JPH0541454A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0541454A JPH0541454A JP19635391A JP19635391A JPH0541454A JP H0541454 A JPH0541454 A JP H0541454A JP 19635391 A JP19635391 A JP 19635391A JP 19635391 A JP19635391 A JP 19635391A JP H0541454 A JPH0541454 A JP H0541454A
- Authority
- JP
- Japan
- Prior art keywords
- layer electrode
- contact
- lower layer
- electrode
- isolation region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は多層電極を有する半導体
装置に関し、特に素子分離領域に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer electrode, and more particularly to an element isolation region.
【0002】[0002]
【従来の技術】従来の半導体装置を図2を用いて説明す
る。従来の半導体の素子分離領域は、シリコン基板1の
選択酸化による厚い酸化ケイ素膜(以下酸化膜と称す)
2で形成されていた。そして図2(a)に示すように、
まず、下層の電極4が形成され、次に酸化膜により、そ
の上層との層間絶縁膜5が形成されていた。そして図2
(b)に示す様に素子分離領域上で下層の電極4と上層
の電極6を接続するコンタクトが形成され、その上に上
層の電極6が形成され図2(c)となる。2. Description of the Related Art A conventional semiconductor device will be described with reference to FIG. The element isolation region of a conventional semiconductor is a thick silicon oxide film (hereinafter referred to as an oxide film) formed by selective oxidation of the silicon substrate 1.
It was formed of 2. Then, as shown in FIG.
First, the lower layer electrode 4 was formed, and then the interlayer insulating film 5 with the upper layer was formed by the oxide film. And Figure 2
As shown in FIG. 2B, a contact for connecting the lower layer electrode 4 and the upper layer electrode 6 is formed on the element isolation region, and the upper layer electrode 6 is formed thereon, as shown in FIG. 2C.
【0003】[0003]
【発明が解決しようとする課題】この従来の素子分離領
域上で上層電極と下層電極とを接続するコンタクトを形
成する時に、上層電極と下層電極の間の層間絶縁膜と素
子分離領域となる厚い絶縁膜が同じ酸化膜である為、コ
ンタクト形成の為のマスクとなるフォトレジストと下層
電極にズレが生じた場合や、コンタクト形成の為の酸化
膜のエッチングが過剰になった場合にコンタクトがシリ
コン基板にまで達してしまい図4に示す様に上層電極及
び下層電極がシリコン基板と接続されてしまい、製造歩
留の低下を引き起こす問題点があった。When forming a contact for connecting an upper layer electrode and a lower layer electrode on this conventional element isolation region, a thick interlayer insulating film between the upper layer electrode and the lower layer electrode and the element isolation region are formed. Since the insulating film is the same oxide film, the contact becomes silicon when the photoresist that serves as a mask for contact formation and the lower layer electrode are misaligned or when the oxide film for contact formation is excessively etched. There is a problem in that the substrate reaches the substrate and the upper electrode and the lower electrode are connected to the silicon substrate as shown in FIG. 4, resulting in a decrease in manufacturing yield.
【0004】本発明の目的は、素子分離領域上での配線
間の接続において、接続のためのコンタクトと下層電極
とのずれにより各電極がシリコン基板と接続されること
を防ぎ、製造歩留を向上させることが出来る半導体装置
を提供することにある。An object of the present invention is to prevent each electrode from being connected to a silicon substrate due to a displacement between a contact for connection and a lower layer electrode in connection between wirings on an element isolation region, thereby improving manufacturing yield. It is to provide a semiconductor device that can be improved.
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置は素
子分離領域において素子分離領域となる厚い酸化膜上に
窒化ケイ素膜(以下窒化膜と称す)が形成されている。In a semiconductor device of the present invention, a silicon nitride film (hereinafter referred to as a nitride film) is formed on a thick oxide film which will be an element isolation region in an element isolation region.
【0006】[0006]
【実施例】次に本発明を図面を参照して説明する。図1
は本発明の一実施例およびその製造方法を説明するため
に工程順に示した半導体素子の断面図である。まず図1
(a)に示す様にシリコン基板1の選択酸化により素子
分離領域となる厚い酸化膜2を形成し、その上に窒化膜
層3を形成する。次にフォトリソグラフィ技術を用いて
窒化膜を選択的にエッチングして図1(b)の様に窒化
膜3を素子分離領域上にのみ残す。その後図1(c)に
示す様に、下層の電極4と上層の電極との間の層間酸化
膜5を形成後、上層の電極6と下層の電極4を接続する
為のコンタクトをフォトレジストをマスクとして層間酸
化膜5を選択的にエッチングして形成する。そしてその
上に上層電極6を形成すると図1(d)に示す一実施例
が完成する。The present invention will be described below with reference to the drawings. Figure 1
FIG. 3 is a cross-sectional view of a semiconductor device shown in order of steps for explaining an embodiment of the present invention and a manufacturing method thereof. Figure 1
As shown in (a), a thick oxide film 2 to be an element isolation region is formed by selective oxidation of the silicon substrate 1, and a nitride film layer 3 is formed thereon. Next, the nitride film is selectively etched by using the photolithography technique to leave the nitride film 3 only on the element isolation region as shown in FIG. After that, as shown in FIG. 1C, after forming an interlayer oxide film 5 between the lower electrode 4 and the upper electrode, a contact for connecting the upper electrode 6 and the lower electrode 4 is formed with a photoresist. Interlayer oxide film 5 is selectively etched and formed as a mask. Then, when the upper layer electrode 6 is formed thereon, the embodiment shown in FIG. 1D is completed.
【0007】[0007]
【発明の効果】以上説明した様に、本発明は素子分離領
域となる厚い酸化膜上を窒化膜で覆っているので、図3
に示す様に下層電極とコンタクトがずれた場合でもコン
タクト形成の為の酸化膜エッチングが窒化膜のところで
止まり上層電極,下層電極がシリコン基板と接続される
事がない。これにより、コンタクトと下層電極のずれに
よる製造歩留の低下を防ぐという効果を有する。As described above, according to the present invention, the thick oxide film serving as the element isolation region is covered with the nitride film.
Even if the contact with the lower layer electrode is deviated as shown in FIG. 5, the oxide film etching for forming the contact does not stop at the nitride film and the upper layer electrode and the lower layer electrode are not connected to the silicon substrate. This has the effect of preventing a decrease in manufacturing yield due to a displacement between the contact and the lower layer electrode.
【図1】本発明の一実施例およびその製造方法を説明す
るために工程順に示した半導体素子の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device shown in order of steps for explaining an embodiment of the present invention and a manufacturing method thereof.
【図2】従来の半導体素子および製造方法を説明するた
めに工程順に示した半導体素子の一例の断面図である。FIG. 2 is a cross-sectional view of an example of a semiconductor element shown in the order of steps for explaining a conventional semiconductor element and a manufacturing method.
【図3】本発明の一実施例で下層電極とコンタクトがず
れた場合の断面図である。FIG. 3 is a cross-sectional view showing a case where the lower electrode and the contact are misaligned in one embodiment of the present invention.
【図4】従来の半導体素子で下層電極とコンタクトがず
れた場合の断面図である。FIG. 4 is a cross-sectional view of a conventional semiconductor element in which a contact with a lower electrode is displaced.
1 半導体基板 2 厚い酸化ケイ素膜 3 窒化ケイ素膜 4 下層電極 5 層間酸化ケイ素膜 6 上層電極 1 Semiconductor Substrate 2 Thick Silicon Oxide Film 3 Silicon Nitride Film 4 Lower Layer Electrode 5 Interlayer Silicon Oxide Film 6 Upper Layer Electrode
Claims (1)
領域において、前記素子分離領域となる厚い酸化ケイ素
膜上を窒化ケイ素膜が覆っている事を特徴とする半導体
装置。1. A semiconductor device, wherein in a device isolation region of a semiconductor device having a multilayer electrode, a silicon nitride film covers a thick silicon oxide film to be the device isolation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19635391A JPH0541454A (en) | 1991-08-06 | 1991-08-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19635391A JPH0541454A (en) | 1991-08-06 | 1991-08-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0541454A true JPH0541454A (en) | 1993-02-19 |
Family
ID=16356433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19635391A Pending JPH0541454A (en) | 1991-08-06 | 1991-08-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0541454A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07115128A (en) * | 1993-10-15 | 1995-05-02 | Nippondenso Co Ltd | Insulator separated semiconductor device |
| KR100244272B1 (en) * | 1997-04-17 | 2000-03-02 | 김영환 | Method for forming isolation hayer in semiconductor device |
-
1991
- 1991-08-06 JP JP19635391A patent/JPH0541454A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07115128A (en) * | 1993-10-15 | 1995-05-02 | Nippondenso Co Ltd | Insulator separated semiconductor device |
| KR100244272B1 (en) * | 1997-04-17 | 2000-03-02 | 김영환 | Method for forming isolation hayer in semiconductor device |
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