JPH0541480A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the destruction of the gate of a MOS transistor in an LSI in case a high potential difference is generated between a power source and GND by mistake at the time of using the LSI. CONSTITUTION:The power supply line 1 of a chip is connected to the collector terminal of an NPN transistor 3 through a signal line 6 and the GND line 2 of the chip is connected to the emitter terminal of the transistor 3 through another signal line 7. The base of the transistor 3 is connected to a potential difference setting circuit 5. In case a potential difference which is larger than the potential difference set between the power supply and GND lines 1 and 2 by means of the circuit 5, a potential is applied across the base terminal of the transistor 3 and an electric current is generated between the lines 1 and 2, resulting in a voltage drop through the line 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a MOS transistor.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit device composed of MOS transistors, the voltage difference supplied to its power supply and GND terminal is directly supplied between the gates of the MOS transistors on the semiconductor chip.

[0003]

In such a conventional semiconductor integrated circuit device, the potential difference supplied between the power source and the GND terminal is directly supplied between the gates of the MOS transistors on the chip. When a potential higher than the absolute rating was erroneously supplied to the power supply terminal, the gate of the internal transistor was destroyed.

In recent years, the gate width of MOS transistors has become narrower with the increase in the scale of LSIs, and it is expected that troubles due to this case will frequently occur.

An object of the present invention is to provide a semiconductor integrated circuit device in which gate breakdown due to a power supply voltage does not occur.

[0006]

According to the structure of the present invention, a power source line and a GND line are wired on a semiconductor chip, and M
In a semiconductor integrated circuit device composed of OS transistors, a means for lowering the voltage of the power supply and bringing the voltage closer to the specified potential difference when a potential difference greater than the specified potential difference occurs between the power supply line and the GND line is provided. To do.

[0007]

1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention.

In FIG. 1, in this embodiment, the power supply line 1 on the LSI chip is connected to the collector terminal of the NPN transistor 3 via the signal line 6.

The GND line 2 is connected to the emitter terminal of the transistor 3 via the signal line 7. The base terminal of the transistor 3 has an N channel M
It is connected to a potential difference setting circuit 5 in which five OS transistors 4 are connected in series.

In this embodiment, the power supply line 1 of the chip
When a normal potential difference is supplied between the power supply line 1 and the GND line 2, the base potential of the NPN transistor 3 from the power supply line 1 is one N-channel transistor.
The potential that is dropped by the threshold voltage is supplied.

Here, assuming that the total value of the threshold voltages of five transistors and the recommended operating voltage value are the same,
The base potential of the NPN transistor 3 is almost the same as the GND level 2, so that the collector-emitter current of the transistor 3 is not generated and does not affect the potential difference between the power supply and the GND lines 1 and 2.

However, when a potential difference of more than the recommended operating voltage occurs between the power supply line 1 and the GND line 2, the threshold voltage of five N-channel transistors 4 is exceeded, and therefore the base of the NPN transistor 3 is exceeded. A potential higher than that of the GND line 2 is supplied to the terminal, a power source is generated between the collector and the emitter of the transistor, and a voltage drop in the power source line 1 due to this is expected, so that the power source, the GND line 1,
The potential difference between the two can be reduced.

As described above, the semiconductor integrated circuit device of this embodiment is provided with a circuit for reducing the potential difference between the power supply of the chip and the GND line when the potential difference of the specified potential difference or more occurs.

[0014]

As described above, according to the present invention, when a potential difference more than the specified potential difference occurs between the power supply line of the chip and the GND line, the means for reducing the potential difference is provided. Even if a potential difference above the absolute rating is erroneously supplied to the power supply and GND terminal of the chip during use, the potential difference can be reduced on the chip, and the gate breakdown phenomenon of the internal transistor can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention.

[Explanation of symbols]

 1 power supply line 2 GND line 3 NPN type transistor 4 N channel type MOS transistor 5 potential difference setting circuit 6, 7 signal line

Claims (1)

[Claims] 1. A power supply line and a GND on a semiconductor chip.
In a semiconductor integrated circuit device in which lines are wired and configured by MOS transistors, means for lowering the voltage of the power supply and bringing the voltage closer to the specified potential difference when a potential difference greater than the specified potential difference occurs between the power supply line and the GND line A semiconductor integrated circuit device characterized by the above.