JPH0541489A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Structure] The bipolar transistor BT and the field effect transistors NFET and PFET are formed on the light-transmissive glass substrate 2, and the island-shaped single crystal layer 6, which constitutes the active region of these transistors, is formed. The steps 8 and 10 include a step of bonding the surface of the non-porous single crystal layer on the porous silicon substrate or the oxidized surface thereof to the glass substrate 2 and then wet-etching the porous silicon substrate. It was obtained by removing by. [Effect] A bipolar transistor BT with a reduced capacitance between the glass substrate 2 and the collector, and an insulated gate field effect transistor NFET, PFET with a reduced floating capacitance of the source S and drain D can be produced, and these are combined. Thus, it is possible to provide a circuit which is capable of high-speed operation, has no latch-up phenomenon, and is free of soft errors due to α rays and has excellent radiation resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bipolar transistor and a field effect transistor, and more particularly to a semiconductor device having a bipolar transistor and a field effect transistor formed on a light transmissive substrate.

[0002]

2. Description of the Related Art The formation of a single crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique, and is a bulk S that is used to fabricate an ordinary Si integrated circuit.
Much research has been done because devices using SOI technology have numerous advantages that cannot be reached with i-substrates. That is, by using the SOI technology, 1. 1. Easy dielectric separation and high integration 2. Excellent radiation resistance 3. Stray capacitance is reduced and high speed is possible,
4. 4. The well process can be omitted. Latch-up can be prevented, 6. Advantages such as a fully depleted field effect transistor can be obtained by thinning the film.

In order to realize the many advantages in device characteristics as described above, a method for forming an SOI structure has been researched for several decades. The contents are summarized in the following documents, for example. Special Issue: "
Single-crystal silicon onnon-single-crystal insula
tors "; edited by GWCullen, Journal of CrystalGro
wth, volume 63, no 3, pp 429-590 (1983).

In addition, on old single crystal sapphire substrates,
SOS (silicon-on-sapphire), which is formed by heteroepitaxy Si by CVD (chemical vapor deposition), is known, and although it has succeeded as the most mature SOI technology, the Si layer and underlying sapphire A large amount of crystal defects due to the lattice mismatch at the substrate interface, the mixing of aluminum from the sapphire substrate into the Si layer, and above all, the high cost of the substrate and the delay in increasing the area hinder the spread of its application. There is. In recent years, attempts have been made to realize an SOI structure without using a sapphire substrate. This attempt is broadly divided into the following two: After the surface of the Si single crystal substrate is oxidized, a window is opened to partially expose the Si substrate, and that portion is used as a seed for lateral epitaxial growth to form a Si single crystal layer on SiO ₂ (in this case). With the deposition of a Si layer on SiO _2. ); The Si single crystal substrate itself is used as the active layer, and SiO ₂ is formed thereunder (this method does not involve deposition of the Si layer).

Various semiconductor elements and integrated circuits including them have been produced on a silicon layer on an insulator formed by these methods.

[0006]

As means for realizing the above 1, as a method for directly laterally epitaxially growing a single crystal layer Si by CVD, amorphous Si is deposited,
Solid-phase lateral epitaxial growth by heat treatment, amorphous or polycrystalline Si layer with electron beam, laser
A method of converging and irradiating an energy beam such as light to grow a single crystal layer on SiO ₂ by melting and recrystallization, and a method of scanning a melting region in a band shape by a rod-shaped heater (Zone melting recrystallization) is known.
Each of these methods has merits and demerits, but there are many problems in controllability, productivity, uniformity, and quality.
Still, there is nothing industrially put into practical use. For example,
The CVD method requires sacrificial oxidation to achieve a flat thin film, and the solid phase growth method has poor crystallinity. In the beam anneal method, the processing time by convergent beam scanning and the beam
There is a problem in the controllability such as the degree of overlapping of frames and focus adjustment.
Of these, the Zone Melting Recrystallization method is the most mature, and relatively large-scale integrated circuits have been prototyped, but still many crystal defects such as sub-grain boundaries remain, and minority carrier-device I haven't made it. Moreover, since each method requires a Si substrate, a good quality Si single crystal layer cannot be obtained on a transparent amorphous insulating substrate such as glass.

The above-mentioned method 2 which does not use the Si substrate as seeds for epitaxial growth includes the following methods: An oxide film is formed on a Si single crystal substrate in which V-shaped grooves are anisotropically etched on the surface, a polycrystalline Si layer is deposited on the oxide film as thick as the Si substrate, and then polished from the back surface of the Si substrate. Thereby forming a Si single crystal region surrounded by the V groove and dielectrically separated on the thick polycrystalline Si layer. In this method, although the crystallinity is good, control is performed in the step of depositing polycrystalline Si to a thickness of several hundreds of microns, and in the step of polishing the single crystal Si substrate from the back surface to leave only the separated Si active layer. Problem in terms of productivity and productivity; 2. SIMOX (SIMO
X: Separation by ion implanted oxygen) is a method for forming a SiO ₂ layer by ion implantation of oxygen in a Si single crystal substrate, and is the most mature method at present because it has good compatibility with the Si process. However, S
In order to form an iO ₂ layer, oxygen ions are added to 10 ¹⁸ ion.
Although it is necessary to implant s / cm ² or more, the implantation time is long, the productivity cannot be said to be high, and the wafer cost is high. Furthermore, many crystal defects remain, and the quality is not industrially sufficient to produce minority carrier devices; 3. A method of forming an SOI structure by dielectric isolation by oxidation of porous Si. This method is a P-type S
Proton ion implantation of N-type Si layer on the surface of i single crystal substrate (Imai et al., J. Crystal Growth, vol 63, 547 (1983)),
Alternatively, it is formed into an island shape by epitaxial growth and patterning, and only the P-type Si substrate is made porous by an anodization method in a HF solution so as to surround the Si island from the surface, and then N-type Si island is accelerated by accelerated oxidation. Is a method of dielectric separation. This method has a problem that the separated Si region is determined before the device process, which may limit the degree of freedom in device design.

Further, the thin film Si layer typified by glass, which is deposited on a light transmissive substrate, is generally amorphous and only polycrystal, and a high performance device cannot be manufactured. This is because the crystal structure of the substrate is amorphous, and a simple single crystal layer cannot be obtained by simply depositing it on the Si layer.

By the way, the light transmissive substrate is important in constructing a contact sensor as a light receiving element or a projection type liquid crystal display device. In order to further increase the density, resolution, and definition of these sensors and display devices, high-performance drive elements are required. In addition, the number of terminals of the switching element for switching the pixel, its driving circuit, and the peripheral circuit becomes enormous, and it is extremely difficult to separately fabricate them and mechanically connect them. Therefore, it is preferable that the semiconductor element, the peripheral driving circuit, and the like are manufactured on the same substrate by a common process, and the connection between them is made by patterning a conductive thin film as is done in a normal integrated circuit. It should only be possible for high-density packaging.

Further, due to the inevitable industrial demand for higher performance of the product to be manufactured, it may be manufactured by using a single crystal layer having excellent crystallinity as an element provided on a light transmissive substrate. As required, amorphous Si or polycrystalline Si
Then, it is difficult to manufacture a circuit having sufficient performance required or required in the future because of the crystal structure having many defects.

However, even if any of the above methods using the Si single crystal substrate is used, the purpose of forming a good quality single crystal layer on the light transmissive substrate cannot be achieved.

The present invention includes a bipolar transistor and a field effect transistor as constituent elements in a high quality single crystal semiconductor layer on a light transmissive substrate which can solve the above problems and meet the above requirements. An object is to provide an integrated circuit.

A further object of the present invention is to provide a semiconductor integrated circuit that realizes the advantages of SOI devices.

The present invention also provides a high quality integrated circuit on a light-transmissive substrate, which can replace expensive SOS and SIMOX even when manufacturing a large-scale integrated circuit having an SOI structure. That is also the purpose.

[0015]

According to another aspect of the present invention, there is provided a semiconductor device having a bipolar transistor and a field effect transistor, wherein the bipolar transistor and the field effect transistor have a light transmitting property at least in a visible light region. The single crystal layer that is formed on the surface of the non-porous single crystal layer on the porous silicon substrate or its oxidized surface is at least visible. It is characterized in that it is a single crystal layer obtained by attaching the porous silicon substrate by a process including at least wet chemical etching after the substrate is bonded to the substrate having a light transmitting property in the light region.

In the present invention, it is preferable that the substrate having a light transmitting property in at least a visible light region has an insulating property, and the substrate having a light transmitting property in at least a visible light region is a glass containing SiO ₂ as a main component. Is preferred.

The present invention provides a Si single crystal layer which is excellent in cost efficiency, is uniform and flat over a large area, has extremely excellent crystallinity, and has extremely few defects on an optically transparent insulating SiO ₂ substrate. Since the device is formed including, a bipolar transistor having a reduced capacitance between the substrate and the collector, and an insulated gate field effect transistor having a reduced floating capacitance of the source and drain can be manufactured, and high-speed operation is possible. It is possible to provide a circuit which is free from the latch-up phenomenon and has no radiation error due to a soft error due to α rays.

Here, in order to facilitate understanding of the present invention, a general technical description of porous silicon and its removal by chemical etching will be given.

Porous Si is described in 1956 by Uhlir et al.
It was discovered in the process of research on electropolishing of semiconductors in 2010 (A.
Uhlir, Bell Syst.Tech.J., vol 35, p.333 (1956)). Also, Unami et al. Studied the dissolution reaction of Si in anodization and reported that the anodic reaction of Si in HF solution requires holes, and the reaction is as follows (T .
Unagami: J. Electrochem. Soc., Vol.127, p.476 (198
0)): Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ^- SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + ( ^{4-λ) e + → SiF} 4 + 4H + + λe - where _{SiF 4 + 2HF → H 2 SiF} 6, e + and, e ^- respectively represent a positive hole and an electron. Further, n and λ are the numbers of holes required for dissolving one silicon atom, respectively, and porous silicon is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type silicon having holes is likely to be made porous. The selectivity of this porosity has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Anno, Ohnaka, Kajiwara; IEICE Technical Report, vol 79, SSD 79-9549 (1979). , And K. Imai; S
solid-State Electronics vol 24,159 (1981)). In this way, P-type silicon in which holes are present is likely to be made porous,
The P-type silicon can be selectively made porous.

On the other hand, it is reported that high-concentration N-type silicon also becomes porous (RP Holmstorm, IJYChi Appl.Phys.Let
t. Vol.42, 386 (1983)), there is no particular focus on P and N,
It is important to select a substrate that can realize porosity.

Since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half that of the original silicon. As a result, the surface area is dramatically increased as compared with the volume, so that the chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

Next, the removal of the porous layer Si by chemical etching will be discussed. Generally, P = (2.33-A) /2.33 (1) is called Porosity, and this value can be changed during anodization, and can be expressed as follows: P = (m ₁ −m ₂ ) / (m ₁ −m ₃ ) (2) or P = (m ₁ −m ₂ ) / ρAt (3) where, m ₁ : total weight before anodization m ₂ : after anodization Total weight m ₃ : Total weight after removing porous Si ρ: Density of single crystal Si A: Porous area t: Thickness of porous Si When area of porous area cannot be calculated accurately There are many. In this case, equation (2) is valid, but porous Si must be etched in order to measure m ₃ .

In the epitaxial growth on the above-mentioned porous Si, since the porous Si has a structural property, it is possible to relax the strain generated during the heteroepitaxial growth and suppress the generation of defects. .. However, in this case as well, it is clear that the Porosity of the porous Si is a very important parameter. Therefore, the above-mentioned measurement of Porosity is indispensable also in this case.

In the present invention, selective etching is carried out using an etching solution which has almost no etching action on crystalline Si and an excellent etching action on porous Si.

According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer, and the density thereof is less than half that of single crystal Si. Nevertheless, the single crystallinity is maintained, and it is possible to epitaxially grow the single crystal Si layer on the porous layer. However, 1000 ° C
In the above, rearrangement of the internal holes occurs, and the characteristics of the enhanced etching are impaired. Therefore, for the epitaxial growth of the Si layer, the molecular beam epitaxial growth method, plasma C
CVD method such as VD, low pressure CVD, photo CVD, bias
Low temperature growth such as sputtering method and liquid phase growth method is suitable.

Embodiments of the semiconductor device of the present invention will be described below in detail with reference to the drawings along with a method of manufacturing the same.

[0028]

Embodiment 1 FIG. 1 is a partial cross-sectional view showing one structural example of a semiconductor device according to the present invention. In FIG. 1, reference numeral 2 is a SiO ₂ glass substrate having a light transmitting property. Three island-shaped single crystal layers 6, 8 and 10 are formed on the substrate.

The conductivity type in the island-shaped single crystal layer 6 is formed in an appropriate pattern as shown, and the Si oxide film 12, the insulating layer 14, the base electrode 16 and the emitter are further formed on the island-shaped single crystal layer 6. The electrode 18 and the collector electrode 20 are formed, and N
A PN type bipolar transistor BT is configured.
Although the bipolar transistor is a planar type in FIG. 1, it may be a lateral type or the like.

The conductivity type in the island-shaped single crystal layer 8 is formed in an appropriate pattern to form the source region S and the drain region D, and the gate oxide film 22, the gate 24, and the insulating film are formed on the island-shaped single crystal layer 8. Layer 14, source electrode 26, drain electrode 2
8 and the gate electrode 30 are formed to configure an N-channel field effect transistor NFET.

The conductivity type in the island-shaped single crystal layer 10 is formed in an appropriate pattern to form a source region S and a drain region D. Further, a gate oxide film 32 is formed on the island-shaped single crystal layer 10.
The gate 34, the insulating layer 14, the source electrode 36, the drain electrode 38, and the gate electrode 40 are formed to form a P-channel field effect transistor PFET.

A first embodiment of manufacturing the semiconductor device of the present configuration example will be described with reference to FIGS.

Here, a method is used in which all of the P-type substrate or the high-concentration N-type substrate is made porous and then a single crystal layer is epitaxially grown. 2 (a)-(c)
Are process diagrams for explaining the method for manufacturing a semiconductor substrate of the present invention, each of which is shown as a schematic cross-sectional view in each process.

As shown in FIG. 2A, first, a P-type (or high-concentration N-type) Si single crystal substrate 52 is prepared, all of which are made porous, and subsequently various growth methods are used. Epitaxial growth is performed on the surface of the porous substrate to form a thin film single crystal Si layer 54. The P-type Si substrate is made porous by an anodization method using an HF solution. This porous Si layer has a density of 1.1 to 0.6 g / cm ³ by changing the density of the single crystal Si from 2.33 g / cm ³ to an HF solution concentration of 50 to 20%. It can be changed into a range.

As shown in FIG. 2B, an oxide layer 56 is formed by oxidizing the surface of the single crystal Si layer 54 on the porous Si substrate 52.
And a light-transmissive substrate 58 represented by glass is prepared, and the oxide layer 5 of the single crystal Si layer 54 on the porous Si substrate is prepared.
The surface of 6 and the surface of the light transmissive substrate 58 are bonded together. The oxide layer 56 plays an important role in the characteristics of the device to be manufactured. That is, as for the interface level generated from the underlying interface of the Si active layer, the level of the oxide film interface can be lower than that in the case of directly bonding without the oxide layer 56, and the characteristics of the obtained electronic device are remarkably high. improves. As shown in FIG. 2B, a Si ₃ N ₄ layer 62 is deposited as an etching prevention film to cover the entire two bonded substrates, and the Si ₃ N ₄ layer on the surface of the porous Si substrate 52 is covered. Remove only the layer.
As the etching prevention film, apiezon wax may be used instead of Si ₃ N ₄ . After that, the whole is soaked in an etching solution to perform only the electroless wet chemical etching on the porous Si to form the thin film non-porous single crystal silicon layer 54 on the transparent substrate 58.

FIG. 2C shows a semiconductor substrate obtained by the present invention. That is, the single crystal Si layer 54 having the same crystallinity as that of the silicon wafer is flatly and uniformly thinned on the light transmissive substrate 58 to be formed in a large area of the entire wafer.

The semiconductor substrate thus obtained can be preferably used from the viewpoint of manufacturing an electronic element which is insulated and separated.

A selective etching method for electroless wet chemical etching of only porous Si will be described below.

As an etching solution which does not have an etching effect on crystalline Si and can selectively etch only porous Si, hydrofluoric acid, buffered hydrofluoric acid, hydrofluoric acid containing hydrogen peroxide or buffered fluorine is used. A mixed solution of acid, a mixed solution of hydrofluoric acid or buffered hydrofluoric acid with alcohol, and a mixed solution of hydrofluoric acid with hydrogen peroxide solution and alcohol or buffered hydrofluoric acid is preferably used.

3 to 10 are characteristic diagrams showing the etching time dependence of the thickness of the etched porous Si and single crystal Si when the porous Si and single crystal Si are soaked in the above various etching solutions. .. The etching liquids are
Fig. 3 shows 49% hydrofluoric acid, Fig. 4 shows a mixture of 49% hydrofluoric acid and hydrogen peroxide (1: 5), and Fig. 5 shows a mixture of 49% hydrofluoric acid and alcohol (10: 1). 6 is a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution,
FIG. 7 shows buffered hydrofluoric acid, FIG. 8 shows a mixed solution of buffered hydrofluoric acid and hydrogen peroxide solution (1: 5), and FIG. 9 shows a mixed solution of buffered hydrofluoric acid and alcohol (10: 1). Figure 10
Is a mixed solution of buffered hydrofluoric acid, alcohol, and hydrogen peroxide solution (10: 6: 50). It should be noted that the one to which alcohol was added was infiltrated without stirring, and the one to which alcohol was not added was infiltrated with stirring.

Porous Si is produced by anodizing non-porous single crystal Si, and the conditions are as follows. The starting material of porous Si formed by anodization is single crystal Si.
However, it is possible to use Si having other crystal structure as well: Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 hour: 2.4 (hour) Porous Si thickness: 300 (μm) Porosity: 56 (%) Porous Si prepared under the above conditions was subjected to various etchings at room temperature as described above. It infiltrated the liquid.

When the reduction in the thickness of the porous Si was measured for the one infiltrated in 49% hydrofluoric acid (white circle in FIG. 3) with stirring, the porous Si was rapidly etched,
90 μm in about 40 minutes, 20 after 80 minutes
Even 5 μm had a high degree of surface property and was uniformly etched.

The reduction in the thickness of the porous Si was measured for the one infiltrated in a mixed solution (1: 5) of 49% hydrofluoric acid and hydrogen peroxide solution (white circle in FIG. 4) with stirring. , Porous Si is rapidly etched, 112 μm in about 40 minutes, and 256 μm in 80 minutes.
It had a high degree of surface properties and was uniformly etched.

Mixed solution of 49% hydrofluoric acid and alcohol (1
0: 1) (white circles in FIG. 5) infiltrated without stirring, the reduction in the thickness of the porous Si was measured, and the porous Si was rapidly etched to 85 μm in about 40 minutes. , 195 μm after 80 minutes
Also had a high degree of surface properties and was uniformly etched.

The thickness of the porous Si in the case of being infiltrated in a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (white circles in FIG. 6) without stirring. The porous Si was rapidly etched, and was 107 μm in about 40 minutes, and even 244 μm after 80 minutes had a high degree of surface property and was uniformly etched.

When the decrease in the thickness of the porous Si was measured for the one that had been soaked in buffered hydrofluoric acid (white circle in FIG. 7) while stirring, the reduction in the thickness of the porous Si was measured, and the porous Si was rapidly etched to 70 μm in about 40 minutes. Further, after 120 minutes, 118 μm had a high surface property and was uniformly etched.

The decrease in the thickness of the porous Si was measured for the one that was infiltrated with a mixed solution (1: 5) of buffered hydrofluoric acid and hydrogen peroxide solution (white circles in FIG. 8) while stirring. The quality Si is rapidly etched, and it is 88 μm in about 40 minutes, and 147 μm in 120 minutes.
It had a high degree of surface properties and was uniformly etched.

The decrease in the thickness of the porous Si was measured for the one infiltrated in the mixed solution of buffered hydrofluoric acid and alcohol (10: 1) (white circle in FIG. 9) without stirring. Porous Si is rapidly etched,
67 μm in a minute, and 112 after 120 minutes
The μm also had a high degree of surface property and was uniformly etched.

The thickness of the porous Si of a buffered hydrofluoric acid / alcohol / hydrogen peroxide solution mixture (10: 6: 50) (white circles in FIG. 10) which was infiltrated without stirring. The porous Si was rapidly etched, and it was found that it was 83 μm in about 40 minutes.
After a lapse of 0 minutes, it had a high surface property of 140 μm and was uniformly etched.

The solution concentration of the hydrogen peroxide solution is 30% here, but it is set at a concentration that does not impair the effect of adding the hydrogen peroxide solution described below and is practically acceptable in the manufacturing process and the like. It As buffered hydrofluoric acid, ammonium fluoride (NH ₄ F) 36.2%, hydrogen fluoride (HF) 4.
A 46% aqueous solution is used.

As the alcohol used in the etching solution, in addition to ethyl alcohol, isopropyl alcohol and other alcohols that have practically no adverse effect on the production process and can be expected to have the following alcohol addition effects can be used.

The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid and hydrogen peroxide.
By adding hydrogen peroxide solution, the oxidation of silicon can be accelerated and the reaction rate can be increased as compared with that without addition, and by changing the ratio of hydrogen peroxide solution, the reaction rate can be increased. Can be controlled. Further, by adding alcohol, the bubbles of the reaction product gas due to the etching can be instantly removed from the etching surface without stirring, and the porous Si can be uniformly and efficiently formed.
Can be etched.

The conditions of solution concentration and temperature are set within a range in which the effect of hydrofluoric acid, buffered hydrofluoric acid and the above hydrogen peroxide solution or the above alcohol is exhibited, and the etching rate is practically acceptable in the manufacturing process and the like. Here, as an example, the case of the above-mentioned solution concentration and room temperature was taken up,
The present invention is not limited to such conditions.

When hydrofluoric acid is used, the HF concentration in the etching solution is preferably set in the range of 1 to 95%, more preferably 5 to 90%, and further preferably 5 to 80%.

When buffered hydrofluoric acid is used, the HF concentration in the etching solution is preferably set in the range of 1 to 95%, more preferably 1 to 85%, still more preferably 1 to 70%, and the NH ₄ F concentration is set. Preferably 1 to 95
%, More preferably 5 to 90%, further preferably 5 to
It is set in the range of 80%.

In the etching solution, the H ₂ O ₂ concentration is preferably 1 to 95%, more preferably 5 to 90%, still more preferably 10 to 80%, and set within the range where the above hydrogen peroxide solution effect is exhibited. To be done.

In the etching solution, the alcohol concentration is preferably 80% or less, more preferably 60% or less, still more preferably 40% or less, and set within the range in which the effect of the alcohol is exhibited.

The temperature is preferably set in the range of 0 to 100 ° C, more preferably 5 to 80 ° C, and further preferably 5 to 60 ° C.

On the other hand, non-porous Si having a thickness of 500 μm was infiltrated into the above various etching solutions at room temperature. Later,
The reduction in the thickness of the non-porous Si was measured (FIGS. 3-10).
Black circle). The non-porous Si, even after 120 minutes,
Only less than 100 Å was etched.

Porous Si and non-porous Si after etching
The sample was washed with water, and its surface was microanalyzed by a secondary ion mass spectrometer. No impurities were detected.

The single crystal layer on the surface of the semiconductor substrate obtained in the above step of FIG. 2 is separated into islands by the partial oxidation method or by etching to form the island-shaped single crystal layers 6, 8 and 10 of FIG. To do. The light transmissive substrate 2 of FIG. 1 is composed of the light transmissive substrate 58 and the oxide layer 56 of FIG.

NPN type bipolar transistor B of FIG.
The process of forming T will be described with reference to FIG.

First, as shown in FIG. 11A, N-type impurity ions are implanted into the island-shaped single crystal layer 6 to form a collector region. Next, the oxide film 1 is formed on the surface of the island-shaped single crystal layer 6 by dry oxidation or wet oxidation by pyrogenicity.
2 is formed, and the oxide film is partially removed by using photolithography or the like. A P-type impurity is diffused from the window thus formed by an ion implantation method, a thermal diffusion method or the like to form a base region. Next, the emitter region and the collector contact region are heavily doped with N-type impurities using a mask pattern formed of photoresist.

Subsequently, as shown in FIG. 11B, the insulating layer 14 is deposited by using the CVD method, the bias sputtering method or the like. Further, after forming contact holes by photolithography and etching, electrodes 16 of the base region, the emitter region, and the collector contact region,
A bipolar transistor is obtained by forming 18 and 20 from Al, Al-Si, W, Mo, W silicide, Ti, Ti silicide, or the like.

The PNP bipolar transistor is also
It can be formed in the same manner by changing the conductivity type of impurities.

The N-channel field effect transistor N of FIG.
A process of forming the FET and the P-channel field effect transistor PFET will be described with reference to FIG.

First, as shown in FIG. 12A, P-type impurity ions are implanted into the island-shaped single crystal layer 8 and N-type impurity ions are implanted into the island-shaped single crystal layer 10 independently. Next, gate insulating films 22 and 32 are formed on the respective island-shaped single crystal layers, and gates 24 and 34 of polycrystalline silicon are further patterned and formed. A source region S and a drain region D are formed by self-aligned ion implantation of impurities using the polycrystalline silicon gate as a mask. At this time, N-type impurity ions are implanted into the NFET to form the source region S and the drain region D, and PFETs are implanted into the source region S and the drain region D.

Subsequently, as shown in FIG. 12B, an insulating layer 14 is formed, contact holes are formed, and then source electrodes 26, 36, drain electrodes 28, 38 and gate electrodes 30, 40 are formed. As a result, an N-channel field effect transistor and a P-channel field effect transistor can be obtained.

An integrated circuit is manufactured by using the bipolar transistor and field effect transistor formed as described above, and connecting these electrodes with a thin film metal wiring or the like so as to have a circuit configuration as shown in FIG. can do.

[0070]

[Embodiment 2] A second embodiment of manufacturing the semiconductor device having the configuration example of FIG. 1 will be described with reference to FIG.

Here, a method of forming an N-type layer before making it porous and then selectively making only a P-type substrate or a high-concentration N-type substrate porous by anodization will be described. 14A to 14D are process drawings for explaining the method for manufacturing a semiconductor substrate according to the present invention, each of which is shown as a schematic cross-sectional view in each process.

As shown in FIG. 14A, a low impurity concentration layer 74 is formed on the surface of the high concentration N type Si single crystal substrate 72 by epitaxial growth by various thin film growth methods.
Alternatively, the surface of the P-type Si single crystal substrate 72 is ion-implanted with protons to form the N-type single crystal layer 74.

Next, as shown in FIG. 14B, a P type S
i single crystal substrate (or high-concentration N-type Si single crystal substrate) 72
Is transformed from the back surface into a porous Si substrate 73 by an anodization method using an HF solution. This porous Si layer has a H density higher than that of single crystal Si, which is 2.33 g / cm ^3.
By changing the F solution concentration to 50 to 20%, the density of 1.
It can be changed in the range of 1 to 0.6 g / cm ³ .

As shown in FIG. 14C, a light transmissive substrate 76 is prepared, and a single crystal Si layer 74 on the porous Si substrate is prepared.
And the surface of the light transmissive substrate 76 are bonded together.
After that, the whole is immersed in an etching solution to electrolessly wet-etch the porous Si only, and the thin film non-porous single crystal silicon layer 74 is formed on the light transmissive substrate 76.
Are left to form.

FIG. 14D shows a semiconductor substrate obtained by the present invention. That is, the single crystal Si layer 74 whose crystallinity is equivalent to that of the silicon wafer is flat on the light transmissive substrate 76,
Moreover, the layer is uniformly thinned to be formed over a large area of the entire wafer.

Using the semiconductor substrate thus obtained, the semiconductor device of FIG. 1 can be manufactured in the same manner as in Embodiment 1 above.

[0077]

EXAMPLES The present invention will be described below with reference to specific examples.

Example 1 A P-type (100) single crystal Si substrate having a thickness of 200 μm was anodized in a 50% HF solution. Current density at this time is 100mA
It was / cm ² . At this time, the porosity rate is 8.4μ.
P-type (10 m / min. and 200 μm thick)
0) The entire Si substrate became porous in 24 minutes.

MBE on the P-type (100) porous Si substrate
A Si epitaxial layer was grown at a low temperature of 0.5 micron by a (molecular beam epitaxy) method. The deposition conditions are as follows: temperature: 700 ° C. pressure: 1 x 10 ^-9 Torr growth rate: 0.1 nm / sec.

Next, the surface of this epitaxial layer is exposed to 50
nm thermal oxidation, and the fused silica glass substrate with optical polishing was laid on the surface of the oxide layer,
Both substrates were firmly bonded by heating at ℃ for 0.5 hours.

[0081] The Si ₃ N ₄ layer by low pressure CVD method 0.
Two substrates which were deposited and bonded to each other with a thickness of 1 μm were covered, and only the Si ₃ N ₄ layer on the porous substrate was removed by reactive ion etching.

Thereafter, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
The selective etching was performed at 6:50) without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is about angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm is removed, and after removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 0.5 μm is formed on the quartz glass substrate. did it.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

On the above single crystal silicon layer, an NPN bipolar transistor, an N channel field effect transistor and a P-type transistor are formed by a conventional method as described in the first embodiment.
An integrated circuit was manufactured by manufacturing channel field effect transistors and interconnecting them.

Example 2 A P-type (100) single crystal Si substrate having a thickness of 200 μm was anodized in a 50% HF solution. Current density at this time is 100mA
It was / cm ² . At this time, the porosity rate is 8.4μ.
P-type (10 m / min. and 200 μm thick)
0) The entire Si substrate became porous in 24 minutes.

A Si epitaxial layer was grown at a low temperature of 5 μm on the P-type (100) porous Si substrate by the plasma CVD method. The deposition conditions are as follows: Gas: SiH ₄ High frequency power: 100 W Temperature: 800 ° C Pressure: 1 x 10 ^-2 Torr Growth rate: 2.5 nm / sec.

Next, the surface of this epitaxial layer is exposed to 50
nm thermal oxidization, and the oxide layer surface was subjected to optical polishing 5
Glass substrates having a softening point were stacked around 00 ° C. and heated in an oxygen atmosphere at 450 ° C. for 0.5 hours, so that both substrates were firmly bonded.

A Si ₃ N ₄ layer was deposited to a thickness of 0.1 μm by the plasma CVD method, two bonded substrates were covered, and only the Si ₃ N ₄ layer on the porous substrate was removed by reactive ion etching. ..

Thereafter, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
The selective etching was performed at 6:50) without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is about angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm is removed, and after removing the Si ₃ N ₄ layer, a single-crystal Si layer having a thickness of 5 μm is formed on the low softening point glass substrate. Could be formed.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

On the above single crystal silicon layer, an NPN type bipolar transistor, an N channel field effect transistor and a P-type transistor are formed by a conventional method as described in the first embodiment.
An integrated circuit was manufactured by manufacturing channel field effect transistors and interconnecting them.

Example 3 A P-type (100) single crystal Si substrate having a thickness of 200 μm was anodized in a 50% HF solution. Current density at this time is 100mA
It was / cm ² . At this time, the porosity rate is 8.4μ.
P-type (10 m / min. and 200 μm thick)
0) The entire Si substrate became porous in 24 minutes.

Reduced pressure CV on the P-type (100) porous Si substrate
The Si epitaxial layer was grown at a low temperature of 5 microns by the D method. The deposition conditions are as follows: Gas: SiH ₂ Cl ₂ 0.6 liter / min H ₂ 100 liter / min Temperature: 850 ° C. Pressure: 50 Torr Growth rate: 0.1 μm / min.

Next, the surface of this epitaxial layer is exposed to 50
nm thermal oxidization, and the oxide layer surface was subjected to optical polishing 5
Glass substrates having a softening point were stacked around 00 ° C. and heated in an oxygen atmosphere at 450 ° C. for 0.5 hours, so that both substrates were firmly bonded.

A Si ₃ N ₄ layer was deposited to a thickness of 0.1 μm by the plasma CVD method to cover two bonded substrates, and only the Si ₃ N ₄ layer on the porous substrate was removed by reactive ion etching. ..

After that, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (10:
The selective etching was performed at 6:50) without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 65 minutes.
It is about angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm is removed, and after removing the Si ₃ N ₄ layer, a single-crystal Si layer having a thickness of 5 μm is formed on the low softening point glass substrate. Could be formed.

Further, the same effect can be obtained by coating with apiezon wax or electron wax instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

As a result of cross-sectional observation by a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

On the single crystal silicon layer, an NPN type bipolar transistor, an N-channel field effect transistor and a P-type transistor are formed by a conventional method as described in the first embodiment.
An integrated circuit was manufactured by manufacturing channel field effect transistors and interconnecting them.

Example 4 A P-type (100) single crystal Si substrate having a thickness of 200 μm was anodized in a 50% HF solution. Current density at this time is 100mA
It was / cm ² . At this time, the porosity rate is 8.4μ.
P-type (10 m / min. and 200 μm thick)
0) The entire Si substrate became porous in 24 minutes.

A Si epitaxial layer was grown at a low temperature of 1.0 micron on the P-type (100) porous Si substrate by the bias sputtering method. The deposition conditions are as follows: RF frequency: 100 MHz RF power: 600 W Temperature: 300 ° C Ar gas pressure: 8 x 10 ^-3 Torr Growth time: 120 min Target DC bias: -200 V Substrate DC bias: +5 V.

Next, the surface of this epitaxial layer is exposed to 50
nm thermal oxidization, and the oxide layer surface was subjected to optical polishing 5
Glass substrates having a softening point were stacked around 00 ° C. and heated in an oxygen atmosphere at 450 ° C. for 0.5 hours, so that both substrates were firmly bonded.

A Si ₃ N ₄ layer was deposited to a thickness of 0.1 μm by the plasma CVD method to cover two bonded substrates, and only the Si ₃ N ₄ layer on the porous substrate was removed by reactive ion etching. ..

Then, the bonded substrates were mixed with a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (10:
The selective etching was performed at 6:50) without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is about angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm was removed, and after removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 1.0 μm was formed on the low softening point glass substrate. Could be formed.

Further, the same effect can be obtained when Apiezon wax or electron wax is coated instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

On the single crystal silicon layer, an NPN type bipolar transistor, an N-channel field effect transistor and a P-type transistor are formed by a conventional method as described in the first embodiment.
An integrated circuit was manufactured by manufacturing channel field effect transistors and interconnecting them.

Example 5 A P-type (100) single crystal Si substrate having a thickness of 200 μm was anodized in a 50% HF solution. Current density at this time is 100mA
It was / cm ² . At this time, the porosity rate is 8.4μ.
P-type (10 m / min. and 200 μm thick)
0) The entire Si substrate became porous in 24 minutes.

A Si epitaxial layer was grown at a low temperature of 10 microns on the P-type (100) porous Si substrate by liquid phase epitaxy. The deposition conditions are as follows: solvent: Sn growth temperature: 900 ° C. growth atmosphere: H ₂ growth time: 20 minutes.

Next, the surface of this epitaxial layer is exposed to 50
nm thermal oxidation, and the surface of the oxide layer was optically polished 8
A glass substrate having a softening point was placed around 00 ° C. and heated at 750 ° C. for 0.5 hour in an oxygen atmosphere, whereby the two substrates were firmly bonded.

A Si ₃ N ₄ layer was formed by a low pressure CVD method.
Two substrates which were deposited and bonded to each other with a thickness of 1 μm were covered, and only the Si ₃ N ₄ layer on the porous substrate was removed by reactive ion etching.

Thereafter, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
The selective etching was performed at 6:50) without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is about angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm is removed, and after removing the Si ₃ N ₄ layer, 1 is left on the glass substrate.
A single crystal Si layer having a thickness of 0 μm could be formed.

Further, the same effect can be obtained when Apiezon wax or electron wax is coated instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

As a result of cross-sectional observation by a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

On the single crystal silicon layer, an NPN type bipolar transistor, an N channel field effect transistor and a P-type transistor are formed by a conventional method as described in the first embodiment.
An integrated circuit was manufactured by manufacturing channel field effect transistors and interconnecting them.

Example 6 An Si epitaxial layer was grown to a thickness of 0.5 μm on a P-type (100) Si substrate having a thickness of 200 μm by the CVD method. The deposition conditions are
It is as follows: Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 liter / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 1 min.

This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . The rate of porosity at this time is 8.4 μm / mi.
p-type (100) Si with n.
The entire substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer remained unchanged.

Next, the surface of this epitaxial layer is exposed to 50
nm thermal oxidation, and the fused silica glass substrate with optical polishing was laid on the surface of the oxide layer,
Both substrates were firmly bonded by heating at ℃ for 0.5 hours.

A Si ₃ N ₄ layer was formed by a low pressure CVD method.
Two substrates which were deposited and bonded to each other with a thickness of 1 μm were covered, and only the Si ₃ N ₄ layer on the porous substrate was removed by reactive ion etching.

Then, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (10:
The selective etching was performed at 6:50) without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is about angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns was removed, and after removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 0.5 μm was formed on the quartz glass substrate. I was able to form.

Further, the same effect can be obtained by coating apiezon wax or electron wax instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

As a result of cross-sectional observation by a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

On the single crystal silicon layer, an NPN type bipolar transistor, an N channel field effect transistor and a P-type transistor are formed by a conventional method as described in the first embodiment.
An integrated circuit was manufactured by manufacturing channel field effect transistors and interconnecting them.

Example 7 An N-type Si layer of 1 micron was formed by ion implantation of protons on the surface of a P-type (100) Si substrate having a thickness of 200 microns. The H ⁺ injection amount was 5 ^× 10 ¹⁵ (ions / cm ² ).

This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . The rate of porosity at this time is 8.4 μm / mi.
p-type (100) Si with n.
The entire substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the N-type Si layer remained unchanged.

Next, the surface of the N-type single crystal Si layer is exposed to 50
nm thermal oxidation, and the fused silica glass substrate with optical polishing was laid on the surface of the oxide layer,
Both substrates were firmly bonded by heating at ℃ for 0.5 hours.

A Si ₃ N ₄ layer was formed by the low pressure CVD method.
Two substrates which were deposited and bonded to each other with a thickness of 1 μm were covered, and only the Si ₃ N ₄ layer on the porous substrate was removed by reactive ion etching.

Then, the bonded substrates were mixed with a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (10:
The selective etching was performed at 6:50) without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is about angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of about 200 μm is removed, and after removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 1 μm is formed on the quartz glass substrate. did it.

Further, the same effect can be obtained when Apiezon wax or electron wax is coated instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

On the single crystal silicon layer, an NPN type bipolar transistor, an N-channel field effect transistor and a P-type transistor are formed by a conventional method as described in the first embodiment.
An integrated circuit was manufactured by manufacturing channel field effect transistors and interconnecting them.

Example 8 A P-type (100) single crystal Si substrate having a thickness of 500 μm was anodized in a 50% HF solution. The current density at this time is 10 mA / c
It was m ² . In 10 minutes, a porous layer having a thickness of 20 μm was formed on the surface. On the P-type (100) porous Si substrate, a Si epitaxial layer was grown at a low temperature of 0.5 micron by a low pressure CVD method. The deposition conditions are as follows: Reaction gas flow rate: SiH ₂ Cl ₂ 0.6 liter / min. H ₂ 100 liter / min. Temperature: 850 ° C. Pressure: 50 Torr Growth rate: 0.1 μm / min.

Next, the surface of this epitaxial layer is exposed to 50
nm thermal oxidization, and the fused silica glass substrate with optical polishing was laid on the surface of the oxide layer, and 450 nm
Both substrates were firmly bonded by heating at ℃ for 0.5 hours.

Then, polishing is performed from the back surface of the Si substrate,
After removing 490 μm, a porous layer was exposed.

A Si ₃ N ₄ layer was deposited to a thickness of 0.1 μm by the plasma CVD method to cover two bonded substrates, and only the Si ₃ N ₄ layer on the porous substrate was removed by reactive ion etching. .

Then, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
The selective etching was performed at 6:50) without stirring. 1
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 15 minutes, 50.
It is about angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 0.5 μm could be formed on the quartz glass substrate.

Further, the same effect can be obtained by coating apiezon wax or electron wax instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

On the single crystal silicon layer, an NPN type bipolar transistor, an N channel field effect transistor and a P-type transistor are formed by a conventional method as described in the first embodiment.
An integrated circuit was manufactured by manufacturing channel field effect transistors and interconnecting them.

(Example 9) An Si epitaxial layer was grown to 1 micron by a CVD method on a P-type (100) Si substrate having a thickness of 200 micron. The deposition conditions are as follows: Reactant gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 liter / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 2 min.

This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . The rate of porosification at this time is 8.4 μm /
min, P type (100) with a thickness of 200 microns
The entire Si substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer remained unchanged.

Next, a fused silica glass substrate that had been optically polished was superposed on the surface of this epitaxial layer and heated in an oxygen atmosphere at 800 ° C. for 0.5 hour to firmly bond the two substrates. .

A Si ₃ N ₄ layer was deposited to a thickness of 0.1 μm by the plasma CVD method, the two bonded substrates were covered, and only the Si ₃ N ₄ layer on the porous substrate was removed by reactive ion etching. .

Then, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
The selective etching was performed at 6:50) without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is about angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of about 200 μm is removed, and after removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 1 μm is formed on the quartz glass substrate. did it.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

On the above single crystal silicon layer, an NPN type bipolar transistor, an N channel field effect transistor and a P-type transistor are formed by a conventional method as described in the first embodiment.
An integrated circuit was manufactured by manufacturing channel field effect transistors and interconnecting them.

[0156]

As described above in detail, in the semiconductor device according to the present invention, the element is formed on the high quality single crystal layer formed on the light transmissive substrate by selectively removing the porous substrate. An integrated circuit including a high performance bipolar transistor and a field effect transistor can be obtained. That is, a bipolar transistor having a small capacitance between the substrate and the collector and having no soft error due to α rays,
A low-cost integrated circuit that can exhibit various advantages as an SOI such as high-speed operation can be provided by making it possible to fabricate a field-effect transistor having a small stray capacitance and no latch-up phenomenon, and combining these appropriately. It becomes possible.

Further, in the present invention, since the light transmissive substrate is used, it can be applied to a contact sensor, a projection type liquid crystal display device and the like, and a drive circuit and a peripheral circuit are provided on the substrate of these light receiving part and display part. Since it is possible to form these elements and the electrical connection between these elements and circuits can be made by patterning the conductive thin film, it is possible to increase the pixel density, the definition, and the resolution, and The treatment can be carried out in a short time and the productivity and economy are excellent.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing a configuration example of a semiconductor device according to the present invention.

2A to 2D are process diagrams showing a method for manufacturing a substrate of the semiconductor device of FIG.

FIG. 3 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 4 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 5 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 6 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 7 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 8 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 9 is a diagram showing etching characteristics of porous Si and non-porous Si.

FIG. 10 is a diagram showing etching characteristics of porous Si and non-porous Si.

11A to 11D are process diagrams showing a method for manufacturing a bipolar transistor of the semiconductor device of FIG.

12A to 12C are process diagrams showing a method for manufacturing the field effect transistor of the semiconductor device of FIG.

13 is a diagram showing a circuit configuration of the semiconductor device of FIG.

14A to 14C are process diagrams showing a method for manufacturing a substrate of the semiconductor device of FIG.

[Explanation of symbols]

 2 glass substrate 6,8,10 island-shaped single crystal layer 12 Si oxide film 14 insulating layer 16 base electrode 18 emitter electrode 20 collector electrode 22,32 gate oxide film 24,34 gate 26,36 source electrode 28,38 drain electrode 30 , 40 gate electrode 52 Si substrate 54 single crystal Si layer 56 oxide layer 58 glass substrate 62 etching prevention film 72 Si substrate 73 porous Si substrate 74 single crystal Si layer 76 glass substrate 80 etching prevention film BT bipolar transistor NFET, PFET electric field effect Transistor

Claims (3)

[Claims] 1. A semiconductor device having a bipolar transistor and a field effect transistor, wherein the bipolar transistor and the field effect transistor are formed on a substrate which is transparent to light in at least a visible light region, and the bipolar transistor and the field effect transistor. The single crystal layer constituting the active region of the effect transistor is formed by bonding the surface of the non-porous single crystal layer on the porous silicon substrate or its oxidized surface to a substrate having a light transmittance in at least the visible light region. A semiconductor device, which is a single crystal layer obtained by removing the porous silicon substrate by a process including at least wet chemical etching. 2. The semiconductor device according to claim 1, wherein the substrate having a light transmitting property at least in a visible light region has an insulating property. 3. The semiconductor device according to claim 1, wherein the substrate having light transmissivity in at least a visible light region is glass containing SiO ₂ as a main component.