JPH0541698A - Separation circuit - Google Patents

Abstract

PURPOSE:To shorten inter-device delay time in a reception separation circuit for a multiple signal. CONSTITUTION:The circuit is provided with a reception part 1 corresponding to at least two transmission lines (a) and (b). The reception part 1 performs the interface conversion of the multiple signal received by a receiver circuit 2, and outputs a reception multiple signal a1. A frame synchronizing circuit 3 outputs a reception multiple frame a2 while establishing the frame synchronization. The reception multiple signals a1 and b1 and reception multiple frame phases a2 and b2 to be outputted from the reception part 1 are supplied to a channel part 4. A selection circuit 5 selects a reception multiple signal and a reception multiple frame phase supplied from the designated reception part 1 among the reception parts 1 at its output. A pulse generation circuit 6 prepares a channel pulse designated by the selected reception multiple frame phase. A channel circuit 7 separates the channel of the reception multiple signal selected by the channel pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demultiplexing circuit for a multiplexer, which receives a multiplexed signal through two or more transmission lines.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, a demultiplexing circuit of this type of multiplex converter has at least two transmission lines a and b.
It has a receiving unit 1 corresponding to. Each receiver 1
Is a receiver circuit 2 that outputs a reception multiplexed signal a1.
A frame synchronization circuit 3 for detecting and outputting the reception multiplex frame phase a2 from the reception multiplex signal a1, and a phase alignment of the reception multiplex frame phase a2 with the intra-device multiplex frame phase c from the control circuit 9. And a frame aligner circuit 8 for outputting the intra-device multiplexed signal a3.

The intra-apparatus multiplexed signals a3 and b3 output from each receiver 1 are supplied to the TSI circuit 10. This T
In the SI circuit 10, the control channel 9 that centrally manages and controls the inside of the device separates the corresponding channels and supplies the separated channels to the respective channel units 4.

Next, the operation of the conventional separation circuit will be described with reference to an example of a time chart of the frame aligner circuit 8 shown in FIG.

In this example, it is assumed that the N-channel multiplexed signal is received by the receiving unit 1 through the transmission line a and the receiver circuit 2 outputs the received multiplexed signal a1. The frame synchronization circuit 3 establishes reception multiplexing frame synchronization from the reception multiplexing signal a1 and supplies the reception multiplexing frame phase a2 to the frame aligner circuit 8.

The frame aligner circuit 8 performs frame phase matching with the in-device multiplexed frame phase c output from the control circuit 9 for the received multiplexed signal a1, and outputs the in-device multiplexed signal a3 to the TSI circuit 10. .. Note that the same operation as described above is performed for the reception multiplexed signal received through the transmission path b, and the intra-apparatus multiplexed signal b3
Is output to the TSI circuit 10 from the other receiving unit 1.

In the TSI circuit 10, since the phase of each of the intra-apparatus multiplexed signals a3 and b3 input is phase-locked to the intra-apparatus multiplexed frame phase c, the TSI circuit 10 is controlled by the control circuit 8 which performs centralized control. The designated corresponding channel is separated and supplied to each channel unit 4.

However, in the separation circuit of the conventional example, since the frame aligner circuit 8 performs the phase alignment with the in-device multiplexed frame phase c, the received multiplexed signal a1 is multiplexed at the maximum. Delayed by a period,
There was a problem that the delay time increased.

An object of the present invention is to provide a separation circuit having a relatively small delay time.

[0009]

In order to achieve this object, the separation circuit of the present invention is provided with at least two transmission lines through which multiplexed signals are transmitted and corresponding to the respective transmission lines. A receiving section for receiving the multiplexed signal, and a channel section provided corresponding to each channel, to which the received multiplexed signal and the received multiplexed frame phase output from the respective receiving sections are supplied, This receiver is
Each has a receiver circuit that performs interface conversion of the received multiplexed signal and outputs the received multiplexed signal, and a frame synchronization circuit that establishes frame synchronization of the received multiplexed signal and outputs the received multiplexed frame phase. The channel unit includes a selection circuit for selecting and outputting the reception multiplex signal and the reception multiplex frame phase supplied from the designated reception unit among the reception units, and the selection circuit. It has a pulse generation circuit for creating a channel pulse designated by the selected reception multiplex frame phase, and a channel circuit for separating the channel of the selected reception multiplex signal by the designated channel pulse. ..

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the separation circuit of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the embodiment.

In FIG. 1, receiving units 1 and 1 for receiving one multiplexed signal are provided corresponding to at least two transmission lines a and b through which the multiplexed signal is transmitted.
Each of the receivers 1 and 1 performs interface conversion of the received multiplexed signal and outputs a received multiplexed signal a1 (b1), and a receiver circuit 2 that establishes frame synchronization of the received multiplexed signal a1 for receiving and multiplexing. Frame phase a2 (b
2) for outputting the frame synchronization circuit 3.

The reception multiplexed signal a1 (b1) output from each of the receiving units 1 and 1 and the reception multiplexing frame phase a
2 (b2) is supplied to the channel unit 4. Each of the channel units 4 receives the reception multiplexed signal a1 (b2) supplied from the designated reception unit 1 of the reception units 1.
And a reception multiplexing frame phase a2 (b2) are selected and output, and a pulse generator for generating a channel pulse designated by the reception multiplexing frame phase a2 (b2) selected by the selection circuit 5. It has a circuit 6 and a channel circuit 7 for separating the channel of the selected reception multiplexed signal by this designated channel pulse.

Next, the operation of this configuration will be described.

The reception multiplexed signal supplied through the transmission line a is subjected to interface conversion in the receiver circuit 2 of the receiving unit 1, converted into the reception multiplexed signal a1 and supplied to the frame synchronization circuit 3 and each channel unit 4. To be done. The frame synchronization circuit 3 establishes frame synchronization of the reception multiplex signal a1 and sends the reception multiplex frame phase a2 to each channel unit 4.

The reception multiplexed signal supplied through the transmission line b and another transmission line (not shown) is similarly processed by the receiving unit 1.

Next, in the channel unit 4, among the received multiplex signals a1 etc. and the received multiplex frame phase a2 etc. supplied by the selection circuit 5, for example, the multiplex reception of the receiving unit 1 designated by the mounting slot is performed. The selected signal and the received multiplexed frame phase are selected and output. The pulse generation circuit 6 is set according to the selected reception multiplexed frame phase, and, for example, creates a channel pulse designated by the mounting slot and outputs it to the channel circuit 7.

The channel circuit 7 separates the channel corresponding to the received multiplexed signal selected by the supplied channel pulse.

The other channel sections 4 operate in the same manner to form a separation circuit for all reception multiplexed signals.

Regarding the designation of the corresponding receiving section and the corresponding channel of the channel section 4, including the method of allocating the total channel number for the entire apparatus, the designation of the mounting slot, the optional package designation and the collective management designation are realized. Means are unspecified.

[0021]

As is apparent from the above description, the demultiplexing circuit of the present invention demultiplexes the received multiplexed signal in the channel portion while keeping the respective received multiplexed frame phases. Therefore, there is no need to use the frame aligner circuit as described in the section of the conventional technique, and the delay time of the separation circuit can be comparatively reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a separation circuit of the present invention.

FIG. 2 is a block diagram showing a configuration of a separation circuit according to a conventional technique.

FIG. 3 is a time chart provided for explaining the operation of the conventional separation circuit shown in FIG.

[Explanation of symbols]

 1 receiver 2 receiver circuit 3 frame synchronization circuit 4 channel unit 5 selection circuit 6 pulse generator circuit 7 channel circuit a, b transmission line a1, b1 reception multiplexed signal a2, b2 reception multiplexing frame phase a3, b3 in-device multiplexing signal

Claims (1)

[Claims] 1. At least two transmission lines through which a multiplexed signal is transmitted, corresponding to each transmission line, a receiving section for receiving the multiplexed signal, and corresponding to each channel. , A channel section to which the received multiplexed signal and the received multiplexed frame phase output from each of the receiving sections are supplied, and each of the receiving sections performs interface conversion of the received multiplexed signal to receive. A receiver circuit that outputs a multiplexed signal, and a frame synchronization circuit that establishes frame synchronization of the received multiplexed signal and outputs a received multiplexed frame phase, wherein the channel unit is one of the receiving units. A selection circuit for selecting and outputting the reception multiplex signal and the reception multiplex frame phase supplied from the designated receiving unit,
A pulse generation circuit that creates a channel pulse specified by the reception multiplex frame phase selected by the selection circuit, and a channel circuit that separates the channel of the selected reception multiplex signal by the specified channel pulse. A separation circuit having.