JPH08307404A - Frame synchronism method and device - Google Patents

Abstract

PURPOSE: To secure the frame synchronism through a single frame pattern detection circuit in a system where the serial data are converted into the parallel data and the frame synchronism is secured. CONSTITUTION: The data which are serially inputted undergo the phase shift through a frame phase adjustment circuit 2 and are inputted to a serial/parallel converter 3. A frame pattern is detected by a frame pattern detection circuit 4 after the serial data are converted into the parallel data. Then it is decided whether the frame pattern is coincident with the desired frame synchronism. If the frame pattern is coincident with the frame synchronism, a stop signal is outputted to a counter 1 via a counter control circuit 6. The counter 1 totalizes the number of bits (control value) including the head and subsequent bits of the frame pattern converted into the parallel data and outputs this totalization result to the circuit 2. Then the counter 1 locks its totalization operation when the stop signal is received. Therefore, the circuit 2 stops its phase shift operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for synchronizing frames after converting multiplexed and serially input data into parallel data.

[0002]

2. Description of the Related Art As a frame synchronization technique for multiplexed and serially input data, a method for detecting a frame synchronization signal included in serial data in a serial state and a method for converting the serial data into parallel data Two methods of detecting synchronization are known.

The method of detecting the frame synchronization as it is with serial data can simplify the structure of the frame synchronizer, but when the data transmission rate is high and the number of bytes monitored in the frame period is large, the transmission rate is followed. become unable. On the other hand, the latter method in which serial data is once converted into parallel data and the frame synchronization is detected by the data expanded in parallel has a relatively complicated device configuration, but has a large number of monitoring bytes in the frame cycle. It is mainly used for synchronization detection during high-speed transmission because of its excellent followability.

FIG. 6 shows an outline of a block diagram of a conventional frame synchronizer for detecting frame synchronization from n (natural number) multiplexed serial data using the latter method. Referring to FIG. 6, serial data input from the transmission path is converted into n-bit parallel data (frame) by the serial / parallel conversion circuit 10. In this case, the number of frame patterns converted into parallel is n. This is because n types of frames are created as a result of creating a frame pattern by shifting the phase of n-bit parallel data bit by bit. The n frame patterns are
It is temporarily stored in a register or the like. Then, of the n frame patterns stored, which frame pattern matches the predetermined synchronization pattern is detected by the frame pattern detection circuit 20, and when it is detected that the frame pattern matches the synchronization pattern, The data rearrangement circuit 30 rearranges the input data based on the frame pattern. The protection circuit 40 shown in the figure is a circuit for monitoring whether or not a synchronization shift has occurred for a certain period.

FIG. 7 is a more detailed block diagram of the frame synchronizer. Here, the multiplexing number n of the input data is
3 "shows an example of conversion into 8-bit parallel data. Latch unit 100 to which data is input
Includes a serial-parallel conversion unit 100a that converts serial data into parallel data, a holding unit 100b that holds the converted parallel data, and a frequency divider 100c that divides the clock by 1/8. The parallel synchronization detection / control unit 400 includes eight frame pattern detection units 401 to 40 that detect patterns of eight types of frame pattern signals held in the parallel data holding unit 400a.
8, an identification information detection unit 400b for detecting identification information for identifying frame synchronization included in serial data, and a control unit with a protection circuit 400c. Frequency divider 2
00 further divides the clock divided by ⅛ by the divider 100c into ⅓ to generate frame pattern detection units 401 to 401.
It controls the detection timing of 408 and the identification information detection unit 400b. The serial-parallel converter 100a converts input data into parallel data. The holding unit 100b divides the parallel data by 8 bits for each 1/8 divided clock from the divider 100c.

Here, the frame pattern detectors 401 to 401
408 are connected in parallel with each other in a state of being shifted by 1 bit, for example, the first frame pattern detection unit 401 detects the 1st bit to the 8th bit, and the second frame pattern detection unit 402 outputs 2 bits. The eighth to ninth bits are detected in the same manner by detecting the 9th to 9th bits.
Detects the 8th to 15th bits. As a result, since the length of the frame pattern is 8 bits, frame synchronization is detected by any of the frame pattern detection units 401 to 408, and the coincidence pulse from the detected frame pattern detection unit is detected by the protection circuit-equipped control unit 400c and It is output to the identification information detection unit 400b. The identification information section 400b is
The identification information is detected at the timing of 1/3 frequency division.

The controller 400c with protection circuit detects from which frame pattern detector the coincidence output is output, and outputs a shift signal to the frequency divider 100c. In this way, the frequency division timing of the frequency divider 100c is adjusted. Further, when the coincidence pulse is output from the frame pattern detection units 401 to 408 and the identification ID is detected from the identification information unit 400b, the frames are synchronized. When this state reaches the number of protection stages set in the protection circuit 40, the control signal, that is, the head information of the frame synchronization in the desired channel is output to the frequency divider 200. As a result, the select start position of the demultiplexer shown in FIG. 8 is determined, so that the received data is distributed to desired channels and separated. From the frequency divider 200, the controller 400c with the protection circuit is provided.
When receiving the control signal from, the signal to that effect is output to the demultiplexer 300.

With the above-mentioned structure, 8
Since different types of frame patterns are generated, the frame synchronization is detected by any one of the frame pattern detection units by determining the coincidence between the eight types of frame patterns and the synchronization pattern. be able to.

FIG. 9 is a data structure diagram of each channel before multiplexing in, for example, PCM communication, and FIG. 10 is a data structure diagram after multiplexing by a multiplexer. As shown in these figures, byte-unit frame synchronization signals F1 and F2 and their identification signal ID are added to the data of each channel. In addition, FIG. 11 shows a time chart of the above-described processing.

[0010]

As described above, conventionally, when detecting frame synchronization, serially input data (8-bit configuration) is expanded into 8 types of frame patterns, and then 15 lines are further added. Expand to parallel data,
The developed frame pattern was detected by the eight frame pattern detection units 401 to 408. For this reason,
The circuit scale of the frame pattern detection units 401 to 408 becomes large, and there is a problem in downsizing the frame synchronizer and reducing manufacturing cost. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and to provide a method for performing frame synchronization with a simple configuration after converting serial data into parallel data, and a frame synchronization device suitable for implementing this method.

[0011]

According to the frame synchronization method of the present invention, input data that is serially transmitted at a predetermined frame period and is phase-shifted for each unit data length is expanded into parallel frame patterns and expanded. The frame pattern is compared with a required synchronization pattern, and when the two patterns do not match, the phase of the input data is shifted until they match, and when they match, the phase of the input data is fixed.

Further, the frame synchronizer of the present invention comprises a phase adjusting circuit for shifting the phase of input data serially transmitted in a predetermined frame cycle for each unit data length, and an input phase-shifted by this phase adjusting circuit. A serial-parallel conversion circuit that sequentially converts data into parallel data, a frame pattern detection circuit that detects the frame pattern of each converted parallel data and determines the matching with a required synchronization pattern, and the frame pattern detection circuit. When it is determined that the frame pattern and the synchronization pattern match, the amount of phase shift by the phase adjustment circuit is fixed, while
And a phase control unit that controls the phase shift amount until they match.

In this structure, the phase control means is
For example, a counter that self-runs at a clock timing longer than the frame cycle of the input data and accumulates a control value representing the time when the frame pattern and the synchronization pattern match each other in the frame cycle, and the frame pattern detection circuit A counter control circuit that allows the continuous cumulative total of the control values by the counter when determining a mismatch and stops the cumulative total of the counter when the pattern matching is determined, and fixes the control value at that time,
And the phase shift amount of the phase adjustment circuit is controlled based on the control value. Furthermore, after the cumulative stop of the control value by the counter, the synchronization state of the detected frame pattern is monitored for a predetermined period, and if a synchronization deviation occurs during the monitoring, an initial value for releasing the fixed control value by the counter It is also effective to provide a protection circuit that generates the activation signal.

[0014]

The input data that is serially transmitted has its phase adjusted by the phase adjustment circuit for each unit data length, and then enters the serial-parallel conversion circuit, where serial data is converted to parallel data, after which frame pattern detection is performed. Enter the circuit. The frame pattern detection circuit detects whether or not the plurality of frame patterns developed in parallel coincide with expected desired frame synchronization. On the other hand, the counter starts the accumulation of the number of bits (control value) at the timing of the unit data length from the pattern head bit in the frame pattern converted into parallel data by the serial-parallel conversion circuit, and the accumulated value is calculated by the phase adjustment circuit. Derive to. Each bit is preferably reset every frame period. The phase adjustment circuit changes the amount of phase shift based on this cumulative value to establish frame synchronization.

When frame synchronization is achieved, that is, when the frame pattern matches the synchronization pattern, the frame pattern detection circuit sends a signal indicating that fact to the counter control circuit. As a result, the counter stops the accumulation of the number of bits and locks the accumulated value derived to the phase adjustment circuit. When the cumulative value from the counter is locked, the phase adjustment circuit maintains the phase state by fixing the current phase shift amount. As a result, the first data of the parallel expanded data is always the first bit of the frame. After the frame synchronization is established, the protection circuit monitors whether synchronization is established for a predetermined number of protection stages, and if synchronization is lost during the monitoring, it sends an initialization signal to the counter control circuit. The counter control circuit initializes the counter (free-run state) based on this initialization signal.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram of a frame synchronization apparatus according to an embodiment of the present invention. This frame synchronizer includes a frame phase adjustment circuit 2 for adjusting the phase of a frame, a serial / parallel conversion circuit 3 for converting serial data into parallel data, a frame pattern detection circuit 4 for detecting a frame pattern, for example, a frame cycle divided by two. The counter 1 is self-propelled, a counter control unit 6 that controls the operation of the counter 1, and a protection circuit 5 that monitors the number of stages of synchronization protection and generates an initialization signal if necessary. The counter control unit 6 stops the counter 1 when, for example, frame synchronization is achieved, and makes the counter 1 self-run again when synchronization is lost.

Note that the period of the counter 1 is set to be the frame period divided by two in consideration of at least the period of the counter 1 in consideration of the synchronization pattern determination time, the control signal transmission time, and the phase fixing described later. Is required to be longer than the frame period.

FIG. 2 shows the frame phase adjustment from the counter 1.
Time control of the three control signals A, B, C derived to the circuit 2
In the illustrated example, the cycle of the counter 1 is
The frequency is divided by two. Requires three control signals A, B, C
Eight types (2³ ) Frame pattern position
This is to control the phase. Counter 1 has these 8 types
The CTR values corresponding to the frame pattern are accumulated. This
The CTR value of is a control value that represents the time when frame synchronization is achieved.
Yes, for example, the CTR value “2” indicates that eight types of frame
The third of the turns means synchronized. Synchronous
The CTR value at the time when it is taken depends on the three control signals A, B and C.
From the counter 1 to the frame phase adjustment circuit 2
It The frame phase adjustment circuit 2 has "0" to "7" bits
The phase can be shifted up to (unit data length),
Based on the control signals A, B, C sent from the unter 1.
Adjust the amount of phase shift. This frame phase adjustment circuit 2
FIG. 3 shows a specific configuration example of the above.

Referring to FIG. 3, the input serial data is input to the phase adjusting circuit 30 from the output terminals of the eight-stage cascade flip-flop circuit (FF). Further, the three control signals A, B, C from the counter 1 are input to the phase adjustment circuit 30. The phase adjustment circuit 30 performs phase adjustment by combining the outputs of the FFs based on the control signals A, B, and C. The output of the frame phase adjustment circuit 2 is sent to the serial / parallel conversion circuit 3 where it is converted into parallel data.

An output format example of the serial-parallel conversion circuit 3 is shown in FIGS. The first conversion example shown in FIG. 4A shows a state in which the synchronization is achieved, and the individual data a to h (1 frame) serially input are respectively bit "1" to. It is expanded in parallel to bit "8". In this case, the data a is bit "1"
Has been developed as, and below, data b is a bit "
2 ", data c is bit" 3 ", data h is bit"
8 ". This frame pattern coincides with the expected synchronization pattern and is in synchronization. The second conversion example shown in FIG.
The data a is expanded in 8 ", the data b is expanded in the bit" 1 ", and the data h is expanded in the bit" 7 ", respectively, which are not synchronized. For example, from the second conversion example, the counter 1
If the frame pattern counting starts, the cumulative value (CTR value) becomes "7" until the pattern can be synchronized. The counter 1 uses the CTR value as the frame phase adjustment circuit 2
Output to. The frame phase adjustment circuit 2 adjusts the phase shift amount of the input data based on this value.

In the third conversion example shown in FIG. 5 (a), the head data a of the frame pattern is developed as bit "7", data b is similarly bit "8", and hereinafter, data h is bit "." 6 "shows the case of being expanded. Further, in the fourth conversion example shown in FIG. 5B, the head data a of the frame pattern is expanded as bit “2”, similarly data b is bit “3”, and hereinafter, data h is bit “1”. It is shown as being expanded as. Figure 5
Since frame synchronization is not achieved in either case, the phase shift amount is adjusted in the same procedure as in the case of FIG.

By adjusting the amount of phase shift in this way, the head bit of the frame pattern after being converted into parallel data becomes the same as the frame head bit of the data serially input in a predetermined frame period, Easily synchronized. In the present embodiment, the example in which the 3-multiplexed signal is converted into 8-bit parallel data has been described, but the number of multiplexed signals and the number of bits of parallel data may be arbitrary.

[0023]

As is apparent from the above description, according to the present invention, at the time of frame synchronization, the head of a frame pattern to be serially input does not have to be monitored for all bits as in the conventional case. There is an effect that the data becomes the top data of the frame pattern after parallel conversion. Further, since the frame synchronization can be achieved by only one frame pattern detection circuit, the configuration (circuit scale) of the frame synchronization device can be simplified, and further, the circuit scale is reduced, thereby reducing the manufacturing cost. You can also plan.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a frame synchronization device according to an embodiment of the present invention.

FIG. 2 is a timing chart of a control signal for adjusting a phase shift amount according to the present embodiment.

FIG. 3 is a configuration diagram of a frame phase adjustment circuit according to the present embodiment.

FIG. 4 is a conversion output format diagram in which serial data is converted into parallel data.

FIG. 5 is a conversion output format diagram in which serial data is converted into parallel data.

FIG. 6 is a conceptual diagram of a conventional frame synchronization method.

FIG. 7 is a block diagram showing a configuration example of a conventional frame synchronization device.

FIG. 8 is a multiplexing / demultiplexing configuration diagram of a multiplexed signal on the transmitting side and a multiplexed signal on the receiving side.

FIG. 9 is a data structure diagram of each channel before multiplexing on the transmission side.

FIG. 10 is a data structure diagram after multiplexing on the transmitting side.

FIG. 11 is a time chart of an example of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 counter 2 frame phase adjustment circuit 3 serial / parallel conversion circuit 4 frame pattern detection circuit 5 protection circuit 6 counter control unit 10 serial / parallel conversion circuit 20 frame pattern detection circuit 30 data rearrangement circuit 40 protection circuit

Claims (4)

[Claims] 1. The input data serially transmitted at a predetermined frame cycle and phase-shifted for each unit data length is expanded into a parallel frame pattern, and the expanded frame pattern is compared with a required synchronization pattern. When the two patterns do not match, the phase of the input data is shifted until they match, and when they match, the phase of the input data is fixed. 2. A phase adjustment circuit that shifts the phase of input data that is serially transmitted in a predetermined frame cycle for each unit data length, and input data that is phase-shifted by this phase adjustment circuit is sequentially converted into parallel data. A serial / parallel conversion circuit, a frame pattern detection circuit that detects the frame pattern of each converted parallel data and determines the matching with a required synchronization pattern, and the frame pattern detection circuit that matches the frame pattern and the synchronization pattern. A frame synchronization device, comprising: a phase control unit that fixes the phase shift amount by the phase adjustment circuit when the determination is made, and controls the phase shift amount until they match when the non-coincidence is determined. 3. The counter, wherein the phase control means is self-running at a clock timing longer than a frame cycle of the input data and accumulates a control value indicating a time point when the frame pattern and the synchronization pattern match each other for each frame cycle. When the frame pattern detection circuit determines a pattern mismatch, the counter allows the cumulative total of the control values to be continued, and when the pattern match is determined, the cumulative value of the counter is stopped and the control value at that time is fixed. 3. The frame synchronization device according to claim 2, further comprising a counter control circuit for controlling the phase shift amount of the phase adjustment circuit based on the control value. 4. The phase control means further monitors the synchronization state of the detected frame pattern for a predetermined period after the control value is cumulatively stopped by the counter, and when the synchronization shift occurs during the monitoring, the phase control means uses the counter. 4. The frame synchronization device according to claim 3, further comprising a protection circuit that generates an initialization signal for releasing the fixed control value.