JPH0542019B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory management method when data processing is performed using a microprocessor.

[Summary of the invention]

The present invention uses a microprocessor that processes data and stores the processed data in memory, and divides the data memory into fixed management units in order to manage the data memory at high speed. Additionally, when the microprocessor writes or reads the data to or from the data memory, an interrupt type memory management circuit monitors the address of the microprocessor and detects the final address of the management unit in the data memory. , prohibits future data memory write operations and issues an interrupt to the microprocessor. The microprocessor receives this interrupt, detects that the management unit has ended, and uses the interrupt to determine whether the instruction that received the interrupt was a write or read, and how many times it accessed from the last address. Determined by the flag held in the memory management circuit, a new management unit is prepared for one access and data processing continues, and a new management unit is prepared for multiple accesses. At the same time, if data is read into a new management unit more than the previous management unit, data will be read from the new management unit for the number of times that exceeded, and if data is written, write protection will be applied. The process is now continued by writing data to new management units for the number of times exceeded.

[Conventional technology]

Traditionally, memory management was done using software.
The determination of the management unit was performed, or the address conversion of the microprocessor was performed using a dedicated memory management element or a memory management element built into the microprocessor.

[Problem to be solved by the invention]

The problem with conventional methods is that the purpose of using a dedicated memory management element is to use a microprocessor as a high-performance computer, and since it includes all the functions necessary for a computer, data The cost was extremely high for applications where only the management of data was desired. Furthermore, although the method of managing data memory using software is inexpensive, the data processing speed is slow.

[Means to solve the problem]

To solve the conventional problems, the present invention uses interrupts that are standard in microprocessors to process data at high speed without using expensive memory management elements. The configuration was designed to manage the memory for use.

[Effect]

When the microprocessor writes or reads from memory, the memory management circuit monitors the address, and when the final address of the management unit is detected, the memory management circuit generates an interrupt to the microprocessor. . The microprocessor that received the interrupt detects the end of the management unit, prepares a new management unit, and determines the contents of the instruction that received the interrupt based on the flag held by the memory management circuit. , performs processing according to the content and continues data processing.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

An outline of the present invention will be explained using FIG.

When the microprocessor 1 accesses the memory 3, the address bus 11, the bus control signal 13, and the data bus 12 operate when reading, and the interrupt type memory management circuit 2 recognizes this and accesses the predetermined memory 3. If it is the final address of the management unit, interrupt type memory management circuit 2
generates a chip select 17, read 15 or write 16 signal to the memory 3 and performs normal access. When the microprocessor 1 accesses the final address of the management unit in the memory 3, the interrupt type memory management circuit 2
An interrupt 14 is generated for the microprocessor 1 at the same time as normal access is made to the microprocessor 1.
The microprocessor 1 recognizes the interrupt during the accessing instruction;
Detects the end of the management unit, prepares a new management unit, determines the content of the instruction based on the read/write distinction flag and the access count distinction flag of the interrupt type memory management circuit 2, and processes according to the content. After that, data processing continues again.

Next, an embodiment of the present invention will be specifically described based on FIGS. 2 and 3. FIG. 2 shows an overall block diagram, and FIG. 3 is a circuit diagram showing the interrupt type memory management circuit 2 in detail.

In this embodiment, the microprocessor 1 assumes that the width of the data bus 12 is 16 bits, accesses the data memory 3 in units of 1 word (16 bits), and the instruction to access the data memory 3 is , a case will be described in which 1 word access is performed in one access or 2 word access is performed in two accesses, and 2 kilobytes are used as the memory management unit. When the microprocessor 1 writes to or reads from the data memory 3, the bus control signal 13 and address bus 11 of the microprocessor 1 are input to the address decoder 4, and the address decoder 4 outputs the data memory selection signal. (RAMSELECT) 23 occurs. The interrupt type memory management circuit 2 receives the selection signal 23,
This is part of the bus control signal 13 of the microprocessor 1. Bus read/write control signal (R/
W) Along with 18, for data memory 3,
17, 15, 1 which are memory control signals
6 is supplied from the memory R/W control block 2D in FIG. At the same time, the interrupt type memory management circuit 2 determines whether the access is to the final address of the memory management unit, as shown in FIG.
By the NAND gate 2A, all the lower address lines of A1 to A10 of the address bus 11 are set to 1.
If it is the final address, then
At the start of a bus cycle, 0 is latched in F/F 2B, and the output of said F/F becomes an interrupt () 14 to the microprocessor 1. F/F at the same time
2C holds information as to whether the access by the microprocessor 1 is for reading or writing. At the end of the bus cycle, F/F2E becomes 0, the memory control signal ( ) 16 is disabled, and the operation of rewriting the data memory 3 is performed until the interrupt clear signal ( ) 20 is given from the microprocessor 1. It is forbidden. F/F
2F and 2G are given an interrupt clear signal ( ) 20 in advance, and both are held at 1. When the access to the final address ends with one word, F/F2F has 0, F/F2G
is held as 1, and when the final address is accessed using two words from the final address,
0 is held in F/F2F and 0 is held in F/F2G. When the microprocessor 1 receives an interrupt, it sets the output R/W flag 19 of the F/F2B,
Read the output flag A24 of F/F2F and the output flag B25 of F/F2G through the I/O port 5 via the address decoder 4 using the status read signal ( ) 21 to determine the contents of the instruction cycle that received the interrupt. do. The contents of F/F2B, 2F, 2G are
In the case of 101, it indicates that the reading process has ended at the final address of the memory management unit, a new management unit for reading is prepared, an interrupt clear signal ( ) 20 is issued, and data processing is continued again. If the contents of F/F2B, 2F, and 2G are 100, it indicates that one word was read beyond the final address of the memory management unit during the read process.
Prepare a new management unit for reading, issue an interrupt clear signal ( ) 20, read the first word of the new management unit into the internal register of microprocessor 1 that has been set in advance for reading, and start data processing again. continue.
In the case of 001, the process indicated by 101 is processed as a write, and in the case of 000, the process indicated by 001 is processed as a write.

Although this embodiment has been explained using the case where the data bus width is 16 bits, it can be realized using almost the same circuit for other microprocessors, and F/ F2
This can be easily realized by increasing the number of F, F/F2G.

〔Effect of the invention〕

As described above, the present invention allows data memory management to be configured with a very small number of parts, so it can be created at a lower cost than when using a dedicated memory management element, and memory management can be performed by software without using the present invention. If this is done, an instruction to compare memory addresses is entered for each piece of data in order to determine the boundaries of the management unit, resulting in a very slow process. By using the present invention, there is no comparison instruction and high-speed processing can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the outline of the present invention;
FIG. 2 is a block diagram representing an embodiment of the present invention;
FIG. 3 is a circuit diagram representing an embodiment of the present invention. 1...Microprocessor, 2...Interrupt type memory management circuit, 3...Data memory, 4...
Address decoder, 5...I/O port.

Claims (1)

[Claims] 1 In a method for managing memory by dividing data memory into fixed units, when a microprocessor writes or reads data to or from the memory, the address of the microprocessor is monitored, and the A flag that detects the final address of a management unit, generates an interrupt to the microprocessor, and at the same time prohibits writing to the memory after accessing the final address, and distinguishes whether access to the final address is a read. A memory management method for managing memory for data by holding a flag indicating how many times the instruction that caused the interrupt has accessed from the final address.