JPH0543399U - ROM interface tester - Google Patents

Abstract

(57) [Abstract] [Purpose] If the specification is such that the FLASH ROM and ROM are mounted in the socket of the DUT, the RO
Enables testing of the FLASH ROM interface function with the M installed. [Structure] The tester 11 includes a frequency divider 21, a driver 22,
It has a blue LED 13 and a red LED 12. In the test connection, the blue LED 13 is turned on by applying the write enable signal WE and + 5V, and the red LED 12 is turned on at + 12V.
Lights up.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a ROM interface tester for testing a ROM interface portion of an OA (office automation) device such as a personal computer.

[0002]

[Prior Art]

 In conventional OA equipment, if both ROM and FLASH ROM (batch erasable and rewritable ROM) can be used, even if the specifications are such that the ROM is installed, FLASH ROM, which is the interface between the system and FLASH ROM, can be used. It was necessary to confirm the normality of the ROM interface, and the ROM was replaced with the FLASH ROM to carry out the test when the FLASH ROM was installed.

[0003]

[Problems to be solved by the device]

 Conventionally, even if the system under test has a ROM-installed specification, it has been necessary to mount the FLASH ROM on the device under test for testing. For this reason, there are drawbacks such as the number of steps required to replace the ROM with the FLASH ROM, and the mistake of forgetting to replace the FLASH ROM with the ROM.

Therefore, an object of the present invention is to provide a ROM interface tester capable of performing an interface test when a system under test is equipped with a ROM and a FLASH ROM is installed.

[0005]

[Means for Solving the Problems]

 According to another aspect of the invention, the first pin of the socket is provided with a first pin that is connected to the interface of the first storage means and a second pin that is connected to the interface of the second storage means. A plug inserted when the first storage means is not mounted and a write signal and a power source for the first storage means taken out through this plug are input, and a frequency division signal obtained by dividing the write signal is output. The ROM interface tester is provided with a frequency dividing means, a first visual display means for displaying the frequency-divided signal, and a second visual display means for displaying the application of power.

According to a second aspect of the present invention, there is provided a first socket of the socket having a first pin connected to the interface of the first storage means and a second pin connected to the interface of the second storage means. A plug to be inserted when the first storage means is not mounted on the pin and a write signal and power source for the first storage means taken out through this plug are input, and a signal obtained by dividing the write signal is output. The ROM interface tester is provided with a frequency dividing means and an audible signal generating means for generating an audible signal from the signal and the power supply.

According to another aspect of the invention, when the first storage means is installed, the first pin connected to the interface of the storage means and the second storage means are installed. To the first storage means from the plug inserted when the first storage means is not mounted on the first pin of the socket having the second pin connected to the first storage means and the interface taken out through this plug. The ROM interface tester is provided with a conversion means for inputting a write signal and a power source, converting the data into data, and outputting the data to the printing means.

[0008]

[Action]

 According to the present invention, when the ROM is mounted on the socket, the test plug is inserted into the FLASH ROM mounting position of the socket, and the extracted write signal and the divided signal generated by the power source are visually or audibly. The interface of FLASH ROM can be confirmed by displaying or converting the write signal into data for printing and recording it in the printer.

[0009]

【Example】

 Hereinafter, the present invention will be described in detail with reference to embodiments.

FIG. 2 shows a ROM interface tester of the embodiment. The ROM interface tester 11 tests the interface function between the FLASH ROM mounted on the printed circuit board of the system and the circuit board. The tester 11 is provided with a red light emitting diode (LED) 12 and a blue LED 13 for confirming the connection of the power supply and the write signal in the FLASH ROM interface, and the probe 14 to be inserted into the socket of the FLASH ROM instead of the FLASH ROM. The cord 15 attached with is connected.

FIG. 3 is a plan view showing the printed circuit board 16 and the socket 17. FIG. 4 shows a state in which the FLASH ROM 18 is mounted on the socket 17. Further, FIG. 5 shows a case where the ROM 19 is mounted in the socket 17. Since the pins of the FLASH ROM interface portion 21 of the socket 17 are vacant, the probe 14 of the ROM interface tester 11 of FIG. 2 can be inserted here to test the FLASH ROM.

FIG. 6 shows the pin arrangement of the FLASH ROM 18. Signals of corresponding symbols are applied to the pins F _{1 to} F ₅ and F _{28 to} F ₃₂ of the FLASH ROM 18.

On the other hand, FIG. 7 shows the pin arrangement of the ROM 19. Signals of corresponding symbols are applied to the ROM 19 pins R _{1 to} R ₃ and R _{26 to} R ₂₈ .

FIG. 8 shows the pin arrangement of the probe 14 of the ROM interface tester 11. Signals of corresponding symbols are applied to the probes 14 pins T _{1 to} T ₄ .

FIG. 9 shows an arrangement when the ROM 19 is mounted on the socket 17. Signals of corresponding symbols are applied to the pins S _{1 to} S ₅ and S _{28 to} S _{32 of the} socket 17 and the pins R _{1 to} R ₃ and R _{26 to} R ₂₈ of the mounted ROM 19. When the ROM 19 shown in FIG. 7 is inserted into the socket 17 shown in FIG. 9, the pin S _{3 of} the socket 17 and the pin R _{1 of the} ROM 19 are designed to be inserted together. Since the pins S ₁ , S ₂ and S ₃₁ , S ₃₂ of the socket 17 of FIG. 9 correspond to the FLASH ROM interface portion 21 of FIG. 5 and the pins of the ROM 19 are not inserted, the probe 14 shown in FIG. By inserting the pins T _{1 to} T ₄ of, the write signal WE and the power supplies + 12V and + 5V can be taken out to the ROM interface tester 11 side and detected.

FIG. 10 shows a test connection. The plug 14 connected to the tester 11 by the cord 15 is inserted into the socket 17 on which the ROM 19 is mounted on the printed board 16.

FIG. 1 shows a circuit of the ROM interface tester. Tester 11 inputs pins T ₁ of the write enable signal WE of the probe 14 of Figure 8 than the code 15, pin T ₃ of + 12V, the pin T ₄ a + 5V. The tester 11 is connected to the plug 14 shown in FIG. When the plug 14 is inserted into the socket in which the ROM of FIG. 7 is mounted, + 12V, the write enable signal WE and + 5V are input from the pins T ₁ , T ₃ and T ₄ .

The output of the frequency divider 21 that inputs the signal WE to the clock input terminal (CLK) is connected to the input terminal (IN) of the driver 22, and the output terminal (OUT) is +5 V from the blue LED 13 via the resistor 23. Connected to. The blue LED 12 provided at one end is connected to a power source 12V through a resistor 24.

The frequency divider 21 frequency-divides the input write enable signal WE signal for the FLASH ROM into a signal of a low frequency that can be visually confirmed by a person and outputs the signal to the driver 22. The blue LED 13 is turned on by the output of the driver 22. The red LED 12 is turned on when + 12V is applied from the resistor 24.

Next, the operation of the ROM interface tester of this embodiment will be described.

FIG. 11 shows the configuration of the system under test. In this figure, the CPU 31, the RAM 32, the ROM 33, the keyboard 34, and the pin S ₃₁ of the socket 17 of the ROM shown in FIG. 9 are connected to each other via a bus 35. In the case of the test, the pin T ₃ of the probe 14 of the ROM interface tester 11 is connected to the socket 17.

FIG. 12 is a flow chart showing the operation during the test of the system under test. This tester tests whether or not the ROM interface is connected to the pin 31 of the socket 17 of FIG. Therefore, the test method is different from the test of the storage area of the ROM, and it is checked whether or not the write enable signal is output to the pin 31. In the test, first, the number N of times of writing to an arbitrary address of the FRASH ROM is set. Therefore, the CPU 31 stores the number of times N in the RAM 32 (FIG. 12; S101). Next, it waits for a light instruction to be input from the keyboard 34 (S102).

When the write instruction is input (Y), the CPU 31 reads the program stored in the ROM 33 and executes the write command, and outputs the write enable signal (WE) via the bus 35 to the socket 17 of the ROM. It is output to the pin S ₃₁ (step S103). Next, the CPU 32 subtracts 1 from the number N stored in the RAM 32 (step S104), and the CPU 31 checks whether or not the number N is zero. If not, the process returns to step S103 (step S105; N). The CPU 31 outputs the write enable signal WE N times by such repetition, and ends the operation when N = 0 (step S105; Y). On the ROM interface tester 11 side of FIG. 1, it was confirmed that the light enable signal (WE) was output by turning on the blue LED 13 and the power supply +12 V, +5 V was output by turning on the red LED 12, and the FLASH ROM interface of the system under test was checked. Is determined to be normal.

The present invention can be modified as follows. That is, if a buzzer is used instead of the blue LED 13, it is possible to construct a tester for audibly confirming the FLASH ROM interface.

As another modified example, the test of the system under test is performed by converting the presence or absence of the write enable signal WE and the power supplies + 12V and + 5V into a code in the tester and outputting the code to the printer together with the test number. The number and the quality of the FLASH ROM interface can be recorded.

[0026]

[Effect of the device]

 As described above, according to the present invention, the interface function of the FLASH ROM can be confirmed with the ROM mounted in the test system. Therefore, even in the ROM specification model, it is necessary to replace the ROM with the FLASH ROM for testing. Disappears. Therefore, there is no need for man-hours for replacement, and there is an effect of preventing replacement mistakes.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a FLASH ROM of the present invention.

FIG. 2 is a plan view showing an embodiment of a ROM interface tester in the present embodiment.

FIG. 3 is a plan view showing a printed circuit board and a socket according to this embodiment.

FIG. 4 shows a flash ROM for the socket in this embodiment.
It is a top view showing the case where M is mounted.

FIG. 5 is a plan view showing a case where a ROM is mounted on the socket according to the present embodiment.

FIG. 6 is a plan view showing the pin arrangement of the FLASH ROM in this embodiment.

FIG. 7 is a plan view showing the pin arrangement of the ROM in this embodiment.

FIG. 8 is a plan view showing the pin arrangement of the probe in the present embodiment.

FIG. 9 is a plan view showing the pin arrangement of the socket in this embodiment.

FIG. 10 is a test connection diagram showing the connection between the tester and the system under test in the present embodiment.

FIG. 11 is a block diagram showing an outline of a configuration at the time of a test of the system under test in the present embodiment.

FIG. 12 is a flow chart showing an operation during a test of the system under test in the present embodiment.

[Explanation of symbols]

 11 Tester 12, 13 LED 14 Plug 15 Code 17 Socket 18 FLASH ROM 19 ROM 21 Frequency Divider 22 Driver 31 CPU 32 RAM 33 Keyboard

Claims (3)

[Scope of utility model registration request] 1. A first storage means on the first pin of a socket comprising a first pin for connecting with an interface of the first storage means and a second pin for connecting with an interface of the second storage means. A plug inserted when the plug is not mounted, a frequency dividing means for inputting a write signal and a power source for the first storage means taken out through the plug, and outputting a frequency-divided signal of the write signal, A ROM interface tester comprising: first visual display means for displaying a signal; and second visual display means for displaying the application of the power source. 2. A first storage means on the first pin of a socket comprising a first pin for connecting to the interface of the first storage means and a second pin for connecting to the interface of the second storage means. A plug inserted when the plug is not mounted, a frequency dividing means for inputting a write signal and a power source for the first storage means taken out through the plug, and outputting a frequency-divided signal of the write signal, An audible signal generating means for generating an audible signal from a signal and a power source. 3. A first storage means on the first pin of a socket comprising a first pin for connecting with the interface of the first storage means and a second pin for connecting with the interface of the second storage means. And a conversion means for inputting a write signal and power supply to the first storage means taken out through the plug and converting the data into data and outputting the data to the printing means. A ROM interface tester characterized by the following.