JPH0543414Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a motor speed detection circuit that detects the zero-crossing point of a signal obtained from a frequency generator that detects the rotational speed of a motor.

Background Art and Its Problems A frequency generator (hereinafter referred to as FG) is used in the servo circuit of a small motor used in a tape recorder, VTR, etc. to detect the rotational speed of the motor. As such a FG, a speed-responsive variable reluctance type is widely used. The output waveform of this type of FG is a sine waveform, and the servo circuit converts this sine waveform into a rectangular wave by detecting its zero-crossing point to obtain speed information.

Conventionally, a circuit shown in FIG. 1 has been used as a circuit for converting a sin waveform into a rectangular wave.

In the figure, the output of FG1 is amplified by a preamplifier 2 to become a sine wave signal shown in FIG. 2A, and this signal is then amplified by a limiter amplifier 3 to become a signal shown in FIG. 2C. This signal is comparator 4
By detecting the zero crossing point at , a rectangular wave signal as shown in FIG. 2D is obtained at the output terminal 5. The rising and falling edges of this rectangular wave signal correspond to the zero-crossing points of the original sine waveform, and therefore, these rising edges and falling edges indicate the speed information of the motor. In an actual servo circuit, the frequency of the rectangular wave signal shown in FIG. 2D is doubled and converted into the rectangular wave signal shown in FIG. 2E, thereby facilitating signal processing in subsequent circuits.

In the comparator 4, the actual detection level is not zero, but is V ₁ and V ₂ as shown in FIG. 2C, and the levels are different on the positive side and the negative side. Therefore, if the limiter amplifier 3 is omitted and the output of the pre-amplifier 2 is directly applied to the comparator 4, the obtained rectangular wave becomes the rectangular wave shown in FIG. 2B. The rise and fall of this rectangular wave are shifted from the true zero-crossing point of the original sin waveform.
Such a deviation results in erroneous speed information, causing the servo circuit to malfunction. If the detection levels V ₁ and V ₂ of the comparator 4 are at the same level, the degree of deviation from the true zero crossing point of the rise and fall of the rectangular wave will be the same, so correct speed information can be obtained, but V ₁ , V ₂ is actually difficult to make the same.

For this purpose, a limiter amplifier 3 is provided to absorb changes in V ₁ and V ₂ by forming the sine waveform into a waveform in which the vicinity of the zero level is expanded as shown in FIG. 2C.

In the conventional circuit shown in FIG. 1 described above, if noise enters the input of comparator 4 when the motor is stopped and the output of FG1 is in a no-signal state, this noise will be detected and an error will occur. The speed information is output. As a countermeasure against noise, it is sufficient to provide the comparator 4 with a hysteresis characteristic so that it does not respond to noise, but it is not possible to provide the comparator 4 with a hysteresis characteristic because the detection accuracy will deteriorate.

Purpose of the invention The present invention provides a motor speed detection circuit that prevents malfunctions due to noise when there is no signal.

Summary of the invention The invention consists of a frequency generator FG that generates a sine wave signal with a frequency corresponding to the rotation of the motor, and a limiter circuit that can obtain a substantially rectangular wave signal (Fig. 2 C) from this sine wave signal. 3, a first comparator 4 capable of obtaining a first rectangular wave signal (FIG. 4A) from the output signal of this limiter circuit by detecting the zero crossing point of the output signal of this limiter circuit; A phase shift circuit 10 that can change the phase of the output signal of the frequency generator and a second rectangular wave signal ( a second comparator 11 capable of obtaining FIG. 4B) without responding to noise;
One of the output signals of the first comparator and the second comparator is supplied to the set or reset terminal, and an inverted signal of the other output signal is supplied to the reset or set terminal. a flip-flop 6, and a second flip-flop 6 to which the inverted signal of the one output signal is supplied to the set or reset terminal, and the other output signal is supplied to the reset or set terminal.
a flip-flop 7, which outputs the output signal of the first flip-flop (FIG. 4C) and the second flip-flop.
A signal obtained by frequency-multiplying the output signal of the first comparator (Fig. 4E) is obtained by performing a logical product with the output signal of the flip-flop (Fig. 4D).
This relates to a motor speed detection circuit configured to obtain the following.

Embodiment FIG. 3 shows an embodiment of the present invention in which a square wave signal whose frequency is doubled as shown in FIG. is attached.

The sine wave signal (FIG. 2A) obtained from the FG 1 is processed by the limiter amplifier 3 and the comparator 4 in the same manner as in FIG. 1, and the rectangular wave signal shown in FIG. 4A is obtained at the point. This rectangular wave signal is the same as the one shown in Figure 2D, and has highly accurate speed information in steady state, but noise occurs when the motor is stopped and the output of FG1 is in a no-signal state. If the fourth
An error output E shown in Figure A occurs. This rectangular wave signal sets flip-flop 6 and also sets flip-flop 7 via inverter 8. On the other hand, the sine wave signal is phase-shifted by, for example, 90 degrees in the phase shift circuit 10 and then applied to the comparator 11. This comparator 11 is of an inverting type with hysteresis characteristics, and is configured not to respond if there is noise at the input as shown as the above-mentioned error output E. Therefore, from this comparator 11, a rectangular wave signal as shown in FIG. 4B is obtained. This rectangular wave signal has a phase delay of 90° with respect to the rectangular wave signal at the point, and the above error output E
This is an inversion of the high level and low level of the rectangular wave signal with no response during the period. The square wave signal at this point resets flip-flop 7 and also resets flip-flop 6 via inverter 9.

The flip-flops 6 and 7 are set and reset, respectively, at the falling edge of the input applied to the set terminal S and the reset terminal R, respectively, and
When set, a low level is output from the output terminals _Q1 and _Q2 , and when reset, a high level is output from each output terminal.

Therefore, the flip-flop 6 is set to a low level at the falling edge of the rectangular wave signal at the point shown in FIG. It is reset to high level at the rising edge of the square wave signal. Therefore, as the output _Q1 of flip-flop 6,
The signal shown in FIG. 4C is obtained. Furthermore, the flip-flop 7 is set to a low level at the falling edge of the output of the inverter 8 (in other words, the rising edge of the rectangular wave signal at the point shown in FIG. 4A), and becomes a low level at the point shown in FIG. 4B. It is reset to high level at the falling edge of the square wave signal. Therefore, the signal shown in FIG. 4D is obtained as the output _Q2 of the flip-flop 7. During the period in which the Q ₁ and Q ₂ outputs respond to the error output E, the flip-flops 6 and 7 are reset, so that they maintain a constant level (low level in the case of the illustrated embodiment). There is. By applying these Q ₁ and Q ₂ outputs to the NAND gate 12, an output signal P ₀ shown in FIG. 4E is obtained at the output terminal 13. This signal P ₀ is obtained by doubling the frequency of the rectangular wave signal at the point, and is at a constant level (high level in the illustrated embodiment) during the error output E period. Therefore, speed information can be obtained from the rising edge of this signal _P0 .

In addition, the comparator 11 with hysteresis characteristics
forms the falling edge of the signal _P0 , and since this falling edge does not serve as speed information, this comparator 11 does not require a particularly high precision one. Further, this comparator 11 may have an offset instead of a hysteresis characteristic. The phase shift circuit 10 does not necessarily need to shift the phase of the input sine wave by 90 degrees, but may be any circuit that shifts the phase of the sine wave to such an extent that the falling edge is formed. Further, the circuit from the point to the output terminal 13 is substantially equivalent to an exclusive OR circuit, and various logic circuit configurations other than those shown in FIG. 3 are possible. Others 3rd
Based on the concept shown in the figure, it can also be applied to rotation that quadruples a rectangular wave signal at a point.

Effects of the invention In the present invention, the first rectangular wave signal obtained from the first comparator is a sine wave signal with a frequency corresponding to the rotation of the motor, which is converted into an approximately rectangular wave signal by a limiter circuit. Since it is made into a rectangular wave by detecting the zero-crossing point of the signal, it accurately corresponds to the rotational speed of the motor. Further, the second rectangular wave signal obtained from the second comparator does not contain noise and has a phase different from that of the first rectangular wave signal. Then, the first and second rectangular wave signals and their inverted signals are supplied to the first and second flip-flops, and the output signals of the first and second flip-flops are ANDed. A signal obtained by frequency-multiplying the output signal of comparator 1 is obtained.

Therefore, the frequency multiplied signal is
Like the second square wave signal, it accurately corresponds to the rotational speed of the motor, and like the second square wave signal, it does not contain noise, so it is highly accurate and reliable. Moreover, it is possible to provide a motor speed detection circuit that is convenient for signal processing in a subsequent circuit.

Also, two flip-flops are connected to the first and second flip-flops.
Since the frequency multiplied signal is obtained by skillfully combining the rectangular wave signal and their inverted signals, the circuit configuration is also simple.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional level detection circuit, Fig. 2 is an output waveform diagram of the main part of Fig. 1,
Figure 3 is a block diagram showing an embodiment of the present invention;
The figure is an output waveform diagram of the main part of FIG. 3. In addition, in the symbols used in the drawings, 1...FG
(frequency generator), 3... limiter amplifier (limiter circuit), 4... comparator (first comparator), 6... flip-flop (first flip-flop), 7... flip-flop (second flip-flop), 10... ...Phase shift circuit, 11...
...Comparator (second comparator), 12...
...It is a NAND gate (AND circuit).

Claims (1)

[Claims for Utility Model Registration] A frequency generator that generates a sine wave signal with a frequency corresponding to the rotation of a motor, a limiter circuit that can obtain a substantially rectangular wave signal from this sine wave signal, and a limiter circuit that can obtain a substantially rectangular wave signal from this sine wave signal. A first rectangular wave signal can be obtained from the output signal of this limiter circuit by detecting the zero crossing point of the output signal.
a comparator, a phase shift circuit that can change the phase of the output signal of the frequency generator, and a second one from the output signal of the phase shift circuit by detecting the zero crossing point of the output signal of this phase shift circuit. a second comparator capable of obtaining a square wave signal without responding to noise; and an output signal of one of the output signals of the first comparator and the second comparator is supplied to a set or reset terminal. and a first flip-flop to which an inverted signal of the other output signal is supplied to the reset or set terminal; or a second flip-flop supplied to the set terminal, and the output signal of the first comparator is determined by ANDing the output signal of the first flip-flop and the output signal of the second flip-flop. A motor speed detection circuit configured to obtain a frequency-multiplied signal.