JPH0543429Y2 - - Google Patents
Info
- Publication number
- JPH0543429Y2 JPH0543429Y2 JP1988034146U JP3414688U JPH0543429Y2 JP H0543429 Y2 JPH0543429 Y2 JP H0543429Y2 JP 1988034146 U JP1988034146 U JP 1988034146U JP 3414688 U JP3414688 U JP 3414688U JP H0543429 Y2 JPH0543429 Y2 JP H0543429Y2
- Authority
- JP
- Japan
- Prior art keywords
- processing circuit
- chip
- detection element
- radiation
- signal processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【考案の詳細な説明】
〈産業上の利用分野〉
本考案は、例えばＸ線撮影装置等、二次元放射
線画像を得るための装置に利用することのでき
る、放射線検出器に関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a radiation detector that can be used in a device for obtaining two-dimensional radiation images, such as an X-ray imaging device.
〈従来の技術〉
一般に、上述の放射線検出器においては、複数
個の放射線検出素子、およびその各検出素子から
の信号を処理するための信号処理回路を、例えば
基板等にどのように実装するかが一つの課題とな
つている。<Prior Art> In general, in the above-mentioned radiation detector, it is difficult to mount a plurality of radiation detection elements and a signal processing circuit for processing signals from each detection element on, for example, a substrate. has become an issue.
従来、その実装は、例えば第４図に示すよう
に、複数個の放射線検出素子、およびその検出素
子の個数に応じた信号処理回路を、それぞれ一枚
のチツプ内に設けて検出素子チツプD4および処
理回路チツプC4を形成し、この検出素子チツプ
D4および処理回路チツプC4を、基板４１の一面
上に搭載するとともに、基板４１の表面上に形成
された配線パターンによつて検出素子チツプD4
の各検出素子と処理回路チツプC4の信号処理回
路とを接続する方法が採られている。そして、こ
のように構成された放射線検出器B4を、第５図
に示すように、順次積層することによつて、大面
積を有する二次元放射線検出器アレイを形成して
いた。 Conventionally, as shown in FIG. 4, for example, a plurality of radiation detection elements and signal processing circuits corresponding to the number of the detection elements are provided in one chip, and a detection element chip D 4 is implemented. and processing circuit chip C4 , and this detection element chip
D 4 and the processing circuit chip C 4 are mounted on one surface of the substrate 41, and the detection element chip D 4 is mounted on one surface of the substrate 41 by a wiring pattern formed on the surface of the substrate 41.
A method is adopted in which each of the detection elements and the signal processing circuit of the processing circuit chip C4 are connected. Then, as shown in FIG. 5, the radiation detectors B4 configured in this manner are sequentially stacked to form a two-dimensional radiation detector array having a large area.
〈考案が解決しようとする課題〉
ところで、上述の実装方法によれば、一枚の検
出素子チツプD4に形成する放射線検出素子の個
数が多くなるにつれ、基板４１の配線パターンの
密集度が高くなり、各放射線検出素子および各信
号処理回路を、それぞれ該当する配線パターンに
接続することが困難になるばかりでなく、処理回
路チツプC4内の信号処理回路の集積度も高くな
り、処理回路チツプC4の製造も困難になるとと
もに、処理回路チツプC4内の各信号処理回路の
信頼性も低下する等の理由から、一枚の検出素子
チツプD4にあまり多くの放射線検出素子を設け
ることができないという問題があつた。<Problem to be solved by the invention> By the way, according to the above-mentioned mounting method, as the number of radiation detection elements formed on one detection element chip D 4 increases, the density of the wiring pattern on the board 41 increases. This not only makes it difficult to connect each radiation detection element and each signal processing circuit to their respective wiring patterns, but also increases the degree of integration of the signal processing circuit within the processing circuit chip C4 . It is not recommended to provide too many radiation detection elements on one detection element chip D 4 because it becomes difficult to manufacture C 4 and also reduces the reliability of each signal processing circuit in the processing circuit chip C 4 . There was a problem that I couldn't do it.
本考案の目的は、基板上の配線パターンの密集
度および処理回路チツプ内の信号処理回路の集積
度を高くすることなく、検出素子チツプに配列す
る放射線検出素子の個数の増加を図ることのでき
る、放射線検出器を提供することにある。 The purpose of the present invention is to increase the number of radiation detection elements arranged on a detection element chip without increasing the density of the wiring pattern on the board or the degree of integration of the signal processing circuit within the processing circuit chip. , to provide a radiation detector.
〈課題を解決するための手段〉
上記の目的を達成するための構成を、実施例に
対応する第１図を参照しつつ説明すると、本考案
は、基板１上に、放射線検出素子が複数個配列さ
れた一枚の検出素子チツプD1を配設するととも
に、複数個の信号処理回路が形成された少なくと
も二枚の処理回路チツプC11およびC12を配設す
る。そして、検出素子チツプD1の各放射線検出
素子からの複数の配線を、所定本数ごとに各処理
回路チツプC11，C12に振り分けて、それぞれの処
理回路チツプC11，C12の信号処理回路に接続す
る。<Means for Solving the Problems> The configuration for achieving the above object will be explained with reference to FIG. 1 corresponding to the embodiment. One arrayed detection element chip D1 is provided, and at least two processing circuit chips C11 and C12 on which a plurality of signal processing circuits are formed are provided. Then, a plurality of wirings from each radiation detection element of the detection element chip D 1 are distributed to each processing circuit chip C 11 and C 12 by a predetermined number, and the signal processing circuit of each processing circuit chip C 11 and C 12 is Connect to.
〈作用〉
一枚の検出素子チツプD1に対して二枚の処理
回路チツプC11およびC12を設けることにより、各
処理回路チツプC11，C12内の信号処理回路の集積
度を、一枚の処理回路チツプを設けた場合に対し
て低くすることが可能になるとともに、検出素子
チツプD1の各放射線検出素子からの複数の配線
を二方向に分散することができ、その配線の密集
度を緩和することも可能になる。<Operation> By providing two processing circuit chips C 11 and C 12 for one detection element chip D 1 , the degree of integration of the signal processing circuits in each processing circuit chip C 11 and C 12 can be unified. It is possible to reduce the cost compared to the case where two processing circuit chips are provided, and the multiple wirings from each radiation detection element of the detection element chip D1 can be distributed in two directions, reducing the density of the wiring. It is also possible to reduce the intensity.
〈実施例〉
本考案の実施例を、以下、図面に基づいて説明
する。<Example> An example of the present invention will be described below based on the drawings.
第１図は本考案実施例の側面図である。 FIG. 1 is a side view of an embodiment of the present invention.
基板１上に、複数個の放射線検出素子（図示せ
ず）が配列された検出素子チツプD1が配設され
ており、検出素子チツプD1の側方両側近傍の基
板１上には、それぞれ処理回路チツプC11および
C12が配設されている。 A detection element chip D 1 in which a plurality of radiation detection elements (not shown) are arranged is arranged on the substrate 1. On the substrate 1 near both sides of the detection element chip D 1 , radiation detection elements are arranged. Processing circuit chip C 11 and
C 12 is installed.
各処理回路チツプC11，C12内には、それぞれ検
出素子チツプD1の放射線検出素子の半数に相当
する個数の信号処理回路（図示せず）が一列に互
いに隣接して形成されている。 In each of the processing circuit chips C 11 and C 12 , a number of signal processing circuits (not shown) corresponding to half of the radiation detection elements of the detection element chip D 1 are formed adjacent to each other in a row.
検出素子チツプD1の複数個の放射線検出素子
のうち半数は、処理回路チツプC11内の該当する
信号処理回路に、また、他の半数の処理回路チツ
プC12内の該当する信号処理回路に、それぞれ基
板１表面上に形成された配線パターンおよび接続
ワイヤ（共に図示せず）等によつて電気的に接続
されており、検出素子チツプD1の各放射線検出
素子からの信号は、図中二点鎖で示すように、処
理回路チツプC11またはC12内の信号処理回路を経
て出力される。 Half of the plurality of radiation detection elements of the detection element chip D 1 are connected to the corresponding signal processing circuits in the processing circuit chip C 11 , and the other half to the corresponding signal processing circuits in the processing circuit chip C 12 . , are electrically connected by wiring patterns and connection wires (both not shown) formed on the surface of the substrate 1, and the signals from each radiation detection element of the detection element chip D1 are as shown in the figure. As shown by the double-dot chain, the signal is output through the signal processing circuit in the processing circuit chip C11 or C12 .
以上のように構成された放射線検出器B1複数
個を順次積層して、第２図に示すような大面積を
有する二次元放射線検出器アレイを形成すること
ができる。なお、各検出素子チツプD1は、それ
ぞれ回路処理チツプC11および基板１によつて覆
われているが、Ｘ線等の放射線は処理回路チツプ
C11および基板１上を通過して検出素子チツプD1
に入射する。 A two-dimensional radiation detector array having a large area as shown in FIG. 2 can be formed by sequentially stacking a plurality of radiation detectors B configured as described above. Note that each detection element chip D 1 is covered by a circuit processing chip C 11 and a substrate 1, but radiation such as X-rays is covered by the processing circuit chip.
C 11 and the detection element chip D 1 passing over the substrate 1
incident on .
ここで、本実施例においては、一つの検出素子
チツプD1に対して二枚の処理回路チツプC11およ
びC12を設けたので、例えば従来と同じ面積を有
する検出素子チツプD1に、従来と同じ個数の放
射線検出素子を形成した場合には、各処理回路チ
ツプC11，C12それぞれの信号処理回路の集積度
を、従来のように、一枚の検出素子チツプに一枚
の処理回路チツプを設けた場合に対し、半分にす
ることが可能になり、各処理回路チツプC11，C12
内の信号処理回路の信頼性の向上を図ることがで
きるとともに、基板１上の配線パターンのピツチ
も従来に比して広くすることができる。また、検
出素子チツプD1の放射線検出素子の個数を例え
ば従来の２倍にした場合でも、各処理回路チツプ
C11，C12の信号処理回路の集積度および配線パタ
ーンの密集度を従来と同じ程度に止留めることが
できる。 Here, in this embodiment, two processing circuit chips C11 and C12 are provided for one detection element chip D1 , so for example, the detection element chip D1 having the same area as the conventional one is When the same number of radiation detecting elements are formed, the degree of integration of the signal processing circuits of each processing circuit chip C 11 and C 12 is changed to one processing circuit for one detection element chip, as in the conventional case. Compared to the case where chips are provided, it is possible to halve the number of chips, and each processing circuit chip C 11 , C 12
The reliability of the internal signal processing circuit can be improved, and the pitch of the wiring pattern on the substrate 1 can also be made wider than in the past. Furthermore, even if the number of radiation detection elements in the detection element chip D1 is doubled, for example, compared to the conventional one, the number of radiation detection elements in each processing circuit chip
The degree of integration of the signal processing circuits of C 11 and C 12 and the density of wiring patterns can be kept at the same level as in the past.
なお、本実施例では、二枚の処理回路チツプ
C11およびC12を基板１の同じ面側に配設している
が、本考案はこれに限られることなく、例えば第
３図に示すように、二枚の処理回路チツプC11お
よびC12のうちの一方の処理回路チツプC12を、基
板３１の反対側の面に配設してもよく、この場
合、第２図に示すような放射線検出器アレイを形
成した際に、Ｘ線等の放射線が処理回路チツプ
C11を通過することなく検出素子チツプD1に入射
するので、処理回路チツプC11が放射線による悪
影響を受ける虞れがなくなる。 Note that in this embodiment, two processing circuit chips are used.
Although C 11 and C 12 are arranged on the same side of the substrate 1, the present invention is not limited thereto. For example, as shown in FIG . One of the processing circuit chips C 12 may be disposed on the opposite surface of the substrate 31. In this case, when forming a radiation detector array as shown in FIG. radiation processing circuit chip
Since the radiation enters the detection element chip D1 without passing through C11 , there is no possibility that the processing circuit chip C11 will be adversely affected by the radiation.
また、以上の本実施例では、一枚の検出素子チ
ツプD1に対して二枚の処理回路チツプC11および
C12を設けた場合について説明したが、一枚の検
出素子チツプD1に対して三枚以上の処理回路チ
ツプを設けてもよい。 In addition, in this embodiment described above, two processing circuit chips C 11 and 1 are used for one detection element chip D 1 .
Although the case where C12 is provided has been described, three or more processing circuit chips may be provided for one detection element chip D1 .
〈考案の効果〉
以上説明したように、本考案によれば、放射線
検出素子が複数個配列された一枚の検出素子チツ
プに対して、その放射線検出素子からの信号を処
理するための信号処理回路が形成された少なくと
も二枚の処理回路チツプを設けたから、各処理回
路チツプ内での信号処理回路の集積度、および検
出素子チツプの各放射線検出素子からの配線の密
集度を、従来に比して低くすることが可能にな
り、各処理回路チツプの製造、および検出素子チ
ツプと処理回路チツプとのコンタクトが従来より
も容易になるとともに、各処理回路チツプ内の信
号処理回路の信頼性も高くなる。<Effects of the Invention> As explained above, according to the present invention, signal processing for processing signals from the radiation detection elements is performed on one detection element chip in which a plurality of radiation detection elements are arranged. Since at least two processing circuit chips with circuits formed thereon are provided, the degree of integration of the signal processing circuit within each processing circuit chip and the density of wiring from each radiation detection element of the detection element chip can be reduced compared to the conventional one. This makes it easier to manufacture each processing circuit chip and to make contact between the detection element chip and the processing circuit chip, and also improves the reliability of the signal processing circuit within each processing circuit chip. It gets expensive.
また、検出素子チツプの放射線検出素子の個数
を多くした場合でも、処理回路チツプの個数を多
くすることにより、処理回路チツプ内での信号処
理回路の集積度が高くなることを抑えることがで
きる。従つて、一枚の検出素子チツプにおける単
位面積当りの画素数の増加を図ることができ、解
像力が従来に比して高い二次元放射線検出器アレ
イを形成することが可能になる。 Further, even when the number of radiation detection elements in the detection element chip is increased, by increasing the number of processing circuit chips, it is possible to suppress an increase in the degree of integration of the signal processing circuit within the processing circuit chip. Therefore, it is possible to increase the number of pixels per unit area in one detection element chip, and it is possible to form a two-dimensional radiation detector array with higher resolution than conventional radiation detectors.
第１図は本考案実施例の側面図、第２図はその
実施例を複数個積層して形成した二次元放射線検
出器アレイの側面図、第３図は本考案の他の実施
例の側面図、第４図は放射線検出器の従来例の側
面図、第５図は二次元放射線検出器アレイの従来
例の側面図である。
１……基板、C11，C12……処理回路チツプ、
D1……検出素子チツプ。
Fig. 1 is a side view of an embodiment of the present invention, Fig. 2 is a side view of a two-dimensional radiation detector array formed by stacking a plurality of the embodiments, and Fig. 3 is a side view of another embodiment of the present invention. 4 is a side view of a conventional example of a radiation detector, and FIG. 5 is a side view of a conventional example of a two-dimensional radiation detector array. 1...Substrate, C11 , C12 ...Processing circuit chip,
D 1 ...Detection element chip.
Claims (1)
一枚の検出素子チツプを配設するとともに、信号
処理回路が複数個形成された少なくとも二枚の処
理回路チツプを配設し、上記各放射線検出素子か
らの複数の配線を、所定本数ごとに上記各処理回
路チツプに振り分けて、それぞれの処理回路チツ
プの信号処理回路に接続してなる、放射線検出
器。 A single detection element chip in which a plurality of radiation detection elements are arranged is disposed on a substrate, and at least two processing circuit chips in which a plurality of signal processing circuits are formed are disposed, and each of the radiation detection elements described above is A radiation detector in which a plurality of wires from the element are distributed to each of the processing circuit chips in a predetermined number and connected to the signal processing circuit of each processing circuit chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988034146U JPH0543429Y2 (en) | 1988-03-14 | 1988-03-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988034146U JPH0543429Y2 (en) | 1988-03-14 | 1988-03-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01137486U JPH01137486U (en) | 1989-09-20 |
| JPH0543429Y2 true JPH0543429Y2 (en) | 1993-11-01 |
Family
ID=31260865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988034146U Expired - Lifetime JPH0543429Y2 (en) | 1988-03-14 | 1988-03-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0543429Y2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61196570A (en) * | 1985-02-25 | 1986-08-30 | Hitachi Zosen Corp | Amorphous silicon X-ray sensor |
| JPS6229162A (en) * | 1985-07-29 | 1987-02-07 | Toshiba Corp | Image sensor |
-
1988
- 1988-03-14 JP JP1988034146U patent/JPH0543429Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01137486U (en) | 1989-09-20 |
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