JPH0544115B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a sector mark detection circuit for an optical disk, and particularly to a circuit that detects sector marks recorded on an optical disk with high reliability.

[Background of the invention]

In an optical disk device, as shown in FIG. 7, a groove 13 is formed in advance in a spiral shape on a disk disc 15, and a row of pits (a row of small pits) 14 is formed along the groove 13 to record information. do. As shown in FIG. 8, signal reproduction from an optical disk is performed by irradiating a laser beam 16 onto the disk surface on which information is recorded in the form of pit rows and detecting the reflected light. The relationship between the pit 14 and the laser beam 16 is such that the beam 16 irradiated onto the pit 14 is diffracted by passing through a narrow pit, so that the reflected light tends to diverge. As shown in the cross-sectional view and plan view of Fig. 8a and b, the pit 1
Laser spot 16 for diameter (0.5μm) of 4
The diameter becomes larger due to the spread, and the reflected light beams from adjacent pits have overlapping parts as shown in FIG. 8c. The reflected light from the bottom of the pit 14 has an optical path difference of 1/2 wavelength with respect to the reflected light from the flat area around the pit, and the phases are opposite to each other, so that they cancel each other out and the amount of detected light decreases.

Furthermore, as shown in Fig. 9, the information track on an optical disk is divided into multiple areas (called sectors), and each area has a track number, sector number, and other information for recording/playback. It consists of a part in which necessary information is recorded (usually called an ID) and a data part in which additional user data is recorded.
For example, an example of a method for recording data in sectors of an optical disk is described in Japanese Patent Laid-Open No. 181163/1983.

At the beginning of the ID section, a signal called a sector mark indicating the starting point of a sector is recorded using a method different from the data modulation method. As shown in Fig. 10, the sector mark exists between the gap part (area where nothing is recorded) and the ID part, and its recording pattern is a modulation method different from that of normal data, as shown in Fig. 10. It has a shape as shown in 22, that is, it is composed of a combination of several oval pits. More specifically, the length of these elliptical pits is determined, and there are two types: relatively long ones at the beginning and end, and relatively short ones arranged in the middle. . The gap area before the sector mark is an area for absorbing rotational fluctuations between devices, and is also an area for securing processing time for the host device. Since sector marks are used as timing signals for read/write operations, very high detection reliability is required. However, in the conventional detection method, a false signal of a sector mark may be detected due to fluctuations in the amplitude of the reproduced signal or deterioration in resolution, resulting in low reliability.

FIG. 6 is a schematic diagram of a conventional sector mark detection circuit.

A reproduced signal 71 read from the optical disk by the optical head 1 is amplified by a preamplifier 2 and an amplifier 3 and input to a sector mark detection circuit 6. In the sector mark detection circuit 6, first, the A/D conversion circuit 4 converts the pit into a digital signal, and then the pulse width detection circuit 5 measures the dimensions of two types of oval pits, and determines that they are sector marks (SM). Based on the determination, a sector mark signal is output.

FIG. 11 is a signal waveform diagram of the data in FIG. 6. 71 is a head read signal, 72 is an output signal of the preamplifier 2, 73 is an output signal of the AGC amplifier 3, and 74 is a DC reproduction signal. both,
Since the signal waveform is a state in which reflected light is received by a resistor, the low level portion is the portion where the pit exists, and the high level portion is the portion on the disk other than the pit. The reproduced signal 71 read out by the optical head 1 is a signal with large amplitude fluctuations due to variations in the optical characteristics of the optical disk and the optical head 1, as shown in FIG. 11a. This signal 71
The preamplifier 2 produces an output waveform shown by the broken line in FIG. 11a, and the small amplitude portion is amplified.
The signal 72 input to the amplifier 3 is obtained by feedback of the output signal 73 in FIG. 11b by the AGC.
The amplitude is adjusted to a high level and a low level, resulting in a DC reproduction signal 74 shown in FIG. 11c.

12 is a waveform diagram of the sector mark portion detected by the sector mark detection circuit of FIG. 6, and FIG. 13 is a waveform diagram of the data portion detected by the sector mark detection circuit of FIG. 6.

The reproduced signal read out by the optical head is
30 in figure 2 (sector mark waveform of oval pit)
In FIG. 13, it is 42 (data waveform of circular pit). The signal reproduced by the head is
It is impossible to distinguish between sector marks and data, and they are all detected by the same circuit, but here, both signals are analyzed separately in FIGS. 12 and 13.

First, in the case of a sector mark, when the output signal 30 of the head amplifier is input to the sector mark detection circuit 6, as shown in FIG.
, this signal 30 is delayed by a delay element for a certain period of time to obtain a waveform of a signal 31 indicated by a broken line. Next, by taking the difference between the waveform before the delay and the waveform after the delay, the differential signal 33 shown in FIG. 12b is obtained. By slicing this differential signal 33 at certain binary slice levels V ⁺ and V ^- and applying these signals to the set and reset inputs of the flip-flop, a digital signal 35 as shown in FIG. 12c is obtained. It will be done. This signal 35 is a signal obtained by A/D converting the analog signal 30. but,
In such a conventional A/D conversion circuit, the values of the binary slice levels V ⁺ and V ^- are greatly influenced by the amplitude of the head output signal, and when the signal amplitude of the head output signal is small, the differential signal 33 is sliced. The level may not be reached and the digital signal 35 may not be reproduced.

On the other hand, when detecting the data in Figure 13,
After the head output signal 42 is delayed by a certain amount of time in the A/D conversion circuit 4 to obtain a signal 41, a differential signal 43 is obtained by taking the difference between the two signals. When slicing this differential signal 43 at binary slice levels V ⁺ and V ^- , if the amplitude of the differential signal 43 is small, the slice level may not be reached. Furthermore, as shown in Fig. 13 1-b, when the resolution is normal, slicing is performed normally, but as shown in Fig. 13 2-b.
As shown in b, when the resolution deteriorates, the reproduction signal resolution of the recorded information in the data section deteriorates and only a part of the differential signal is sliced, so as shown in 2-c,
Even though it is data, an erroneous digital signal 45 such as an oval pit may be reproduced and mistakenly detected as an original sector mark pattern.

[Purpose of the invention]

An object of the present invention is to improve such conventional problems, to obtain a reproduced signal with a constant signal amplitude when detecting a sector mark, and to prevent data from being erroneously detected as a sector mark due to resolution deterioration. An object of the present invention is to provide a sector mark detection circuit for an optical disk that can detect sector marks with high reliability.

[Summary of the invention]

In order to achieve the above object, the sector mark detection circuit for an optical disk according to the present invention amplifies the reproduced signal optically read out from the optical disk to a predetermined amplitude using an AGC amplifier, and directs the amplified signal to the starting point position of the sector. In an optical disk device that inputs data to a recorded sector mark detection circuit, the gap area provided between each sector recorded on the optical disk is detected using the reproduction signal, and the position of the sector mark following the gap is predicted. The present invention is characterized in that it includes means for generating a gate signal and sending it to the sector mark detection circuit, and means for switching the control time constant of the control voltage of the AGC amplifier between before and after sector mark detection.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an overall configuration diagram of a data reproducing circuit and a sector mark detecting circuit to which the present invention is applied.

In FIG. 1, 101 is an optical head for reading data and sector marks from an optical disk;
2 is a preamplifier common to data and sector marks, 1
03 is AGC amplifier, 104 is DC regeneration circuit, 1
05 is a data signal peak point detection circuit, 106 is a differentiation circuit that generates a signal indicating the peak position of the signal, 107 is a zero cross point detection circuit that is the peak point position, 108 is an AGC feedback circuit according to the present invention, and 109 is an amplitude detection circuit. 110 is a read data generation logic circuit, 111 is a differential amplitude detection circuit, 112 is a sector mark gate generation circuit according to the present invention, 113 is a sector mark detection circuit shown in FIG. 6, and 114 is an A/D converter to a digital signal. The conversion circuit 115 is a sector mark detection logic circuit for measuring the dimensions of the oblong pit.

The reproduced signal read by the optical head 101 is AC-coupled and amplified by the preamplifier 102 to obtain a reproduced signal. Since this reproduced signal has a waveform with large amplitude fluctuations as shown in FIG. 11a, it is converted by the AGC amplifier 103 into a reproduced signal with a constant amplitude (waveform 73 in FIG. 11b). A DC component is added to the output signal of the AGC amplifier 103 by the DC regeneration circuit 104 so that the potential at the peak point corresponding to the pit is constant.
A DC reproduction signal (waveform 74 shown in FIG. 11c) is obtained. The timing for controlling the AGC feedback circuit 108 is determined by the sector mark detection circuit 113.
given by. The output of the AGC amplifier 103 is connected to a peak point detection circuit 105 and converted into a pulse train corresponding to the peak point on the pit side.
The peak point detection circuit 105 includes a differentiation circuit 106 and a zero-crossing point detection circuit 107. The differential amplitude detection circuit 111 detects that the amplitude of the signal differentiated by the differentiating circuit 106 is at a predetermined level.
Detected by. On the other hand, the amplitude detection circuit 109 detects that the amplitude of the reproduced signal to which the DC component is added by the DC reproduction circuit 104 is at a predetermined level. Read data generation logic circuit 110
Now, a read data signal is generated from the pulse train corresponding to the pit-side peak point output from the peak point detection circuit 105 and the amplitude information detected by the amplitude detection circuit 109 and the differential amplitude detection circuit 111. The sector mark gate generation circuit 112 time-monitors the pulse interval of the pulse train of the read data signal, and generates a sector mark gate signal if there is no read data signal within a certain time.

The present invention solves the following two problems with conventional circuits: (a) A decrease in the sector mark detection rate and non-detection due to amplitude fluctuations of the head output signal can be solved. , head output signal
Gain control is performed by the AGC amplifier 103 to keep the signal amplitude constant, thereby eliminating erroneous detection of sector marks due to amplitude fluctuations. In addition, (b) to prevent erroneous detection of sector marks due to deterioration of data resolution in the data area, the sector mark is always located after the gap area where no data is recorded on the disk format. By adding to the mark signal detection condition that a gap portion always exists before detecting a sector mark, erroneous detection of a sector mark in the data portion is eliminated. The circuits that solve the above two problems are the AGC feedback circuit 108, the sector mark gate generation circuit 112, and the sector mark detection circuit 113.
These circuits will be sequentially explained with reference to FIGS. 4 and 5.

FIG. 2 is a detailed configuration diagram of the AGC feedback circuit of FIG. 1.

As shown in FIG. 1, the AGC feedback circuit 108 includes a DC regeneration circuit 104, a sector mark detection circuit 113, and an AGC amplifier 103.
are connected to each other.

In FIG. 2, 201 and 202 are comparators;
03 and 204 are timing signals for operating the AGC amplifier 103, which are a gain up gate signal and a gain down gate signal. 205 is a level signal (search SM signal) output when a sector mark cannot be detected. Also, 206,20
7 is a signal for increasing/decreasing the gain of the AGC amplifier 103 according to the signal amplitude of the DC reproduction signal. The voltage for gain control of the AGC amplifier 103 is generated by a capacitor C ₁ , resistors R ₁ , R ₂ , R ₃ and a power supply voltage V ⁺ , and in this case,
By discharging the capacitor C ₁ to lower the voltage, the gain of the amplifier 103 is increased, and by charging the capacitor C ₁ and increasing the voltage, the gain of the amplifier 103 is lowered. Of course, it is also possible to reverse this and control the gain of the amplifier 103.

In the DC reproduction circuit 104, gain control signals 206 and 207 for the AGC amplifier 103 are obtained by comparing the reproduction signal 74 to which the DC component has been added with a reference voltage using comparators 201 and 202. AGC voltage generation circuit 208 (part inside the broken line)
While the gain up signal 206 is output, the voltage level of the capacitor _C1 is discharged with _the time constant of _R1C1 , the AGC control voltage is lowered, and the gain of the AGC amplifier 103 is increased. In addition, the gain down signal 207
While the voltage is being output, the capacitor C ₁ is charged with a time constant of R ₂ C ₁ , the AGC control voltage is increased, and the gain of the AGC amplifier 103 is decreased. By repeating such operations, automatic gain control of the AGC amplifier 103 is performed. Here, AGC amplifier 103
The timing signals 203 and 204 that operate the
The timing signal generation circuit 209 monitors the time using the sector mark, and generates the signal at the position recorded in a certain specific pattern (in this embodiment, the highest frequency) in each sector. When no sector mark is detected, the search SM signal 20
5 sets the voltage level of capacitor C ₁ to R ₃ C ₁ (R ₃
≫R ₁ , R ₂ ) and increase the gain of the AGC amplifier 103. At this time, in order to prevent the circuit from becoming saturated due to the gain increasing too much, the timing signal generation circuit 207 generates the gain down gate signal 207 at the same time during the search SM.
Control with 9. As a result, AGC amplifier 103
operates to keep the signal amplitude at the lowest frequency, where the signal amplitude is largest, constant. When a sector mark is detected by the sector mark detection circuit 113 while the lowest frequency is controlled to be constant, the search SM signal 205 is inverted, and the gain of the AGC amplifier 103 is changed to the gain up gate signal 20.
3. It is controlled by the gain down gate signal 204. Here, search SM signal 205
can be easily created by time-monitoring whether the sector mark arrives within a certain predetermined time.

In this way, the AGC amplifier 103 transfers the sector mark and data to the A/D conversion circuit 11.
4 and the high-side and low-side slice levels of the differentiating circuit 106 to raise and lower the amplitude.

FIG. 3 is a circuit configuration diagram of the sector mark gate generation circuit of FIG. 1, and FIG. 4 is an operation time chart of the circuit of FIG. 3.

As shown in Figure 2, sector marks (hereinafter referred to as
SM) The gate generation circuit 112 receives the pulse train of the read data signal from the read data generation logic circuit 110 and monitors the pulse interval.
Generates SM gate and sector mark detection circuit 11
Send to 3. 212 and 219 are retriggerable one-shot multivibrators, and 213
is a flip-flop. In addition, in FIG. 4, 214 is the format on the disk, 215
216 is the read data of the output signal of the read data generation logic circuit 110, 216 is the output signal of the retriggerable one-shot multivibrator 219, and 21
7 is the output signal of the one-shot multivibrator 212, and 218 is the output signal of the flip-flop 213, that is, the SM gate signal.

In the format 214 on the disk in FIG. 4, the gap section (GAP) that exists before all the SM, ID, and DATA areas is an area in which no signals are written, and is the area where the pulse train in the DATA area starts. This is the period from the falling edge to the rising edge of the pulse train in the SM region. Therefore, the SM gate creation circuit 112
is the read data pulse 2 from the logic circuit 110
Retriggerable one shot 2 at the start of 15
19 and monitors that the pulse is triggered within a predetermined time. If no pulse is triggered within a predetermined time, the output signal 216 of the one shot 219 at the beginning of the gap region becomes an inverted signal (negative polarity pulse 216 in FIG. 4). Then, read data pulse 215 again
When triggered, the output signal 216 of the one shot 219 is inverted at the rising edge and becomes positive, and maintains that level until the pulse train is interrupted. The one-shot multivibrator 212 is
At the rising edge of the retriggerable one-shot multivibrator 219, a one-shot pulse 217 having a pulse width T in the SM region +α is generated. α
This is to provide extra time. By inputting the output signals of the one shots 219 and 212 to the set input terminal S and trigger input terminal T of the flip-flop 213, as shown in FIG.
The SM GATE signal 218 is obtained as an output. By sending this to the sector mark detection circuit 113, the detection circuit 113 can detect the sector mark without error within this gate period.

FIG. 5 is a configuration diagram of the A/D conversion circuit of the sector mark detection circuit in FIG. 1.

In FIG. 5, 61 is a delay element, 62 is an amplifier, 63 and 64 are comparators, and 65 is a flip-flop. Further, this A/D conversion circuit 114 is
The SM detection logic circuit 115 is connected to the output side, and the AGC amplifier 103 is connected to the input side.
SM gate generation circuit 11 is connected to one input of the gate.
2 are connected. The signal input from the AGC amplifier 103 is a sector mark waveform 30 or a data signal waveform 42 as shown in FIGS. 12a and 13a. These signal waveforms 30, 4
2 is input to this A/D conversion circuit 114, one is input to the amplifier 62 through the delay element 61, and the other is input to the amplifier 62 as it is.
Differential signal (33 in Figure 12b or Figure 13b)
43) is obtained. These signals 33, 43
are compared with certain slice levels V ⁺ and V ^- in comparators 63 and 64. Then, each output of the comparators 63 and 64 is transferred to a flip-flop 65.
By inputting to the set input terminal S and the reset input terminal R of the sector mark 35 in FIG.
Alternatively, the data signal 44 of FIG. 13c can be obtained. The output signal of the flip-flop 65 is ANDed with the aforementioned SM GATE signal 218, and a pre-SM signal is sent to the SM detection logic circuit 115. Since the SM GATE signal 218 is turned on only during the sector mark area time, only the sector mark 35 in FIG. 12c is detected and output to the SM detection logic circuit 115. Therefore, as shown in FIG. 13c, the erroneous digital signal 4 in the data
Even if 5 occurs, it will be rejected by the AND gate and the
In the SM signal, all signals outside the sector mark area are removed. The pulse width of the pre-SM signal is recognized by the SM detection logic circuit 115, a prescribed length is measured, and the pre-SM signal is output as a sector mark.

In this way, in this embodiment, even when there is no sector mark of the timing signal for executing AGC, the AGC amplifier of the read data reproducing circuit is made sufficiently larger than the time constant during original read data reproducing, so that the signal amplitude can be adjusted. By adding AGC at the highest level, a reproduced signal is obtained with a constant signal amplitude even when a sector mark is detected. Furthermore, by creating a gate signal that predicts the position of a sector mark based on the data format on the medium, erroneous detection of sector marks due to deterioration of resolution in data is prevented.

[Effects of the Invention] As described above, according to the present invention, it is possible to eliminate a decrease in the sector mark detection rate or non-detection due to amplitude fluctuations of the head output signal, and also to eliminate sector mark errors due to data resolution deterioration in the data section. Since detection can be eliminated, it is possible to detect sector marks with extremely high reliability.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a data reproducing circuit and a sector mark detection circuit to which the present invention is applied, and FIG.
Figure 3 is a detailed diagram of the sector mark gate generation circuit in Figure 1, Figure 4 is an operation timing chart of the circuit in Figure 3, and Figure 5 is the sector mark gate generation circuit in Figure 1. A block diagram of the A/D conversion circuit of the mark detection circuit, FIG. 6 is a block diagram of a conventional sector mark detection circuit, FIGS. 7 and 8 are principle diagrams of optical disc playback operation, and FIGS. 9 and 10.
The figure is an explanatory diagram of a format sector mark on an optical disk. FIG. 13 is a diagram illustrating the principle of erroneous sector mark detection during A/D conversion of a conventional data section. 101: Optical head, 102: Preamplifier, 10
3: AGC amplifier, 104: DC regeneration circuit, 10
5: Peak point detection circuit, 108: AGC feedback circuit, 113: Sector mark detection circuit, 1
12: SM GATE generation circuit.

Claims (1)

[Claims] 1. An optical disk in which a playback signal optically read from an optical disk is amplified to a predetermined amplitude by an AGC amplifier, and the amplified signal is input to a sector mark detection circuit recorded at the start position of a sector (information recording unit). In the apparatus, a gap area provided between each sector recorded on an optical disk is detected from the reproduction signal, a gate signal is generated to predict the position of a sector mark following the gap, and the sector mark detection circuit 1. A sector mark detection circuit for an optical disk, comprising means for transmitting a control voltage to the AGC amplifier, and means for switching a control time constant of the control voltage of the AGC amplifier before and after sector mark detection.