JPH0545065B2 - - Google Patents
Info
- Publication number
- JPH0545065B2 JPH0545065B2 JP61256104A JP25610486A JPH0545065B2 JP H0545065 B2 JPH0545065 B2 JP H0545065B2 JP 61256104 A JP61256104 A JP 61256104A JP 25610486 A JP25610486 A JP 25610486A JP H0545065 B2 JPH0545065 B2 JP H0545065B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- sealed semiconductor
- leads
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止型半導体装置に関し、特にデ
ユアル・イン・ライン型の樹脂封止型半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and particularly to a dual-in-line type resin-sealed semiconductor device.
樹脂封止型半導体装置は、ハーメテイツク封止
型半導体装置に比べて低原価であり量産性にもす
ぐれているが、耐湿性の面では僅かながら不足し
ている
第２図ａ，ｂは従来のデユアル・イン・ライン
型の樹脂封止型半導体装置を示す一部切欠き平面
図およびＢ−B′線断面図である。
Resin-sealed semiconductor devices are lower in cost and more easily mass-produced than hermetically-sealed semiconductor devices, but they are slightly lacking in moisture resistance. FIG. 2 is a partially cutaway plan view and a sectional view taken along the line B-B' showing a dual-in-line resin-sealed semiconductor device.
第２図ａ，ｂに示すように、従来の樹脂封止型
半導体装置は半導体チツプ１と、半導体チツプ１
を載置し釣りピン８で支持されたアイランド部６
と、アイランド部６の周辺に配置され半導体チツ
プ１のボンデイング・パツド５と金属細線４で接
続された複数のリード７を含んで構成される。 As shown in FIGS. 2a and 2b, a conventional resin-sealed semiconductor device includes a semiconductor chip 1 and a semiconductor chip 1.
The island portion 6 is placed with a fishing rod supported by a fishing pin 8.
The semiconductor chip 1 includes a plurality of leads 7 arranged around the island portion 6 and connected to the bonding pads 5 of the semiconductor chip 1 by thin metal wires 4.
〔発明が解決しようとする問題点〕
上述した従来の樹脂封止型半導体装置は、アイ
ランド部を支持する釣りピン表面と樹脂封止面の
間隙を伝わつて水が侵入し半導体装置の耐湿性を
低下させるという問題点がある。[Problems to be Solved by the Invention] In the conventional resin-sealed semiconductor device described above, water enters through the gap between the surface of the fishing pin supporting the island portion and the resin-sealed surface, impairing the moisture resistance of the semiconductor device. There is a problem of lowering the
本発明の目的は、耐湿性の良好な樹脂封止型半
導体装置を提供することにある。 An object of the present invention is to provide a resin-sealed semiconductor device with good moisture resistance.
本発明の樹脂封止型半導体装置は、デユアル・
イン・ライン型の樹脂封止型半導体装置におい
て、相対する両側より内側に向つて伸長し中央部
で接触することなく互いに入り組んだ形状をなす
複数のリードと、前記中央部で前記複数のリード
上にまたがり絶縁物を介して載置された半導体チ
ツプを含んで構成される。
The resin-sealed semiconductor device of the present invention has dual
In an in-line type resin-sealed semiconductor device, a plurality of leads extend inward from opposite sides and form an intricate shape with each other without touching in the center, and The structure includes a semiconductor chip placed across the semiconductor chip with an insulator interposed therebetween.
次に本発明の実施例について図面を参照して説
明する。
Next, embodiments of the present invention will be described with reference to the drawings.
第１図ａ，ｂは本発明の一実施例を示す一部切
欠き平面図およびＡ−A′線断面図である。 FIGS. 1a and 1b are a partially cutaway plan view and a sectional view taken along the line A-A', showing an embodiment of the present invention.
第１図ａ，ｂに示すように、デユアル・イン・
ライン型の樹脂封止型半導体装置において、相対
する両側より内側に向つて伸長し中央部で接触す
ることなく互いに入り組んだ形状をなす複数のリ
ード２と、前記中央部で複数のリード２にまたが
り絶縁物３を介して載置されボンデイング・パツ
ド５と、複数リード２の先端を金属細線４で接続
された半導体チツプ１を含んで構成される。 As shown in Figure 1 a and b, dual in
In a line-type resin-sealed semiconductor device, a plurality of leads 2 extend inward from opposite sides and form an intricate shape with each other without contacting at the center, and a plurality of leads 2 extend across the plurality of leads 2 at the center. The semiconductor chip 1 includes a bonding pad 5 mounted on an insulator 3, and a semiconductor chip 1 having a plurality of leads 2 whose tips are connected by thin metal wires 4.
〔発明の効果〕
以上説明したように本発明は、相対する両側か
ら伸長する複数のリードにまたがり絶縁物を介し
て半導体チツプを載置することによつて釣りピン
から水が侵入し易いアイランド部を排除し、樹脂
封止されるリードの長さを従来に比べ伸長して侵
水経路を実質的に長くし半導体装置の耐湿性を向
上させる効果がある。[Effects of the Invention] As explained above, the present invention has a structure in which a semiconductor chip is placed across a plurality of leads extending from opposite sides via an insulator, thereby reducing the island portion where water easily enters from the fishing pin. The present invention has the effect of eliminating this problem, increasing the length of the resin-sealed leads compared to the conventional method, substantially lengthening the water intrusion path, and improving the moisture resistance of the semiconductor device.
第１図ａ，ｂは本発明の実施例を示す樹脂封止
型半導体装置の一部切欠き平面図およびＡ−
A′線断面図、第２図ａ，ｂは従来の樹脂封止型
半導体装置の一部切欠き平面図およびＢ−B′線
断面図である。
１……半導体チツプ、２……リード、３……絶
縁物、４……金属細線、５……ボンデイング・パ
ツド、６……アイランド部、７……リード、８…
…釣りピン。
FIGS. 1a and 1b are partially cutaway plan views of a resin-sealed semiconductor device showing an embodiment of the present invention, and FIGS.
A sectional view taken along the line A', and FIGS. 2a and 2b are a partially cutaway plan view and a sectional view taken along the line B-B' of a conventional resin-sealed semiconductor device. DESCRIPTION OF SYMBOLS 1...Semiconductor chip, 2...Lead, 3...Insulator, 4...Metal thin wire, 5...Bonding pad, 6...Island part, 7...Lead, 8...
...Fishing pin.
Claims (1)
体装置において、相対する両側より内側に向つて
伸長し中央部で接触することなく互いに入り組ん
だ形状をなす複数のリードと、前記中央部で前記
複数のリード上にまたがり絶縁物を介して載置さ
れた半導体チツプを含むことを特徴とする樹脂封
止型半導体装置。1. In a dual-in-line resin-sealed semiconductor device, a plurality of leads extend inward from opposite sides and form an intricate shape with each other without contacting in the center, and 1. A resin-sealed semiconductor device comprising a semiconductor chip placed over leads of the chip with an insulator interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61256104A JPS63108761A (en) | 1986-10-27 | 1986-10-27 | Resin sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61256104A JPS63108761A (en) | 1986-10-27 | 1986-10-27 | Resin sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63108761A JPS63108761A (en) | 1988-05-13 |
| JPH0545065B2 true JPH0545065B2 (en) | 1993-07-08 |
Family
ID=17287943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61256104A Granted JPS63108761A (en) | 1986-10-27 | 1986-10-27 | Resin sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63108761A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4937656A (en) * | 1988-04-22 | 1990-06-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JPH0286153A (en) * | 1988-09-22 | 1990-03-27 | Toshiba Corp | Resin sealed type semiconductor device |
| JP4450530B2 (en) * | 2001-07-03 | 2010-04-14 | 三菱電機株式会社 | Inverter module |
| DE102007028512A1 (en) | 2007-06-21 | 2008-12-24 | Robert Bosch Gmbh | Electrical component |
-
1986
- 1986-10-27 JP JP61256104A patent/JPS63108761A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63108761A (en) | 1988-05-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |