JPH0546694A - Logic simulation method - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a logic simulation method that reduces the number of events that occur in a logic circuit that is composed of a plurality of logic elements with the same function that operate at the same time, and that enables faster processing. .. [Structure] It is applied to a flip-flop circuit that is often used in a sequential circuit, and is composed of flip-flops of the same function that operate with clock signals at the same time. Then, first, at step 101, each logic element in the logic circuit is subjected to Boolean algebra, and at step 102, the logic elements using the same connection line among the logic elements are put together to extract a common net. Further, in step 103, a group of elements having the same function connected to the common connection line is formed by grouping, and in step 104, when the connection destination of each group indicates the same group, each output line is set to 1 Put it together in a book.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method for performing logic verification of a logic device, and more particularly to an event driven method, that is, a method for simulating only a logic element in which a signal value change occurs due to an event occurrence. The present invention relates to a technique effectively applied to a logic simulation method in which the processing time is shortened and the speed is increased by the signal value propagation in the unit of a group of a plurality of logic elements in the logic verification by.

[0002]

2. Description of the Related Art As a conventional logic simulation method, for example, as shown in Japanese Patent Laid-Open No. 63-145549, each logic element of a logic circuit to be simulated is subjected to a Boolean expression for calculating a signal value. And the like, the output signal value of the logic element is obtained for each change in the signal value of the input terminal of the logic element, and the output value is connected to the output terminal as an event and propagated to the next logic element.

Further, as a method of collecting logic elements,
For example, as disclosed in Japanese Patent Laid-Open No. 63-211036, there is a method in which a common variable of a Boolean expression replaced for calculating a signal value of a logic element is calculated to be combined into an aggregate as a composite element.

[0004]

However, in the prior art as described above, the occurrence of an event due to a signal change occurs for each logic element, which causes a problem in the event processing. For example, even when repeating logic elements having the same function, which are often used in sequential circuits of data-related logic circuits, event processing is required for all logic elements. For this reason, there are many repetition processes for performing event processing. The problem is that it takes longer time.

Therefore, an object of the present invention is to provide a logic simulation method capable of reducing the number of events generated in a logic circuit composed of a plurality of logic elements having the same function and operating at the same time, and accelerating the processing. To provide.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the logic simulation system of the present invention is a logic simulation system based on the event driven system, in which a plurality of logic elements having the same function which operate at the same time in a simulation target logic circuit are set as one aggregate. A logical expression table for simulation execution in which the output signal lines of the respective logic elements of the aggregate are put together into one and connected to the connection destination, and the signal values of the respective logic elements which are made into one aggregate are collectively stored in the signal value table. It is what constitutes.

[0009]

According to the logic simulation method described above,
By constructing the logical expression table, for example, a sequential circuit structure such as a data system logical circuit has various logic elements of the same function that operate at the same time, as in the case of parallel creation corresponding to bits and bytes. At this time, the logic elements having the same function can be combined into one aggregate, and a simulation can be performed in which the number of events indicating the factor of the signal value change is reduced.

Thus, the propagation processing of the signal value change in the plurality of logic elements having the same function is performed for each unit, and the speed of the logic simulation can be increased.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flow chart showing a processing procedure for assembling logic elements of the same function in one embodiment of a logic simulation system of the present invention, and FIG. 2 is a circuit diagram showing a simulation target circuit in this embodiment. 3 is an explanatory view showing a Boolean expression of a circuit to be simulated, FIG. 4 is an explanatory view showing a Boolean expression for extracting a common net, FIG. 5 is a circuit diagram showing a logic circuit in an aggregate, and FIG. 6 is a connection of the aggregate. FIG. 7 is a circuit diagram showing a simulated target logic circuit, FIG. 7 is a circuit diagram showing a simulation target logic circuit having one connection line, FIG. 8 is a circuit diagram showing a logic circuit, and FIG. 9 is a description showing a configuration of a logical expression table. FIG. 10, FIG. 10 is an explanatory diagram showing a logical expression table, FIG. 11 is an explanatory diagram showing the structure of the logical expression table when it is an aggregate, and FIG. 12 is a processing procedure at the time of simulation execution. It is to flow diagram.

First, the structure of a simulation target logic circuit to which this embodiment is applied will be described with reference to FIG.

The logic circuit to be simulated in this embodiment is, for example, a flip-flop circuit that is frequently used in a sequential circuit, and has flip-flops (hereinafter referred to as FF) 1 to 3 having the same function, which operate with a clock signal at the same time. F
It is composed of F4 to FF6, and the output terminal of FF1 is FF.
4, the output terminal of FF2 is connected to the input terminal of FF5, and the output terminal of FF3 is connected to the input terminal of FF6. An input signal is input to each of FF1 to FF3, and an output signal is output from each of FF4 to FF6.

Next, the operation of this embodiment will be described with reference to FIGS. 3 to 7 based on the processing procedure for collecting the logic elements having the same function in the logic circuit of FIG. 1 into an aggregate. ..

First, in step 101, each logic element in the logic circuit is subjected to Boolean algebra, and as shown in FIG.
The intermediate output signal U1 of 1 is represented as U1 = CO · I1 + not (CO) · OU1 from the clock signal C0, the input signal I1, and the old intermediate output signal OU1 of the intermediate output signal U1. Similarly, the subsequent flip-flops FF2 to F
If F6 is also converted into a Boolean algebra, the intermediate output signal U
2, U3 and output signals O1 to O3 are represented as shown in FIG.

Then, among the logic elements which have been Boolean-algebraized in step 102, logic elements using the same parameter, that is, the same connection line are put together and a common connection line (net) is extracted, so that FIG. As shown, FF1 to FF3 are clocked out using clock signals C0 and not (C0), and FF4 to FF6 are clocked out with clock signals C1 and not (C1), and their common connection lines are clocked to clock signal C0. , C1 can be extracted.

Further, the elements having the same function connected to the common connection line extracted in step 103 are put together, and a group of the same logic elements is created by grouping.
As shown in FIG.
F1 to FF3 can be one aggregate 7, that is, the input signals I1 to I are set by the parameters of the clock signal C0.
3 can be defined as an input, and as a result, it can be defined as a flip-flop aggregate having a structure in which intermediate output signals U1 to U3 are obtained.

When the logic circuit of FIG. 2 is represented by a flip-flop group, a series structure of the groups 7 and 8 is formed as shown in FIG. 6, which can be easily created from the Boolean expression of FIG. ..

Further, after connecting the assemblies 7 and 8 in step 104, the connection destinations of the output connection lines of the assemblies 7 and 8 are checked, and the fan-out destinations of the output terminals of the assemblies 7 and 8, That is, when the connection destinations point to the same aggregate, the output lines are combined into one and a signal value correspondence table for the input / output terminals is created to generate the same functional elements in the logic circuit as the aggregates 7 and 8. To do.

As a result, as shown in FIG. 7, the logic circuits shown in FIG. 2 can be combined into groups 7 and 8, and the connections between the groups 7 and 8 can be combined into an intermediate output signal X. , 8 by collectively converting them into one output connection line X, it is possible to reduce the number of connections between the aggregates 7 and 8.

Next, a logic model for simulating these logic circuits, actually a logic model in the combinational logic circuit of FIG. 8, will be described below.

First, in FIG. 8, the model of the element A9 shows an AND element, which has 0 and 0 as an input signal value, 0 as an output value and a connection address C, and the element B10 is also an AND element. The input signal value has 1 and 1, and the output value has 0 and the connection destination address C. Further, the element C11 is also an AND element, and the input signal value has the input signal value 0 from the element A9 and the input signal value 1 from the element B10, and the output value 0 and the connection destination are not provided.

In this case, since this structure has a signal value to be an input of the single functional element and its output value and a connection destination,
Each input condition and signal value when aggregated,
Cannot have output destination.

In view of the above, the logical element as an aggregate has conventionally been configured with a logical expression table for each element as shown in FIG. 9, but in the present embodiment, as shown in FIG. Defines the signal value and output value of each input terminal, and the output connection destination.

That is, the function part indicates the function of the logic element as an aggregate, the input pointer points to the input value table having the signal value of the aggregated input line for each input terminal, and the output pointer is The structure is such that an output value table having the signal value of each output terminal is designated. By this method, the signal connection relation for each aggregate can be represented.

Then, using the logical model of this structure,
The procedure for advancing the simulation will be described with reference to FIGS. 11 and 12.

First, FIG. 11 shows the relationship between the event control table for sequentially propagating the signal changes of the aggregated logic circuits and the logic model table.

The time wheel 12 controls the propagation time of the output event of each logic element indicating a signal change, and the event table 13 connected from the time wheel 12 shows the output event of each logic element. Further, the event table 13 is connected to the signal value table 14, "VP" of the event table 13 indicates the signal value of the event, and "NP" is used to connect the events to be executed at the same time.

Further, each event indicates the logical model table 15, and when this time of the time wheel 12 coincides with the simulation time, the event table 13
Event is taken out, the signal value of the signal value table 14 is transmitted to the logical model table 15, and the output signal value of each logical model is obtained.

Then, for the calculated output signal value, the propagation destination address is obtained by "FOP" prepared in the logical model table 15, and the event by the event table 13 is moved to the position corresponding to the delay time of this logical model of the time wheel 12. And as the propagation signal value of the signal value table 14.

Next, the execution flow of these simulations is shown in FIG.

First, in step 1201, the timer T for managing the simulation time is set to "1". Then, step 1202 is a process of determining whether or not the simulation end time has been reached, and if the timer T is equal to the simulation end time, the process ends.

On the other hand, if it is different from the simulation end time, the input signal of the time of the timer T is registered in the event table 13 in step 1203. In this case, the event table 13 has the timer T as shown in FIG.
Is connected to the time wheel 12 shown by.

Then, in step 1204, it is determined whether or not an event exists on the time wheel 12 indicated by the timer T. For example, if there is an event at the time of the timer T, the event is extracted in step 1205 and the output value of the element indicated by the event is calculated.

In this case, when the output value of the element has changed from before, this element is created as an event in step 1206, and the event is registered at the time indicated by the time wheel 12 corresponding to the delay time of the element. And
This process is repeated until there is no event at the time of the timer T.

Further, when there is no event at the time of the timer T, the timer T is updated in step 1207 and the process returns to step 1202.

As described above, the process is repeated until the simulation end time. In the conventional method, step 1
Although the loop from 204 to step 1206 is repeated for each logic element, this system repeats the same functional logic elements as one aggregate unit.

Therefore, according to the present embodiment, a plurality of FF1 to FF3 and FF4 to FF6 having the same function at the same time are made into one aggregate 7, 8 and one output signal line of this aggregate 7, 8 is provided. To FF1 to FF6
By grouping the signal values of the above in the signal value table 14 to form a logical expression table, it is possible to perform event processing once for each of the aggregates 7 and 8. The simulation can be run.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and can be variously modified without departing from the scope of the invention. Needless to say.

For example, although the present embodiment has been described in the case of being applied to a flip-flop circuit, the present invention is not limited to the above-mentioned embodiment, and a plurality of logics having the same function and operating at the same time. It is also widely applicable to a circuit composed of elements.

In the above description, the case where the invention made by the present inventor is mainly applied to the logic simulation method by the event driven method, which is the field of use of the invention, is not limited to this and other logics are used. It is also widely applicable to simulation.

[0042]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, a plurality of logic elements having the same function which operate at the same time in the logic circuit to be simulated are
A simulation is performed in which the output signal lines of each logic element of this one aggregate are collected into one and connected to the connection destination, and the signal values of each logic element of the one aggregate are collectively stored in the signal value table. By configuring the logical expression table for use, the propagation processing of the signal value change in the plurality of logic elements having the same function can be performed in the unit of one unit, so the number of events indicating the factors of the signal value change can be reduced. can do.

As a result, since the signal value propagation of the logic element having the same function and processed at the same time can be processed by one event, the speed of the logic simulation can be increased.

[Brief description of drawings]

FIG. 1 is a flow chart showing a processing procedure for assembling logic devices of the same function in one embodiment of a logic simulation system of the present invention.

FIG. 2 is a circuit diagram showing a simulation target circuit in the present embodiment.

FIG. 3 is an explanatory diagram showing a Boolean expression of a simulation target circuit in the present embodiment.

FIG. 4 is an explanatory diagram showing a Boolean expression for extracting a common net in this embodiment.

FIG. 5 is a circuit diagram showing an integrated logic circuit in this embodiment.

FIG. 6 is a circuit diagram showing a simulation target logic circuit in which an aggregate is connected in the present embodiment.

FIG. 7 is a circuit diagram showing a simulation target logic circuit having one connection line in the present embodiment.

FIG. 8 is a circuit diagram showing a logic circuit in the present embodiment.

FIG. 9 is an explanatory diagram showing the configuration of a logical expression table in the present embodiment.

FIG. 10 is an explanatory diagram showing a logical expression table in the present embodiment.

FIG. 11 is an explanatory diagram showing a configuration of a logical expression table in the case of forming an aggregate in the present embodiment.

FIG. 12 is a flowchart showing a processing procedure when a simulation is executed in the present embodiment.

[Explanation of symbols]

 1-6 FF (flip-flop) 7,8 aggregate 9 element A 10 element B 11 element C 12 time wheel 13 event table 14 signal value table 15 logical model table

Claims (1)

[Claims] 1. A logic simulation method based on an event-driven method, wherein a plurality of logic elements having the same function and operating at the same time in a simulation target logic circuit are set as one set, and the output of each logic element of the one set is set. A logical expression table for simulation execution is constructed in which the signal lines are combined into one and connected to a connection destination, and the signal values of the respective logic elements in the one aggregate are collectively stored in a signal value table. A logic simulation method characterized in that propagation processing of a signal value change in a logic element having a function is performed in units of an aggregate.