JPH0546736B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a detector for detecting a frequency modulated signal using a binary digital signal, and particularly relates to a detector suitable for integration into an integrated circuit.

(Prior art and its problems) A so-called direct conversion method is known as a method for realizing a frequency detector using an integrated circuit. This method has the advantage that filtering and other processing can be performed at the baseband because the frequency of the received wave is directly converted to the baseband. Conventionally known baseband signal processing methods using differentiation and multiplication have the advantage of being able to demodulate signals modulated with analog signals, but on the other hand, they require automatic gain adjustment and circuit balance. The drawback was that it was quite difficult to implement the circuit.

In other words, in conventional frequency detectors using the direct conversion method, for example, British Patent No. 1530602, “Demodulator for FM
As shown in ``Signals,'' this requires an automatic gain control circuit and a multiplication circuit, which makes it difficult to implement the circuit.As is well known, in a frequency detector, the input signal It is necessary to suppress amplitude fluctuations.This amplitude fluctuation, for example, is
Since the amplitude ranges over 80 dB, the dynamic range of the circuit for suppressing this is extremely large. In a conventional frequency detector using an intermediate frequency, an easy-to-implement amplitude limiting circuit can be used as a method for suppressing amplitude fluctuations of an input signal. However, in the direct conversion method, if the received signal is frequency-converted directly to the baseband band, and amplitude limitation is performed in the baseband band, harmonic distortion cannot be separated. Therefore, an automatic gain control circuit that is a linear circuit is required.

However, this circuit is more difficult to implement than an amplitude limiting circuit. Furthermore, it is a well-known fact that in a multiplication circuit, it is necessary to maintain linearity with respect to two input signals, and that it is difficult to achieve this.

(Object of the Invention) The present invention makes it possible to use an amplitude limiting circuit in the baseband band by limiting the detection target to a signal modulated by a binary digital signal among frequency modulated waves. The object of the present invention is to provide a frequency detector that does not require a multiplication circuit and is easy to implement.

(Structure of the Invention) According to the present invention, when a signal to be detected which is frequency modulated by a binary digital signal is input,
a frequency conversion means for outputting 4N baseband signals (here, N is a positive integer) having mutually different phases, including at least a local oscillator having a frequency substantially equal to the center frequency of the modulated wave signal;
Obtained by binarizing 4N baseband signals
A means for generating 4N binarized signals, and a means for arranging the 4N binarized signals so that their phases are modulo 180°, and sequentially taking every other signal. The entire signal is defined as a first signal group, the remaining binarized signals are defined as a second signal group, and the first signal group is further divided into every other signal in the order of the phases. When the entire signal group is a third signal group, and the remaining signals are a fourth signal group, a first signal group that inputs all the signals included in the first signal group
a second exclusive OR circuit that receives all the signals included in the second signal group as input, and a third exclusive OR circuit that receives as input the signals of the first signal group. Each time the state of any one of the signals in the signal group changes, one of the binary signal states is selected, and each time the state of any signal in the fourth signal group changes, the binary signal is selected. means for obtaining a reference signal generated by selecting the other state of the reference signal and the first state;
a third exclusive OR circuit which receives as input the output of the exclusive OR circuit; The above object can be achieved by having a means for sampling the output of the exclusive OR circuit and using a signal obtained from this sample value as a detection output.

(Example) A detailed explanation will be given below using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. When the received wave frequency-modulated with a mark or space binary digital signal is input to the input terminal 11, the output of the local oscillator 30 having an oscillation frequency approximately equal to the center frequency of the received wave is sent to the phase difference separation circuit 3.
Mixers 21, 22, 23,
24, the frequency is converted to baseband. The low-pass filters 31, 32, 33, and 34 extract only the baseband signal of the desired channel and limit the noise band. The baseband signals are transmitted through binarization circuits 41, 42, and 4, respectively.
3, 44 and binarized signals I ₁ , Q ₁ ,
I ₂ and Q ₂ are obtained. These signals have a phase difference corresponding to the phase difference given by the phase difference separation circuit 35, as shown in FIG. Here, the solid line indicates the case where the modulated signal is a mark, and the broken line indicates the case where the modulated signal is a space. By inputting the signals I ₁ and Q ₁ to the exclusive OR circuit 62 and the signals I ₂ and Q ₂ to the exclusive OR circuit 61, the signals I ₁ and Q ₁ and the signal I ₂ Q ₂ are input to the second obtained as shown in the figure. Also, the signals I ₁ and Q ₁
By inputting to the reference signal generation circuit 70,
A reference signal Z is obtained. This signal is derived from the output of a set-reset circuit that is set at the change of state of signal _Q1 and reset at the change of state of signal _I1 , and is independent of whether the modulating signal is a mark or a space. By inputting this reference signal and the signal I ₁ Q ₁ to the exclusive OR circuit 75, the output signal Alternatively, depending on the space, the logic level becomes "1" (solid line) or "0" (broken line), indicating that frequency detection is performed. The thin pulse portion occurs because the state change times of the signals I ₁ Q ₁ and Z input to the exclusive OR circuit 75 are slightly shifted due to imperfections in the circuit. Although the effect of this pulse portion can be reduced using a low-pass filter, the effect is not complete. Therefore, in the present invention, the signal X is sampled by the D-type flip-flop 90 using the pulse signal DI ₂ Q ₂ obtained by inputting the signal I ₂ Q ₂ to the pulse generating circuit 80 as a clock pulse. Pulse signal DI ₂ Q ₂
As shown in FIG. 2, since the signal X is generated in the middle of the generation time of the pulse-like portion of the signal X, the influence of the pulse-like portion can be eliminated.

For example, as shown in FIG. 3, the pulse generation circuit 80 splits a signal input into an input terminal 311 into two, passes one through a delay circuit 320, and then inputs it into an exclusive OR circuit 330. , a pulse is generated at the output terminal 312 each time the state of the input signal changes. Since this operation is well known, further explanation will be omitted here.

The reference signal generation circuit 70 can be implemented as shown in FIG. 4, for example. Signal Q ₁ is input to input terminal 411,
After the signal I ₁ is input to the input terminal 413, it is input to the pulse generation circuits 421 and 422, respectively.
A pulse is generated at each signal change point. The pulses generated at the change points of signal _Q1 set the set-reset circuit 430 and the signal
The pulse generated at the change point of I ₁ resets the set-reset circuit 430 so that a reference signal as shown in FIG. 2 is available at the output terminal 412.

The phase difference between the signals I ₁ , Q ₁ , I ₂ , and Q ₂ is not limited to 45°, and can be any value other than zero.
This can be easily understood by drawing a waveform diagram like the one shown in Figure 2. Furthermore, it can be confirmed that the number of baseband signals is not limited to four, and even if it is increased to 4N, similar operation can be obtained.
For example, if the baseband signal is 0°, 22.5°, 45°,
Consider increasing to eight signals with relative phases of 67.5°, 90°, 112.5°, 135°, and 157.5°. At this time, the signals with phases of 0°, 45°, 90°, and 135° are all set as the first signal group, and the remaining signals are set as the second signal group.
If the signal group is , the change time of the signals included in the second signal group is intermediate between the change times of the signals in the first signal group. Of the second signal group, if the signals with phases of 0° and 90° are the third signal group, and the signals with the phases of 45° and 135° are the fourth signal group, then the third signal group The reference signal can be generated by a set-reset circuit that is set at the change point of the signal of the fourth signal group and reset at the change point of the signal of the fourth signal group. By inputting the signal obtained by inputting all the signals of the first signal group to the exclusive OR circuit and the reference signal to the exclusive OR circuit, the signal X as shown in FIG. is obtained.

If the signals of the second group are input to the exclusive OR circuit and then input to the pulse generation circuit as shown in Figure 3, the sample pulses obtained will be
This sample pulse is generated at an intermediate time between the change times of the signal group, in other words, avoiding the pulse-like part included in signal X, so this sample pulse can be used to sample signal X with a sample circuit. .

Here, the essential thing is to classify the phases of the signals by arranging them in order. However, if the phase difference exceeds 180°, it is necessary to arrange them in an order modulo 180°. This can be easily understood by drawing a waveform diagram.

The method of providing a phase difference between baseband signals is not limited to the method of providing a phase difference between local oscillation signals as in the embodiment of the present invention. good. Also the signals I ₁ and Q ₁
It works similarly if I replace the signals I ₂ and Q ₂ . Furthermore, a combination of a circuit in which the signals are exchanged in this way and the original circuit is also possible. Note that in the above explanation, after the baseband circuit, the above-mentioned processing can be performed using a microprocessor or the like after first converting to a digital value.

(Effects of the Invention) As explained above, all the circuits after the mixer operate at the baseband, and all the circuits after the binarization circuit can be configured with digital circuits, so the present invention facilitates implementation using integrated circuits. effective. The baseband circuit and subsequent circuits can also be realized by once converting into digital values and then using a microprocessor or the like to perform signal processing according to the method shown in the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the present invention, FIG. 3 is a block diagram showing a pulse generation circuit used in the present invention, and FIG. 4 is a block diagram showing an example of the present invention. FIG. 2 is a block diagram showing a reference signal generation circuit used in the present invention. In these figures, 11,311,411,
413 is an input terminal, 12, 312, 412 is an output terminal, 21, 22, 23, 24 is a mixer, 31,
32, 33, 34 are low pass filters, 41, 4
2, 43, 44 are binarization circuits, 61, 62, 7
5,330 is an exclusive OR circuit, 80,421,
422 is a pulse generation circuit, 90 is a D-type flip-flop circuit, and 430 is a set-reset circuit.

Claims (1)

[Claims] 1 A signal frequency-modulated by a binary digital signal is input, and 4N local oscillators (here, N
is a positive integer); a means for generating 4N binarized signals obtained by binarizing the 4N baseband signals; and binarization of the 4N baseband signals. When the signals are arranged in an order in which their phases are modulo 180°, the entire set of signals taken every other signal in order is set as the first signal group, and the remaining binary signals are set as the first signal group. 2 signal groups, and the first signal group is further taken for every other signal in the order of the phases, and the entire signal obtained is defined as a third signal group,
When all of the remaining signals are considered as a fourth signal group, a first exclusive OR circuit that receives as input all the signals included in the first signal group, and a first exclusive OR circuit that receives all the signals included in the first signal group; a second exclusive OR circuit that receives all the signals;
With the signals of the signal group as input, one of the states of the binary signals is selected each time the state of any of the signals of the third signal group changes, and one of the states of the fourth signal group is selected. means for obtaining a reference signal generated by selecting the other state of the binary signal each time the signal state of the signal changes; and inputting the reference signal and the output of the first exclusive OR circuit. a third exclusive OR circuit; and means for sampling the output of the third exclusive OR circuit every time the state of any one of the signals included in the second signal group changes. 1. A frequency detector comprising: a frequency detector, wherein a signal obtained from the output of the sampling means is used as a detection output signal.