JPH0547169A - Memory control system - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] The present invention relates to a memory control method in a FIFO in which data is sequentially written and read by a first-in first-out method, and an object thereof is to prevent data from overflowing and to have good memory efficiency. First, N data areas are first acquired from a memory area 1 in which a predetermined area can be acquired and released, and data is sequentially written and read by a first-in first-out method.
Of the FIFO 2, and when data is written in all N data areas and accumulated without being read out, another M (= N or ≠ N) data areas are acquired and similarly first-in first-out A second FIFO 3 for sequentially writing and reading data according to the method is configured, and while writing data to the second FIFO 3 is sequentially started, data is sequentially read from the first FIFO 2 and then the first FIFO 2 is read. When the reading of all data from the first FIFO 2 is completed, the first FIFO 2 is released to the memory area 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control system, and more particularly to a memory control system in a FIFO for sequentially writing and reading data by a first-in first-out system.

[0002]

2. Description of the Related Art Conventionally, with respect to this type of memory control method, a maximum amount of data which is first written and not stored in the FIFO and stored without being read is predicted from a memory area corresponding to the expected maximum amount. This is done by acquiring the required number of data areas. It should be noted that these data areas are virtually positioned so that the data area of the TOP address is next to the data area of the BOTTOM address so that the data can be sequentially written and read by the first-in first-out method according to the event generated as the FIFO. The ring-shaped structure shown in FIG.

[0003]

However, in the above-mentioned one, since the maximum amount of data to be stored is predicted and the required number of data areas corresponding to the expected maximum amount are acquired. In the unlikely event that a large number of events occur and the amount of data that should be accumulated exceeds the expected maximum amount, there is a problem in that data cannot be handled and data overflows.

Further, when the number of events is small and the amount of data to be stored is small with respect to the expected maximum amount, there is a problem that the memory efficiency is low. The present invention is
It is an object of the present invention to provide a memory control method that does not cause data overflow and has good memory efficiency, with the aim of solving such problems.

[0005]

In order to achieve the above-mentioned object, the memory control method according to the present invention obtains and opens a predetermined area as shown in the block diagram of the principle structure of FIG. Solution) First, N data areas are first acquired from the releasable memory area 1 and the first FIFO 2 for sequentially writing and reading data by the first-in first-out method is constructed, and then all of these N data areas are formed. When the data is written to and accumulated in the memory without being read, another M (= N or ≠ N) data area is acquired, and similarly the second FIFO 3 for sequentially writing and reading data by the first-in first-out method is used. Configure this second FIF
While sequentially writing data to O3, the first
Data is sequentially read from the first FIFO 2 and when the reading of all data from the first FIFO 2 is completed, the first FIFO 2 is released (released) to the memory area 1. Is.

[0006]

From the memory area 1 in which a predetermined area can be acquired and released (released), it is assumed that a data area of 1 byte is required for one event, in other words, data for one event. , In short, N
Acquire individual data areas. The acquired N data areas are configured in the first FIFO 2 for sequentially writing and reading data by the first-in first-out method. Normally, when data writing and reading are performed almost alternately, data writing and reading is performed on the N data areas which are the first FIFO 2.

However, when the number of occurrences of events increases and N bytes of data, in other words, data is accumulated in all N data areas, the occurrence of the next event is shown in FIG. Other new M (= N or ≠ N) data areas are acquired from the memory area 1 as described above. The acquired M data areas are similarly configured in the second FIFO 3 for sequentially writing and reading data by the first-in first-out method. This second FIF
Data is sequentially written into the M data areas of O3 from the TOP address, and the reading of N times from the acquisition of these M data areas is the first FIF.
It is performed from N data areas which are O2. When these readings of N times are completed, the N data areas forming the first FIFO 2 are released (released) to the memory area 1 again as shown in FIG. 1 (B).

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a specific embodiment in which the memory control system according to the present invention is applied to a fire fighting system will be described with reference to the drawings. First, in FIG. 2 schematically showing the fire-fighting system S, a command board 11 for communicating with each of the telephones A to N in a wired and / or wireless manner is provided with a microcomputer 12 for calling each of the telephones A to N. Has been.
The microcomputer 12 includes a central processing unit (CPU) 12A that executes a predetermined program, a read-only memory (ROM) 12B that stores a program including an operating system program in advance, a memory area created as a memory pool, and a normal memory. A readable / writable memory (RAM) 12C in which a memory area to which variables and flags are assigned is set, and a keyboard 12D as an input device.
And a monitor 12E as a display device. The memory area created as a memory pool in the RAM 12C is a memory area for transmission between tasks that can be commonly used by the tasks, and is a memory area in which the FIFO of the present invention is configured. Also, the memory area to which ordinary variables and flags are allocated is a memory area in which only the necessary areas are acquired in the order in which they are declared, and that area is fixed. A user program such as a program configuring the FIFO of each of the telephones, and further, in the present embodiment, each telephone A to
This is a memory area in which a table of telephone numbers for calling N is stored. Although not shown, the command board 11 is provided with a handset for transmitting and receiving to and from each of the telephones A to N, and a ten-key pad for sequentially inputting a series of telephone numbers. There is.

In the microcomputer 12, the telephone numbers etc. for calling the respective telephones A to N stored as a table in a memory area to which ordinary variables and flags of the RAM 12C are assigned are monitored by an operation instruction from the keyboard 12D.
E is displayed in the list. The telephone number selected and instructed by the keyboard 12D from the telephone numbers displayed in this list is a series of numbers constituting the telephone number in the FIFO formed in the memory area created as the memory pool of the RAM 12C. It is written in order and accumulated once in a batch. Next, a series of numbers constituting the stored telephone number is read out in a time-sequential manner at intervals of time, and the read-out number, in other words, the telephone number is used via the exchange 13 and the network 14. It is connected to the desired telephones A to N.

Next, each memory area of the RAM 12C in this embodiment will be described with reference to FIG. The memory area 20 created as a memory pool has 8 bytes as 1
It consists of 64 blocks from address 0 to address 63, and has a total storage capacity of 512 bytes.

On the other hand, another memory area in the RAM 12C
Reference numeral 21 is a memory area in which ordinary variables, flags, etc. are stored, and 25 blocks, each of which has 8 bytes as one block, are successively allocated and acquired from a certain address by declaration, and 25 blocks are sequentially declared. In other words, you get 200 bytes each. Therefore, if only 100 bytes of the 25 blocks acquired by declaration are used, the remaining area is idle.

By the way, from the memory area 20 generated as a memory pool when one FIFO is formed by the user program for forming the FIFO, four blocks, in other words, a 32-byte FIFO area 22 is formed. Acquired based on the operating system program. These 32 bytes FIFO area
An area 22A for 10 bytes of 22 is used to store the next control data. The remaining 22-byte area 22B has data of 1 byte each, and in the present embodiment, one number of a telephone number as one event is stored in each data area. It is configured in the data area.

"NEXT": The addresses of the four blocks acquired when the next FIFO is constructed are stored. If four blocks forming the next FIFO are not acquired, "NULL" is stored. "TOP": The address "0" of the head data area in the 22 address sequential data areas is stored.

"BTM (BOTTOM)": The address "21" of the tail data area in the 22 address sequential data areas is stored. "HEAD": Next, the address of the data area where the data is written is stored. “TAIL”: The address of the data area from which data is read next is stored. Lastly, the basic operation of the fire-fighting system configured as described above to which the memory control method of the present invention is applied will be described with reference to FIG.

Step A As described above, when one telephone number is selected from the telephone numbers displayed in the list on the monitor 12E by the keyboard 12D, four blocks from the memory area 20 created as the memory pool of the RAM 12C. FI
Acquire the FO area 22 based on the operating system program. Step B "NEXT", "TO
P ”,“ BTM ”,“ HEAD ”and“ TAIL ”
Then, set the initial value as follows.

“NEXT” = “NULL” “TOP” = “HEAD” = “TAIL” = “0” “BTM” = “21” Step C Configure one telephone number selected by the keyboard 12D 1 When a series of numbers is being received, the next one number is written in the data area of the address indicated by "HEAD" so that the series of numbers are written one by one in each data area.

Step D Update routine of "HEAD". Details will be described later with reference to the flowchart shown in FIG. Step E The reception of a series of numbers constituting one telephone number selected and instructed from the keyboard 12D is completed and time-out occurs, and "HEAD" and "TAI" are displayed.
If the addresses pointed to by L "are not equal and data is written in the data area forming the FIFO," T "
Data is read from the data area of the address indicated by "AIL", in other words, one number related to a series of numbers forming the telephone number.

Step F "TAIL" update routine. Details will be described later with reference to the flowchart shown in FIG. Update routine for "HEAD" (FIG. 5) Step D-1 If the address indicated by "HEAD" plus 1 is equal to the address indicated by "TAIL", or if the address indicated by "TAIL" and "TOP"
Are equal to each other and the address indicated by "HEAD" is equal to the address indicated by "BTM",
Since the numbers of telephone numbers are written in all the data areas, the memory area 20 is used to configure the next FIFO.
From this, a new 4-block FIFO area 22 'is acquired based on the operating system program.

Step D-2 "Set value in NEXT for the previous FIFO and" NEXT for the next FIFO "
Initial values are set to T "," TOP "," BTM "," HEAD ", and" TAIL "as follows: Previous FIFO;" NEXT "= 4 blocks acquired when configuring the next FIFO Address of the FIFO area 22 'of the next FIFO; "NEXT" = "NULL""HEAD" = "TAIL" = "TOP" = "0""BTM" = "21" Steps D-3, D-4 "HEAD" If the address indicated by "" plus 1 and the address indicated by "TAIL" are not equal, or the address indicated by "TAIL" is not equal to the address indicated by "TOP", or "HE"
When the address indicated by "AD" and the address indicated by "BTM" are not equal, and when the address indicated by "HEAD" and the address indicated by "BTM" are equal, "HE"
The write address is advanced with the address of "AD" as the address of "TOP", or "H" when the address indicated by "HEAD" and the address indicated by "BTM" are not equal.
The address of EAD "is incremented by 1 and the write address is similarly advanced.

"TAIL" update routine (FIG. 6) Steps F-1, F-2 "NEXT" is "NULL"
And the address indicated by "TAIL" and "B
When the addresses indicated by TM "are the same," TAIL "
The read address is advanced by using the address of "NO" as the address of "TOP". Also, the address indicated by "TAIL" and "B
When the addresses indicated by "TM" are not equal, "TAI
The address of L "is incremented by" 1 "and the read address is similarly advanced.

Step F-3 "NEXT" is "NUL"
When it is not L, and the address pointed to by "TAIL" plus 1 is equal to the address pointed by "HEAD", or the address pointed by "TAIL" and "BT"
When the addresses indicated by "M" are equal and the address indicated by "HEAD" is equal to the address indicated by "TOP", a series of telephone numbers is read from all data areas related to the previous FIFO. FI
The FIFO area 22 forming the FO is opened (released) to the memory area 20.

Steps F-4 and F-5: If "NEXT" is not "NULL" and the address pointed to by "TAIL" plus one is not equal to the address pointed by "HEAD", or "TAIL" When the address indicated by "" and the address indicated by "BTM" are not equal or the address indicated by "HEAD" and the address indicated by "TOP" are not equal, the "TAIL" address and the "BTM" address are Are equal, "TAI
The read address is advanced with the address of "L" as the address of "TOP", and the address of "TAIL" and "B"
If the address of TM "is not equal," TAIL "
Is incremented by "1" and the read address is advanced in the same manner.

[0023]

As described above, according to the present invention, it is possible to newly acquire or even open (release) a data area forming a FIFO corresponding to the amount of data to be stored. As a result, the data does not overflow and the memory efficiency is good.

[Brief description of drawings]

FIG. 1 is a principle block diagram for explaining a principle configuration of a memory control method according to the present invention.

FIG. 2 is a schematic block diagram of an embodiment when the memory control system according to the present invention is applied to a fire fighting system.

FIG. 3 is a configuration diagram of a memory area described in FIG.

FIG. 4 is a flowchart of a main routine of a user program which constitutes the FIFO described in FIG.

FIG. 5 is a flowchart of the “HEAD” update routine described in FIG.

FIG. 6 is a flowchart of the “TAIL” update routine described in FIG.

FIG. 7 is a conventional explanatory view.

[Explanation of symbols]

 1, 20, 21 Memory area 2 First FIFO 3 Second FIFO 11 Command board 12 Microcomputer 12A CPU 12B ROM 12C RAM 12D Keyboard 12E Monitor 13 Switch 14 Line network 22 FIFO area

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuyuki Sashikawa 1-4-4 Hakataekimae, Hakata-ku, Fukuoka-shi, Fukuoka Prefecture Fujitsu Kyushu Communication Systems Limited (72) Inventor Mika Nakamura Hakata-ku, Fukuoka-shi, Fukuoka Hakata Ekimae 1-4-4 Fujitsu Kyushu Communication Systems Limited (72) Inventor Masahiro Nihei 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (1)

[Claims] 1. A first FIFO 2 which first acquires N data areas from a memory area 1 capable of acquiring and releasing a predetermined area and sequentially writes and reads data by a first-in first-out method, When data is written in all of these N data areas and accumulated without being read out, another M (= N or ≠ N) data areas are acquired and similarly data is sequentially written by the first-in first-out method. A second FIFO 3 for reading is constructed, and data writing to the second FIFO 3 is sequentially started, while data is sequentially read from the first FIFO 2 and all data from the first FIFO 2 is read. The memory control method wherein the first FIFO 2 is opened to the memory area 1 when the reading of the data is completed.