JPH054755B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention uses three access ports, three memories, and three 2-port memories to access up to three pieces of data at the same time. The present invention relates to a multiport memory device that speeds up shared memory access in a multiprocessor system consisting of a plurality of processors that share memory.

(Technical) As the processing demands on computer systems have become more complex and sophisticated, expectations have increased for parallel processing using multiprocessor systems, which have multiple processors, which are the processing core of computer systems. There is. There is a method of using a shared memory as a means of transmitting information between multiprocessors. As a means of realizing shared memory, there is a bus coupling method in which a plurality of processors and memories are coupled via a bus and dedicated hardware (arbiter) is used to arbitrate the right to use the bus.

(Problem to be Solved by the Invention) In the conventional shared memory system using the bus coupling system, the arbiter that arbitrates the right to use the bus determines one processor to access the shared memory. This solved the problem of competing for shared memory between multiple desired processors. That is, the arbiter arbitrates shared memory access rights, thereby sequentially processing shared memory access requests from a plurality of processors. Therefore, as the number of processors that make up a multiprocessor system increases, the frequency of shared memory access increases, and in the conventional method that processes shared memory accesses sequentially, shared memory accesses become a bottleneck, causing processors to There was a problem that the effect of multiple parallel processing could not be fully demonstrated.

An object of the present invention is to process shared memory access in parallel, which was processed sequentially in the conventional technology, by providing three access ports and making it possible to access three pieces of data at the same time. The purpose of the present invention is to provide a multi-port memory device that can be used.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a multi-port memory device that targets data with a width of 1 bit and has three terminals dedicated to input and output.
memories A, B, and C, and three 2-port memories AB, BC, and CA with two sets of input and output terminals.
and the memory A and the 2-port memory AB,
a decoder A that decodes the output of the CA and outputs it to the output port A; the memory B; and the port memory;
a decoder B that decodes the outputs of AB and BC and outputs the decoded outputs to the output port B; a decoder C that decodes the outputs of the memory C and the two-port memories BC and CA and outputs the decoded outputs to the output port C; three comparators A, which compare the output of the device and the input data from the input port;
B, C, three exclusive OR circuits that invert the data stored in the memories A, AB, CA according to the mismatch signal of the comparator A, and the storage of the memories B, AB, BC according to the mismatch signal of the comparator B. Consists of three exclusive OR circuits that invert data, and three exclusive OR circuits that invert the data stored in memories C, CA, and BC according to the discrepancy signal from comparator C. By rewriting the data stored in the memory and the two 2-port memories, the values of the data read from the three output ports at the same address will always be the same, and the value of the data at the same address read from the three output ports will always be the same. It is characterized by being accessible.

(Function) The multiport memory device of the present invention encodes 1-bit data into a 6-bit code so that three pieces of data can be accessed simultaneously.
stored in memory. That is, six memories are used to store one bit of data. The memory section for storing data is constructed by connecting three memories and three 2-port memories as shown in FIG. A two-port memory can read two data, write two data, or read one data and write one data in one access. When accessing using input port A or output port A, memory 101 and 2-port memory 104,1
Use 05. In the case of data reading, the decoder 111 decodes the outputs of the memory 101 and 2-port memories 104 and 105, and reproduces the stored data. In the case of data writing, the stored data is read out, and the comparator 121 compares the written data with the stored data. Comparisons are made bit by bit. It is not necessary to rewrite bits for which the comparison results are equal. Therefore, the memories 101, 10
The information of the corresponding bit stored in 4,105 is not changed. Bits for which the comparison results do not match must be inverted. This bit inversion operation is performed by memory 10
1,104,105 are stored. This is achieved by inverting all bit information.

Similarly, when accessing using input port B or output port B, memory 102 and 2-port memories 104 and 106 are used. For data reading, memory 102, 2-port memory 1
The decoder 112 decodes the output of 04, 106 and reproduces the stored data. In the case of data writing, read the stored data and comparator 1
22 compares the written data with the stored data, and manipulates the corresponding bit information stored in the memories 102, 104, and 106. When accessing using input port C or output port C, memory 103 and 2-port memory 10
A decoder 113 decodes the output of 5,106 and reproduces the stored data. In the case of data writing, the stored data is read and the comparator 12
3 compares the written data with the stored data, and operates the corresponding bit information stored in the memories 103, 105, and 106. Decoder 1
11, 112, and 113 output '1' when the three inputs have odd parity, and output '0' when the input has even parity. 131, 132, 133, 134, 1
35, 136, 137, 138, and 139 are arithmetic units that operate on bit information stored in the memory according to instructions from the comparators.

The operating principle of the multiport memory device of the present invention will be explained using the drawings. FIG. 3 shows the state when the value of an arbitrary address 'a' is read out to three output ports. The data stored in the memories 101, 102, 103 and the 2-port memories 104, 105, and 106 are all '0', and the data at address 'a' is also '0'. Since the inputs of decoders 111, 112, and 113 are all '0', the parity is even.
The outputs of 11, 112, and 113 are '0'.

FIG. 4 shows the operation of writing data '1' to address 'a' using input port A. Since the input to the decoder 111 is the output '0' of the memories 101, 104, and 105, the output of the decoder 111 is '0'. Comparator 121 receives input data '1' from input port A.
and the output '0' of the decoder 111 are compared. Since the comparison result is a mismatch, the comparator 121
1,134,136 memory 101,104,1
Instructs to invert the stored data of 05. As a result,
The data stored in the memories 101, 104, and 105 are '
Changes to 1'. Three memories 101, 1 determine the data of output port A by inverting this stored data.
This means that the stored data of 04 and 105 has changed. Memory 104 is involved in the determination of output port B data. Two-port memory 105 is involved in determining the data of output port C.

FIG. 5 shows the state of the stored data after it has been changed by the write operation shown in FIG. The input to the decoder 111 is the data stored in the memories 101, 104, 105.
1', '1', '1', which is odd parity, so the data at output port A is '1'. Decoder 112
The inputs are the stored data '0', '1', '0' of the memories 102, 104, and 106, and are odd parity, so the data at the output port B is also '1'. The input to the decoder 113 is the stored data '0', '1', and '0' in the memories 103, 105, and 106, which are also of odd parity, so the output of the output port C is also '1'. Therefore, it can be seen that the change of data at address 'a' to '1' by the write operation using input port A is reflected in all output ports.

FIG. 6 shows the operation of writing data '0' to address 'a' using input port B. The decoder 112 receives the outputs '0', '1' of the memories 102, 104, 106,
Since it receives '0' as input, it outputs '1'.
Comparator 122 receives input data from input port B'
0' and the output '1' of the decoder 112 are compared. Since the comparison result is a mismatch, the comparator 122
32, 135, 138, memory 102, 104,
106 is instructed to invert the stored data. As a result, the data stored in the memories 102, 104, and 106 change to '1', '0', and '1'. Memory 104 is involved in data determination of output port A, and memory 106
is related to data determination of output port C.

FIG. 7 shows how the stored data is changed by the write operation shown in FIG. The input to the decoder 111 is the stored data '1' in the memories 101, 104, 105;
Even parity is '0' and '1', and the input to the decoder 112 is the data stored in the memories 102, 104, and 106.
1', '0', '1', again with even parity, the input of the decoder 113 is the 2-port memory 103, 105,
Since the stored data of 106 are '0', '1', and '1', and the parity is even, the data of output ports A, B, and C are '0'. From the above, it can be seen that the result of writing data using any input port is reflected on all output ports.

As a result, it can be seen that in the multiport memory device of the present invention, three pieces of data can be accessed in one access.

(Example) Examples of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of a multiport memory of the present invention.

101, 102, 103 are general access ports with 1 memory, 104, 105, 106 are 1 memory
Two data can be accessed in one access 2
This is port memory. In a read operation using access port A, data stored in the memory 101, 2-port memories 104, 105 is read by the decoder 111.
decodes the data and reproduces the data at the corresponding address. As a decoder, a parity generator that outputs '1' with odd parity can be used. In a write operation using access port A, first, memory 10
Arithmetic units 131, 134, 1 read data stored in the 1 and 2 port memories 104, 105, the comparator 121 compares the read data and the write data, and inserts a mismatch signal into the path of the write data.
Send to 36. In this case, exclusive OR circuits can be used as these arithmetic units. If the comparison result is a match, the mismatch signal sent from the comparator 121 to the arithmetic unit is '0', so the arithmetic unit rewrites the data stored in the memory once again. If the comparison result is a mismatch, the mismatch signal sent from the comparator 121 to the arithmetic unit is '1', so the arithmetic unit inverts the data stored in the memory and writes it into the memory. 3
Each access port can be used to access different addresses, so one access port can be used to access three different addresses.
Individual data can be accessed.

(Effects of the Invention) The multi-port memory device of the present invention uses three memories and three two-port memories, and at the time of a data write operation, the data stored in the memory is inverted based on the comparison result of data stored in the memory and written data. 3 in one access by determining whether or not
It allows access to individual data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a multiport memory device of the present invention, and FIGS. 2 to 7 are diagrams for explaining the operation of the present invention. In the figure, 101, 102, 103 are memories, 104, 105, 106 are 2-port memories,
111, 112, 113 are decoders, 121, 12
2,123 is a comparator, 131,132,133,
134, 135, 136, 137, 138, 13
9 is a computing unit.

Claims (1)

[Claims] 1. Three memories A, B, and C that handle 1-bit wide data and have terminals dedicated to input and output,
three two-port memories AB, BC, and CA each having two sets of input and output terminals, and a decoder A that decodes the outputs of the memory A and the two-port memories AB and CA and outputs the decoded outputs to the output port A. , a decoder B that decodes the outputs of the memory B and the two-port memories AB and BC and outputs them to the output port B; and a decoder B that decodes the outputs of the memory C and the two-port memories BC and CA and outputs them to the output port C. Comparing the output of the decoder C with the output of the decoder and the input data from the input port 3
three exclusive OR circuits that invert the data stored in the memories A, AB, and CA according to the discrepancy signal of the comparator A, and the comparator B
three exclusive OR circuits that invert the data stored in the memories B, AB, and BC according to the discrepancy signal of the comparator C;
It consists of three exclusive OR circuits that invert the data stored in one memory and two 2-port memories in a data write operation, thereby inverting the data at the same address read from three output ports. A multiport memory device characterized in that data values are always equal and that up to three pieces of data can be accessed during one access cycle.