JPH0477934B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention shares memory by providing multiple access ports and enabling multiple data reads and multiple data writes at the same time. The present invention relates to a multiport memory that increases the shared memory access speed of a multiprocessor system consisting of a plurality of processors.

(Prior Art) As the processing demands on computer systems have become more complex and sophisticated, expectations are increasing for parallel processing using multiprocessor systems that have multiple processors, which are the processing core of computer systems. . There is a method of using a shared memory as a means of transmitting information between processors in this multiprocessor system. One way to implement shared memory that is accessed by multiple processors is to connect the multiple processors and shared memory that make up the multiprocessor system via a bus, and to use dedicated hardware (arbiter) that arbitrates the right to use the bus. There is a bus coupling method to use.

(Problems with the prior art) In a shared memory using the conventional bus coupling method, an arbiter that arbitrates the right to use the bus determines one processor to access the shared memory. This solved the problem of shared memory contention among processors. That is, the arbiter arbitrates shared memory access rights, thereby sequentially processing shared memory access requests from a plurality of processors. Therefore, as the number of processors that make up a multiprocessor system increases, the frequency of shared memory access increases, and in the conventional method that processes shared memory accesses sequentially, shared memory accesses become a bottleneck, causing processors to The problem was that the effects of multiple parallel processing could not be fully utilized.

An object of the present invention is to improve shared memory access, which was processed sequentially in the prior art, by providing multiple access ports and making it possible to read multiple data and write multiple data at the same time. Multi-port and parallel processing
The purpose is to provide memory.

(Means for Solving the Problems) The multi-port memory of the present invention includes a plurality of input/output shared access ports, and the access ports are arranged in a grid having the same number of rows and columns as the number of access ports. is provided for each column, which receives as input the square of the number of memories and the outputs of the memories in the same number as the number of access ports arranged on one column, decodes data, and outputs it to the access ports. A decoder, the output of the memory arranged on an arbitrary column that is not targeted for data writing, and the write data sent to the access port allocated to the decoder. It consists of an encoder provided for each row that generates the same number of data to be written to the memory as the number of access ports arranged on the row, and the access cycle consists of a data read phase and a data write phase, and the data read phase An address is provided for each column, and an address is provided for each row in the data write phase, and the encoder writes the contents of any one of the memories as many as the number of access ports arranged on the column. Encoding is performed so as to set all data values by changing, and for the output of the same number of the memories as the number of the access ports arranged on the column input to the decoder,
When the contents of any one of said memories changes, the contents of any one of said memories equal to the number of said access ports on a column are changed by determining a particular data value due to the change. It is characterized by performing modification and data writing operations.

(Operation) In the multiport memory of the present invention, data is encoded with the same code as the number of access ports. The features of the multi-port memory of the present invention will be explained using an example of four access ports. FIG. 2 shows the configuration of a memory section that stores data. 16 memories are arranged in a grid of 4 rows and 4 columns. 200, 201, 202, 203 are the first
This is memory that constitutes a row. This memory may be a conventional random access memory. Therefore, it is also possible to use a 1 megabit random access memory to realize a multi-port memory with a large capacity of several megawords. 20
Memories 0, 210, 220, and 230 constitute the first column. The four memories arranged in one row store the same code. The four memories located above the columns store four codes of encoded data. Each column has a decoder that recovers data from the codes stored in the four memories belonging to the column. The four codes used when encoding data are fixed arbitrary three codes,
The remaining code must be able to vary to represent all possible values of the data. An example of encoding when the data width is 3 bits is a method in which the sum of four codes is divided by 8 and the remainder is used as data.

Multiport of the present invention using the above code
The memory data write operation will be explained. FIG. 3 shows the state of the write address in the memory before the write operation. 300, 301, 302, and 303 are the four memory rows used by access port 0.
300, 310, 320, and 330 are the four memories in the column used by access port 0.

In the write operation, access port 2 will be used to write "1". Access phase is 2
Consists of phases. In the first phase, the codes of the four memory write addresses belonging to the second column are read, and the encoder in the second row generates a code to be written in the second row from the write data and the read code in the second column. FIG. 4 shows the state when the write address of the memory is read in the first phase. 402,41
2,422,432 This is the code of the memory write address belonging to the second column. Since the sum of the read codes (0, 0, 0, 0) in the second column is 0, it is known that the data is "0". Therefore, the code written in the second line is "1". The second phase is the first
Write the write code generated in phase to the four memories in the second row. FIG. 5 shows the state of the memory write address after the second phase is completed. 520,
Codes 521, 522, and 523 have been rewritten from "0" to "1". In this data write operation, the codes of all memory write addresses belonging to the row corresponding to the access port are rewritten, so no matter which column is read, the data at the write address has changed to "1". In a write operation, in the first phase, code is read from the memory belonging to the column of the access port used for writing, and in the second phase, the code is written to the memory belonging to the row of the access port used for writing, but other Memory belonging to columns and rows is not used. Therefore, in the multiport memory of the present invention used in the example described, four rows assigned to four access ports can be used to write data to four different addresses.

A data write operation to multiple addresses will be explained using an example of data write using four access ports. Let the write addresses of access ports 0, 1, 2, and 3 be addresses a, b, c, and d, respectively. Furthermore, the write data is assumed to be "1", "2", "3", and "4". FIG. 6 shows the code at address a before the write operation. Since the write operation is performed using access port 0, 600, 610, 620, 63 in the first column
0 and 600, 601, 602, 603 in the first row are used. FIG. 7 shows the code at address b before the write operation. Since writing is performed using access port 1, 701, 711, 721, 73 in the second column
1 and 710, 711, 712, and 713 in the second row are used. FIG. 8 shows the state after code reading in the first phase. 1st row 800, 81
0,820,830 is the code of address a. The second column 801, 811, 821, 831 is the code of address b. Similarly, the third column 802, 812,
822 and 832 are addresses c, 4th column 803 and 81
3,823,833 is the code of address d. For each column, using the decoder assigned to the column,
Generate write code. FIG. 9 shows how the code is written in the second phase. 1st line 900,
901, 902, and 903 are codes written to address a. 2nd row 910, 911, 912, 91
3 is a code written to address b. Similarly, the third row 920, 921, 922, 923 is address c,
The fourth rows 930, 931, 932, and 933 are codes written to address d. FIG. 10 shows the code at address a after the write operation is completed. 1st row 100
From the sum of the codes (6, 2, 1, 0) of 0, 1010, 1020, 1030, the remainder when divided by 8 is 1, so it can be seen that the data is "1". 11th
The figure shows the code at address b after the write operation is completed. 1st row 1100, 1110, 1120, 11
From the sum of 30 codes (3, 4, 1, 2), the remainder when divided by 8 is 2, so we know that the data is "2". The same thing can be said about access ports 2 and 3.

As a result, if the access cycle of the Altiport memory of the present invention is made into two phases, a data read phase and a data write phase, if the total number of data to be accessed is less than or equal to the number of access ports, multiple data reads and multiple data can be written in one access cycle.

(Example) Examples of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the altiport memory of the present invention in which the number of access ports is four.

The memory sections for storing data are arranged in a grid of 4 rows and 4 columns. 11, 21, 31, 41 are the first
This is memory belonging to a column. If a dynamic memory refresh function is provided, it is possible to use 1 megabit dynamic memory, making it possible to realize a large-capacity Altiport memory.

A data read operation using access port 0 will be explained as an example. In the first phase of the access cycle (data read phase), the read address of address port 0 belongs to the first column of memory 1.
Sent to 1, 21, 31, 41. Memory 11 always receives the address of address port 0, but other memories 21, 31, and 41 receive addresses of other address ports in the second phase (data write phase). For this reason, selectors 27, 37,
47 to select the address of address port 0. 4 memories 11, 2 belonging to the first column
The outputs of 1, 31, and 41 are converted into storage data by the decoder 10 assigned to access port 0, and output to access port 0.

Next, a data write operation using access port 0 will be explained. Memory 11 belongs to the first column and also to the first row. 11,12,1
3 and 14 are memories belonging to the first row. In the first phase, as in the case of a read operation, write addresses are given to memories 11, 21, 31, and 41 in the first column, four memories 11, 21, 31, and 41 are read, and the addresses assigned to access port 0 are read. The encoder 15 uses the output and the write data of the access port 0 to input the memories 11, 12, 13,
14 is generated. In the second phase, the write data generated by the encoder 15 in the first phase is transferred to the memories 11, 12, 13 belonging to the first row.
Write to 14. For this reason, selectors 17, 18, 19
selects the write address of address port 0 and provides it to memories 12, 13, and 14. Memory 11 always receives the write address of address port 0. Since writing in the second phase rewrites all memories belonging to the first row, all the data stored in the four columns at the address targeted for writing is rewritten.

Finally, the demultiplexer 10 and encoder 15 will be explained.
To simplify the explanation, assume that the data bit width is 3 bits. FIG. 12 is a block diagram of an embodiment of the multiplexer 10. 1200, 1201, 1202
is a 3-bit adder. The outputs of the four memories on the column are respectively on lines 1210, 1211, 121
2, 1213, adders 1200, 1201
is added. Further, the addition result with overflow removed passes through 3-bit wide lines 1214 and 1215 and is added by an adder 1202. The addition result of the adder 1202 with overflow removed is a value obtained by dividing the addition results of the four memories by eight.

FIG. 13 is a block diagram of an embodiment of encoder 15. 1300 and 1301 are 3-bit adders,
1302 is a 3-bit subtraction yellow. Adder 13 adds the outputs of three memories out of the four memories on the column, excluding the memory belonging to the row where the encoder writes the code.
Add by 00,1301. The encoder calculates the difference between the write data and the results added by adders 1300 and 1301. Naturally, adder 1300 and 1
When added to the code used by 301, it becomes write data. Therefore, the encoder subtracts the addition results of adders 1300 and 1301 from the write data of the access port in subtracter 1302, and outputs the value with the undercarriage removed as a write code.

(Effects of the Invention) The multi-port memory of the present invention uses the square of the number of access ports arranged in a lattice pattern, and divides the access cycle into a read phase and a write phase. It is characterized in that the memory belonging to a particular column is used, and in the write phase, each access port similarly uses the memory belonging to a particular row. As a result, as long as the total number of data to be accessed is less than or equal to the number of access ports, it is possible to read any number of data and write any number of data in one access cycle.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the multiport memory of the present invention with four access ports. In the figure, 10, 20, 30, 40 are compound devices, 11, 12, 13, 14, 21, 22,
23, 24, 31, 32, 33, 34, 41, 4
2, 43, 44 are memory, 15, 25, 35, 4
5 is an encoder, 17, 18, 19, 27, 28, 2
9, 37, 38, 39, 47, 48, 49 are selectors. 2 to 11 are diagrams for explaining the operation of the present invention, FIG. 12 is a block diagram of an embodiment of a compounder, and FIG. 13 is a block diagram of an embodiment of an encoder.

Claims (1)

[Claims] 1. A memory having a plurality of input/output shared access ports and arranged in a grid having the same number of rows and columns as the number of access ports, the square of the number of the access ports, and a memory arranged on one column. A decoder provided for each column receives the same number of outputs from the memories as the number of access ports, decodes the data, and outputs the data to the access ports; Write to the same number of memories as the number of access ports arranged on an arbitrary row from the output of the memory that is not a write target and the write data sent to the access port assigned to the decoder. It consists of an encoder provided for each row that generates data, and the access cycle consists of a data read phase and a data write phase, in which an address is given for each column in the data read phase, and an address is given for each row in the data write phase, encoding such that the encoder sets all data values by changing the contents of any one of the memories as many as the number of access ports arranged in a column; Determining a specific data value based on the change when the contents of any one of the memories changes for the outputs of the same number of the memories as the number of the access ports arranged on the columns input to the decoder. A multi-port memory characterized in that the contents of any one of the memories of the same number as the number of access ports on a column are changed to perform a data write operation.