JPH0548027A - Static ram - Google Patents

Abstract

(57) [Summary] [Object] To provide a static RAM in which an increase in power supply current at a low power supply voltage is prevented. [Structure] A voltage detection circuit is incorporated in a static RAM having a level conversion circuit for converting from an ECL level to a CMOS level, and a word line is forcibly deselected when the power supply voltage is below a predetermined voltage in absolute value. A control signal that causes the control signal to be generated. [Effect] Since the word line is brought into a non-selected state when the level conversion circuit cannot operate normally, it is possible to prevent such an increase in power supply current at a low voltage.

Description

Detailed Description of the Invention

[0001]

This invention relates to a static type RA
Regarding M (random access memory), for example, EC
The present invention relates to a technique effectively used by having an input / output interface compatible with L (emitter coupled logic).

[0002]

2. Description of the Related Art Bipolar transistor and CMOS
There is a high-speed, large-capacity static RAM that makes full use of logic gates, drivers, and sense amplifiers that combine (complementary MOS). Regarding such a static RAM, there is, for example, “Nikkei Electronics” pages 199 to 209 dated March 10, 1986.

[0003]

Of the above static RAMs, the ones compatible with ECL are ECLs.
A level conversion circuit for converting an input signal having a small amplitude such as a level into a large signal level such as a CMOS level is used. This level conversion circuit requires a relatively large operating voltage in order to amplify the signal level as described above. Then, at a voltage lower than the operation lower limit voltage, the signal level is set to an intermediate indefinite level because the transistors and MOSFETs do not operate sufficiently. On the other hand, in the CMOS circuit, the operation lower limit voltage is small, and a plurality of word lines are set to a high level corresponding to an indefinite level, and a direct current flows through the data line load and the memory cell. Although the current flowing in one memory cell is small, a DC current flows in many memory cells connected to a plurality of word lines, so that R
The power supply current in the entire AM increases. For this reason, in a memory device in which the RAM is mounted, an excessive current may flow when the power is turned on, and the overcurrent protection circuit may operate, making it impossible to power on the system. Therefore, when using such a memory device, it is necessary to take measures such as stopping the operation of the overcurrent protection circuit when the memory device is powered on. An object of the present invention is to provide a static RAM that prevents an increase in power supply current at low power supply voltage. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, from the ECL level to the CMOS
A voltage detection circuit is incorporated in a static RAM having a level conversion circuit for converting to a level, and a control signal for forcibly bringing a word line to a non-selected level when the power supply voltage is below a predetermined voltage in absolute value is formed. ..

[0005]

According to the above-mentioned means, since the word line is brought into the non-selected state when the level conversion circuit cannot operate normally, it is possible to prevent such an increase in the power supply current at a low voltage.

[0006]

FIG. 4 is a block diagram showing an embodiment of a static RAM to which the present invention is applied. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known Bi-CMOS manufacturing technique. The X-system address signals AX0 to AXi composed of a plurality of bits are input to the X-system address buffer XB. The address signal taken into the address buffer XB is decoded by the X-system decoder circuit XD, and a word line selection signal is formed here. The word line selection signal is transmitted to the word driver WD, although not particularly limited. By providing such a word driver WD, a large number of memory cells are coupled to each other so that a word line having a relatively large load capacitance can be switched between high speed and low speed. The X-system address signals AX0 to AXi composed of a plurality of bits are at the ECL level. The address buffer XB uses CMOS
The level is converted and supplied to the decoder circuit XD.

Y-system address signal A consisting of a plurality of bits
Y0 to AYj are input to the Y system address buffer YB. The address signal taken into the address buffer YB is decoded by the Y-system decoder circuit YD, and a selection signal for the data line, in other words, a selection signal for the column switch is formed here. The selection signal of the column switch is transmitted to the column switch (or Y selector) YS to connect the selected data line to the common data line. The Y-system address signal AX0 composed of the plurality of bits
~ AXi is the ECL level as above. The address buffer YB converts it into a CMOS level and supplies it to the decoder circuit XD.

The memory array MARY is formed by arranging static type memory cells, which will be described later, in a matrix. That is, in the figure, memory cells are arranged in a grid pattern at the intersections of the complementary data lines extending in the vertical direction and the word lines extending in the horizontal direction. It should be understood that the memory array MARY also includes a data line load circuit as described later.

The read signal of the common data line is supplied to the input of the sense amplifier SA, where it is amplified with high stability and at high speed. The amplified output signal of the sense amplifier SA is
The data is output from the data output terminal DO through the data output circuit OB. The read signal output from the data output terminal DO is an ECL level signal. The ECL level write data supplied from the data input terminal DI is supplied to the input of the data input circuit IB. The write signal fetched through this data input circuit IB is
Write amplifier W converted to CMOS level
It is transmitted to A's input. The write amplifier WA outputs a write signal to the common data line. The write signal transmitted to the common data line is transmitted to the selected complementary data line through the column switch YS, and the word line is taken into the selected memory cell.

The timing control circuit TG receives the chip enable signal CEB and the write enable signal WEB, and activates the internal signal CE for activating the decoder circuits XD and YD, the operation signal SAC of the sense amplifier SA, and the write amplifier WA. The operation signal WE that causes the data line output circuit OB and the operation signal OE that activates the data line output circuit OB are formed. The static RAM of this embodiment has the EC
L compatible.

FIG. 3 shows a concrete circuit diagram of one embodiment of the memory array portion of the static RAM and its peripheral circuits according to the present invention. Each circuit element shown in FIG. 1 is made of single crystal silicon by Bi-CMOS technology in which a bipolar transistor and a CMOS circuit are combined.
It is formed on each semiconductor substrate. In the figure, the P-channel MOSFET is distinguished from the N-channel MOSFET by adding an arrow to its channel portion (back gate portion). The input / output interface of the static RAM of this embodiment is made compatible with the ECL circuit. Therefore,
A negative power supply voltage VEE is used with respect to the ground potential of the circuit.

In memory array MARY, two memory cells connected to complementary data lines D0 and D0B are shown as a representative. Each of the memory cells MC has the same configuration as each other, and as its one specific circuit is representatively shown, the gate and the drain are cross-connected to each other and the source is coupled to the negative voltage of the circuit. Channel type storage MOSFETs Q1 and Q2 and the above-mentioned MOSFE
High resistance R1, made of a poly (polycrystalline) silicon layer, provided between the drains of TQ1 and Q2 and the ground potential of the circuit
R2 and. N-channel type transmission gate MOSFETs Q3 and Q4 are provided between the common connection point of the MOSFETs Q1 and Q2 and the complementary data lines D0 and D0B. Transmission gates M of memory cells arranged in the same row
The gates of the OSFETs Q3, Q4, etc. are commonly connected to corresponding corresponding word lines W0, Wn, etc., respectively, and the input / output terminals of the memory cells arranged in the same column are exemplarily shown as the above representative. Connected to a pair of complementary data lines (also referred to as complementary bit lines or complementary digit lines) D0 and D0B.

In the memory cell MC, the MOSFET Q
1, Q2 and resistors R1, R2 form a kind of flip-flop circuit, but the operating point in the information holding state is quite different from that of the flip-flop circuit in the ordinary sense. That is, in order to reduce the power consumption of the memory cell MC, the resistance R1 of the memory cell MC is
MOSFETQ when ETQ1 is turned off
It has a remarkably high resistance value such that the gate voltage of 2 can be maintained at a voltage slightly higher than its threshold voltage. Similarly, the resistance R2 is also set to a high resistance value. In other words, the resistors R1 and R2 are made high enough to compensate the drain leak currents of the MOSFETs Q1 and Q2. The resistors R1 and R2 have a current supply capability that prevents the information charges accumulated in the gate capacitance (not shown) of the MOSFET Q2 from being discharged.

According to this embodiment, the RAM is CMOS-
Although manufactured by the IC technology, the memory cell MC is composed of the N-channel MOSFET and the polysilicon resistance element as described above. Static type R
As the AM memory cell, a P-channel MOSFET may be used instead of the polysilicon resistance element. The size of the memory cell can be reduced as compared with the case where a P-channel MOSFET is used. That is, when a polysilicon resistor is used, it can be formed on the gate electrode of the drive MOSFET Q1 or Q2, and the size of itself can be reduced. And P channel MOS
As when using the FET, the drive MOSFET Q1,
Since there is no need to keep a relatively large distance from Q2, there is no useless blank portion.

In the figure, although not particularly limited, between the complementary data lines D0 and D0B and the ground potential of the circuit,
P-channel type load MOSFETs Q9 and Q10, which act as resistance elements when the power supply voltage VEE is constantly supplied to their gates, are provided. These load MOSFETs Q9 and Q10 are formed to have a relatively small size so that they have a small conductance. These load MOSFETs Q9, Q1
0 is the load MO of P-channel type in parallel form.
SFETs Q11 and Q12 are provided. These loads M
The OSFETs Q11 and Q12 are formed to have a relatively large size so that they have a relatively large conductance. The MOSFETs Q9 to Q12
Conductance and memory cell M in the ON state
The ratio of the combined conductance of the transmission gate MOSFET and the storage MOSFET of C is such that in the read operation of the memory cell MC, the complementary data lines D0 and D0B are
The value is selected so as to have a desired potential difference according to the stored information. An internal write signal WE, which is set to a high level such as the ground potential of the circuit during the write operation, is supplied to the gates of the load MOSFETs Q11 and Q12.
As a result, during the write operation, the load MOSFET
TQ11 and Q12 are turned off. Therefore, the load means of the complementary data line in the write operation is only the MOSFETs Q9 and Q10 having the small conductance.

In this embodiment, although not particularly limited, in order to make the signal amplitude of the read signal of the memory cell read through the column switch almost constant regardless of the address of the memory cell, the load MOSFET Q as described above is used.
9 to Q12 are not on the far end side of the complementary data lines D0 and D0B, in other words, on the side opposite to the end of the data line connected to the column switch side, but near the complementary data line and the column switch. Is provided. More specifically, the load MOSFETs Q9 to Q12 are arranged between the column switch and the memory cell arranged closest to the column switch.

In the figure, the word line W0 is selected by the X decoder circuit XD and the word driver WD, but in the figure, in order to prevent the drawing from being complicated, the AND (AND) gate circuit G1 is used for X. It also serves as a decoder XD and a word driver WD. This also applies to the word line Wn shown as another representative. The X decoder circuit XD is composed of AND gate circuits G1 and G2 which are similar to each other. An address buffer XB, which receives an X-system external address signal AX (AX0 to AXi) consisting of a plurality of bits supplied from the outside, is applied to the input terminals of these AND gate circuits G1, G2, etc.
The internal complementary address signals formed by are applied in a predetermined combination. Actually, the X decoder circuit XD is configured by dividing it by providing a predecoder or the like, but in this embodiment, it is functionally shown by one AND gate circuit.

In this embodiment, a low voltage detection circuit LVD for determining the potential of the power supply voltage VEE is provided. When the low voltage detection circuit LVD detects that the power supply voltage VEE is a low voltage equal to or lower than the lower limit voltage in the level conversion circuit from ECL to CMOS, the low voltage detection circuit LVD forms a control signal that substantially invalidates the operation of the decoder XD. .. That is, the low voltage detection circuit LVD forms a control signal such as logic 0 (low level) when the power supply voltage VEE is the predetermined low voltage as described above, and is independent of the level-converted address signal at this time. Keep all word lines at non-selected level.
As a result, R in the low voltage region such as when the power is turned on starts.
The power supply current flowing through the AM is prevented from becoming abnormally large.

Although not particularly limited, a P-channel MOSFET Q5 is provided between the complementary data line D0 and the read common complementary data line RCD in the memory array.
A corresponding column switch is provided. Other data line D
A column switch composed of a P-channel MOSFET Q6 is also provided between 0B and the read common complementary data line RCDB. A column switch consisting of an N-channel MOSFET Q7 is provided between the complementary data line D0 and the write common complementary data line WCD in the memory array. A column switch composed of an N-channel MOSFET Q8 is also provided between the other data line D0B and the write common complementary data line WCDB. A column selection signal Y0 is supplied to the gates of the N-channel MOSFETs Q7 and Q8, and a column selection signal Y0 inverted by the inverter circuit N1 is supplied to the gates of the P-channel MOSFETs Q5 and Q6. As a result, when the column selection signal Y0 is set to the high selection level, the N-channel MOS
FET Q7, Q8 and P-channel MOSFET Q5
Q6 is turned on. The column selection signal Y0 is
X composed of a circuit similar to the X decoder circuit XD
It is formed by a decoding circuit YD (not shown).

In the read operation, the voltage drop caused by the memory current flowing through the data line load resistance or the like with respect to the ground potential of the circuit is output as a read signal. Therefore, as described above, the P-channel MOSFET
Is used as a column switch, the read signal of the memory cell on the data line can be directly transmitted to the common complementary data lines CD and CDB side without causing level loss due to the threshold voltage of the MOSFET. In the write operation, the complementary data line D
One of 0 and D0B is set to a low level such as the ground potential of the circuit, and the memory MO of the memory cell connected thereto is
By turning off the SFET, the other memory MO
Switch the SFET on. Therefore, by using the N-channel MOSFET as a column switch as described above, the low level of the ground potential of the circuit can be transmitted to the data line as it is.

In this embodiment, the common complementary data lines RCD and RCD for reading are load MO of P-channel type for supplying power to the common complementary data line for reading.
SFETs Q13 and Q14 are provided. These loads M
The power supply voltage VE is applied to the gates of the OSFETs Q13 and Q14.
When a low level such as E is constantly supplied, it functions as a resistance element. This load MOSFET Q1
The resistance values of Q3 and Q14 are set so as to have sufficiently large resistance values with respect to the load MOSFETs Q11 and Q12 provided on the data lines D0 and D0B.

Common complementary data line RC for reading
D and RCDB are coupled to the input terminal of the sense amplifier SA. The output signal of the sense amplifier SA is transmitted to the input terminal of the data output circuit OB that outputs the output signal from the external terminal. Common complementary data lines WCD, W for writing
The CDB is coupled to the output terminal of the write amplifier WA. The output signal of the data input circuit IB which receives the write data supplied from the external terminal is supplied to the input terminal of the write amplifier WA. By thus separating the common data line for reading and for writing, the load condition of the common complementary data line can be optimally set for the operations of the sense amplifier SA and the write amplifier WA. A P-channel MOSFET Q13 for equalization is provided between the common complementary data lines for reading RCD and RCDB for high-speed reading. The equalizing pulse E is applied to the gate of the MOSFET Q13.
Q is supplied. The equalizing pulse EQ is X system or Y
It is generated when the address signal of any one bit of the system changes, and turns on the MOSFET Q13 to short-circuit the common complementary data lines RCD and RCDB.

The static RAM of the above embodiment
The read operation from the memory cell is as follows. The storage MOSFET in which the memory cell is turned on can be regarded as a constant current source. Therefore, the read low level from the memory cell is equal to the load MOSFETs Q11 and Q12.
The memory cell MCn closest to the
A voltage drop occurs due to the memory current Io flowing through the resistance component RL of the FETs Q11 and Q12. The memory current Io and the resistance RY of the column switch provided in parallel with the resistance RL and the common data line load MOSFET
The resistance component RP of Q13 and Q14 is also branched and flows, but the series combined resistance of these resistors RY and RP is
Since it is sufficiently larger than L, it can be substantially ignored.

On the other hand, in the memory cell MC0 arranged farthest from the load MOSFET,
The memory current Io is applied to the resistance RL and the resistance RD of the data line.
Will flow. Therefore, at the input / output node of the memory cell, a large signal amplitude is set by the resistor RL + RD, but on the column switch side, there is only a voltage drop caused by the memory current Io flowing through the resistor RL as described above. Therefore, the common complementary data line RD for reading
The read signal of the memory cell transmitted to the input of the sense amplifier SA through C and RCDB can be made almost constant regardless of the X-system address.

FIG. 1 shows a circuit diagram of an embodiment of the low voltage detection circuit LVD. The circuit symbols attached to the respective circuit elements in the figure partially overlap with those in FIG.
It should be understood that each has a separate circuit function. This also applies to the description of FIG. 2 below. Between the ground potential of the circuit and the power supply voltage VEE, diode-shaped transistors T1 and T2 and a resistor R1 are provided in series. A resistor R2 is provided between the base of the transistor T2 and the power supply voltage VEE.
A P-channel MOSFET Q1 and an N-channel MOSFET are provided between the ground potential of the circuit and the power supply voltage VEE.
Q2 is provided in series. The P-channel type MOSF
The gate of ETQ1 is supplied with the potential of the emitter of the transistor T2. N-channel type MOSFE
The potential of the base of the transistor T2 is supplied to the gate of TQ2.

The commonly connected drain outputs of the MOSFETs Q1 and Q2 are amplified by the CMOS inverter circuit N1 and the input and output are cross-connected.
It is taken in by the latch circuit composed of the OS inverter circuits N2 and N3. The feedback CMOS inverter circuit N3 has a smaller output drive capability than the input inverter circuit N1 of the latch circuit, and the input signal of the latch circuit is changed according to the output signal of the input inverter circuit N1. The latch output signal output from the inverter circuit N2 is output through the output inverter circuit N4, and is input as a gate control signal to one input of the NAND gate circuit G forming the X decoder XD. The output signal of the NAND gate circuit G performs the selecting operation of the word line to which the memory cell MC is connected through the word driver DW.

The operation of the low voltage detection circuit LVD of this embodiment is as follows. Power supply voltage VEE is transistor T
When the voltage between the base and emitter of 1 and T2 is 2VBE or less, these transistors T1 and T2 are in the off state. Therefore, the power supply voltage VEE is supplied to the gate of the P-channel MOSFET Q1 through the resistor R1, and when the power supply voltage VEE becomes larger than the threshold voltage of the MOSFET Q1 in absolute value, the P-channel MOSFET Q1.
Turns on. In addition, N-channel MOSFET
Since the power supply voltage VEE is supplied to the gate of Q2 through the resistor R2, it is turned off. Therefore, in the low voltage region as described above, the P-channel MOSFET Q1
A high level such as the ground potential of the circuit is output according to the ON state of the and is taken into the latch circuit. The output inverter circuit N4 of the latch circuit outputs a low-level control signal. However, the power supply voltage VEE needs to be equal to or higher than the operating voltage of the CMOS inverter circuits N1 to N4.

A gate circuit G constituting a decoder circuit is provided by the low level of the output signal of the low voltage detection circuit LVD.
Forms a high-level output signal regardless of the level-converted address signal, so that the word driver WD sets the word line to a low-level non-selection level. This can prevent a direct current from flowing through the load of the complementary data line and the memory cell in the low voltage region as described above.

When the transistors T1 and T2 are turned on by the increase of the power supply voltage VEE, the P-channel type M
The constant voltage of 2VBE is supplied to the gate and the source of the OSFET Q1. On the other hand, N-channel type MOS
VEE-VBE is provided between the gate and source of FET Q2.
As described above, a voltage proportional to the power supply voltage VEE is applied, and a level output signal is formed according to the conductance ratio. At this time, the size of the N-channel MOSFET Q2 is made larger than that of the P-channel MOSFET Q1 so that it has a large conductance. Therefore, when the output signals of the MOSFETs Q1 and Q2 become lower than the logic threshold voltage of the inverter circuit N1 as the power supply voltage VEE increases in absolute value, the output signal of the inverter circuit N1 is inverted and set to the high level. As a result, the control signal also becomes high level, the NAND gate circuit G forms a decoded output according to the level-converted address signal, and only one word line is selected from the plurality of word lines. Thus, the detection voltage of the low voltage detection circuit LVD of this embodiment is such that the power supply voltage VEE is 2VBE or more in absolute value,
It is set by a combination of the conductance ratio of the MOSFETs Q1 and Q2 and the logic threshold voltage of the inverter circuit N1.

FIG. 2 shows a circuit diagram of an embodiment of the level conversion circuit. The input part of the level conversion circuit is
Basically, it is composed of a unit ECL circuit. The output signal of the address buffer is in a wired OR configuration that constitutes a predecoder circuit, and a transistor T1 receiving the output signal ECL and a transistor T2 receiving the reference voltage VBB are in a differential form, and a constant current source Io is used as a common emitter.
Is provided and its collector has a load resistance R
1, R2 are provided. The collector outputs of the differential transistors T1 and T2 are input to the next level amplifier circuit section through the emitter follower output circuit including the transistors T3 and T4 and the constant current source Io provided at the emitter.

The complementary output signal formed by the input section is supplied to the gates of P-channel MOSFETs Q1 and Q2. These P-channel MOSFETs Q1 and Q
The source of 2 is connected to the ground potential of the circuit and its drain is an N-channel MOSFET in the form of a current mirror.
Q3 and Q4 are provided. P-channel MOSFET Q1 whose gates are supplied with the complementary input signals.
And Q2 will carry complementary drain currents according to their complementary input signal levels. For example, one MOSF
When the current flowing through ETQ1 is relatively increased, the current flowing through the other MOSFET Q2 is relatively decreased. In this case, a large current also flows through the current mirror type N-channel MOSFETs Q3 and Q4 in accordance with the drain current formed by the MOSFET Q1.
Therefore, the P-channel MOSFET Q2 and the N-channel MOSFET Q4 are operated in a complementary manner, and a low level signal such as a substantially negative power supply voltage VEE corresponding to the conductance ratio is formed from the commonly connected drains. On the contrary, when the current flowing through the MOSFET Q2 is relatively increased and the current flowing through the MOSFET Q1 is relatively decreased, a high level such as the ground potential of the circuit is formed.

In this embodiment, in order to increase the output current, in other words, to rapidly drive a capacitive load having a relatively large capacitance value, the output signal of the level conversion circuit is , The collector is supplied to the base of the transistor T1 connected to the ground potential point of the circuit. The transistor T1 constitutes a totem pole type push-pull output circuit together with the transistor T2 connected in cascade. Although there is no particular limitation between the collector and the base of the output transistor T2 on the low level side, an N-channel MOSFE for receiving the output signal on the preceding stage side is provided.
TQ5 is provided. An N-channel MOSFET Q6 for pulling out a low level for receiving an output signal is provided between the base and the emitter of the transistor T2.
Instead of this configuration, the MOSFET Q5 is
It may have the same structure as TQ1 to Q4 and receive the output signal of the level amplifying circuit whose input signal is inverted.

In such a level conversion circuit, in the transistor circuit of the input stage and the transistor circuit of the output stage, the transistors forming a constant current with the differential transistors T1 and T2 and the two output transistors are cascade-connected, so that at a minimum. It requires a large voltage of 2 VBE or more.
On the other hand, in the CMOS circuit, P-channel type MOSF
It operates at a relatively low voltage such as about 1 V corresponding to the sum of the threshold voltages of ET and N-channel MOSFETs. Therefore, in the low voltage region where the power supply voltage VEE is about 1 V, the output level of the ECL circuit or the level conversion circuit becomes indefinite, whereas the CMOS circuit can operate, and the CMOS circuit forming the decoder has an indefinite level. The input signal is regarded as either high level or low level, and a plurality of word lines are selected. However, in this embodiment, the decoder circuit does not select the word line in response to the control signal generated by the low voltage detection circuit LVD as described above.

The effects obtained from the above embodiment are as follows. That is, (1) a voltage detection circuit is incorporated in a static RAM equipped with a level conversion circuit for converting from an ECL level to a CMOS level, and a word line is forcibly de-energized when the power supply voltage is below an absolute value of a predetermined voltage. By forming the control signal for causing the selection level, the word line is deselected when the level conversion circuit does not operate normally.
The effect that the increase of the power supply current at such a low voltage can be prevented is obtained. (2) According to the above (1), there is an effect that the overcurrent protection circuit of the system power supply such as the memory device and the microcomputer including the memory device can be simplified.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG.
In FIG. 1, the circuit for detecting a low voltage uses a constant voltage between the base and emitter of a bipolar transistor or a constant voltage between the gate and source of a MOSFET, or a PN junction diode, zener diode or Jottky diode. Various embodiments such as a constant voltage such as or a combination of these can be adopted. The control signal generated by the low voltage detection circuit may be set to logic 1 so that the gate is closed at a low voltage when the gate circuit that forms the selection signal of the word line is formed of a logical sum gate. Alternatively, a logic function may be added to the word driver so that the word line is forcibly made unselected by the control signal when the voltage is low.

The circuit for converting from the ECL level to the CMOS level can adopt various embodiments. In FIG. 3, the common complementary data line may be common for reading and writing. The load of the complementary data line may be provided on the opposite side of the column switch. An additional circuit such as a write recovery circuit may be provided on the common data line or the common complementary data line in order to perform high-speed reading after the write operation. In FIG. 4, the memory array may be divided into a plurality of memory mats and the substantial lengths of the word lines and the data lines may be shortened to speed up memory access. The data may be written / read in units of a plurality of bits.

[0037]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, from the ECL level to the CMOS
A voltage detection circuit is incorporated in a static RAM having a level conversion circuit for converting to a level, and a control signal for forcibly bringing a word line to a non-selected level when the power supply voltage is below a predetermined voltage in absolute value is formed. As a result, the word line is brought into the non-selected state when the level conversion circuit cannot operate normally, so that it is possible to prevent such an increase in the power supply current at a low voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a low voltage detection circuit used in a static RAM according to the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a level conversion circuit used in the static RAM according to the present invention.

FIG. 3 is a specific circuit diagram showing an embodiment of a memory array section of a static RAM and a peripheral circuit thereof according to the present invention.

FIG. 4 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.

[Explanation of symbols]

LVD ... Low voltage detection circuit, XB ... X system address buffer, YB ... Y system address buffer, XD ... X system decoder circuit, YD ... Y system decoder circuit, WD ... Word driver, YS ... Column switch (Y selector), MARY …
Memory array, SA ... Sense amplifier, OB ... Data output circuit, IB ... Data input circuit, WA ... Write amplifier,
TG ... Timing control circuit, MC ... Memory cell, W0,
Wn ... Word line, D0, D0B ... Complementary data line, RC
D, RCDB ... Common complementary data line for reading, WCD,
WCDB ... Common complementary data lines for writing, Q1 to Q13
... MOSFET, T1 to T6 ... transistors.

Claims (3)

[Claims] 1. An address selection circuit for converting an ECL level input signal into a CMOS level to perform a memory selection operation, and forcibly bringing a word line to a non-selection level when a power supply voltage is an absolute value or less than a predetermined voltage. A static RAM comprising a voltage detection circuit for generating a control signal for controlling the static RAM. 2. The control signal is supplied to a logic gate circuit forming an address decoding circuit forming an input signal of a word driver, and sets the word line to a non-selection level regardless of the address signal. The static RAM according to claim 1. 3. The voltage detection circuit sets the ECL level to C
The static RAM according to claim 1 or 2, wherein a voltage lower than a lower limit operating voltage of a level conversion circuit for converting to a MOS level is detected.