JPH0548409A - Digital input circuit - Google Patents

Abstract

PURPOSE:To count the number of input signals by means of fuzzy inference based on a pulse width of the input signal and a pulse ratio without need for the selection of a filter clock frequency even when noise is included in the input signal and the input signal includes chattering caused when the signal width of the input signal is switched by a contact or the like. CONSTITUTION:A filter circuit 20 filters input signals a1-a3. Even when the input signals a1-a3 have noise or chattering or the speed changes from a high to a low speed, a fuzzy inference section 26 eliminates the noise and chattering based on a pulse width and a pulse ratio with respect to the input signal, a 1st counter 32 counts the input signal a1 at a high/low speed and the input signals a2, a3 at a low speed are outputted to an output circuit 36 as it is.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a digital input circuit for filtering an input signal.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional digital input circuit, and FIG. 5 is a timing chart for explaining the operation of the digital input circuit of FIG. This digital input circuit 2
Is composed of a filter circuit 4 and a clock control circuit 6. The filter circuit 4 is connected between the input terminal 8 for the input signal in and the output terminal 10 for the output signal out, and has a shift register 4-1, a noise removal circuit 4-2, AND gates G1, G5 and RS. It consists of a flip-flop FF5 of the type.

The shift register 4-1 has a four-stage configuration of D-type flip-flops FF1 to FF4, which are cascade-connected in a serial input / parallel output type, and output terminals Q of the respective flip-flops FF1 to FF4.
Is connected to each input part of the AND gate G1 and each output terminal Q'is connected to each input part of the AND gate G5. Noise removal circuit 8
Is composed of a NAND gate G2, an AND gate G3, and an inverter G4, and each input portion of the NAND gate G2 has an output terminal Q'of a flip-flop FF2.
And an output terminal Q of the flip-flop FF3 are connected to each other, and an output section of the NAND gate G2 and an output section of the inverter G4 are connected to each input section of the AND gate G3, The input part of the inverter G4 is connected to the input terminal 8 of the input signal in.

In such a digital input circuit 2, the filter clock CK having the frequency shown in FIG. 4 is applied to the clock terminals CK of the flip-flops FF1 to FF4. Then, a normal input signal in having a signal length that is, for example, four times or more the cycle of the filter clock CK is input to the input terminal D of the flip-flop FF1.
Is input, the outputs FF1 to FF4 which rise to a high level in response to the respective rising inputs of the filter clock CK are output from the output terminals Q of the respective flip-flops FF1 to FF4 which are connected in cascade.

The NAND gate G2 outputs a logical product G2 of the low level output from the output terminal Q'of the flip-flop FF2 and the low level output from the output terminal Q of the flip-flop FF3. In this output state, since the normal high level input signal in is input to the input terminal 8, the inverter G
4 outputs are low level. Therefore, the output of the AND gate G3, which is the logical product G3 of the inverter G4 and the NAND gate G2, remains at the low level,
The flip-flop FF1 is not reset by the logical product G3 of the AND gate G3.
In response to the rising of the output terminal Q of the output terminal 4 of the AND gate G1 to the set terminal S of the RS flip-flop FF5.
AND G1 for counting the normal input signal in
Is output, which causes the flip-flop FF
5 from the output terminal Q to the output terminal 10 of the normal input signal i
The count output signal out corresponding to n rises and is output. On the other hand, each flip-flop FF1 to FF
When the output terminal Q'of the output terminal 4 of the fourth flip-flop sequentially falls and the output terminal Q'of the last flip-flop FF4 falls, the AND gate G5 outputs the RS flip-flop F.
The logical product G5 is output to the reset terminal R of F5, whereby the flip-flop FF5 is reset, and as a result, the output signal out falls, and as a result,
The input signal in is output as a normal signal.

On the other hand, when the input signal in having a signal length less than or equal to 4 times the cycle of the filter clock CK is input to the input terminal D of the flip-flop FF1, each flip-flop FF1 is processed in the same manner as described above. ~ FF
Although the output Q of each of the four rises, the AND timing G1 of the AND gate G1 remains at the low level due to the deviation of the rising timing, whereby the flip-flop FF5 is not set, and therefore the output from the output terminal 10 is output. The signal out is no longer output, and the input signal in becomes noise and is removed.

Next, a plurality of synchronization noises synchronized with the cycle of the filter clock CK may be continuously input to the input terminal 8 as the input signal in. If such synchronization noise is used as the output signal out, an erroneous count occurs. Therefore, in order to prevent this erroneous count, when the synchronization noise is input to the input terminal D of the flip-flop FF1, the filter clock CK for each is output. The flip-flops FF1 to FF4 rise to a high level from their output terminals Q at the rising edge of
And the output terminal Q ′ output of the flip-flop FF2 and the output terminal Q output of the flip-flop FF3 are both at the low level, the NAND gate G2 outputs a high-level NAND output G2. .. Then, at this time, since the input signal in is at the low level, the output of the inverter G4 is at the high level. Therefore, from the high level NAND operation output G2 from the NAND gate G2 and the high level output of the inverter 8c,
The logical product output G3 of the ND gate G3 becomes high level and the flip-flop FF1 is reset. As a result, the logical product G of high level is output from the AND gate G1.
1 is not output, and therefore the flip-flop FF5
The output signal out, which is a count output, is not output from the output terminal Q to the output terminal 10, and as a result, the input signal in that causes an erroneous count such as synchronization noise is not counted.

Next, the clock control circuit 6 will be described. The clock control circuit 6 includes a reference clock generation circuit 6-1, frequency dividers 6-2 and 6-3, a clock setting switch 6-4, and a clock selection circuit. It is composed of circuits 6-5. The reference clock generation circuit 6-1 is for generating a reference clock, and the frequency divider 6-2 is for frequency-dividing the reference clock from the reference clock generation circuit 6-1. -3 further divides the divided clock divided by the divider 6-2. Therefore, the output of the frequency divider 6-2 is a clock having a longer period than the reference clock, that is, a higher speed clock, and the output of the frequency divider 6-3 is a lower speed clock having a longer period than the clock.

The clock setting switch 6-4 is a filter clock C for the flip-flops FF1 to FF4.
The clock selection circuit 6-5 is a switch for setting the frequency of K, and the clock selection circuit 6-5 corresponds to the setting by the clock setting switch 6-4. One of the low-speed clocks from 3 is selected and each flip-flop FF1 to FF4 receives the filter clock CK.
Is output as.

In such a clock control circuit 6, within the signal width of the input signal in, the filter clock CK
It is necessary that at least 4 exist. Therefore, when the signal width of the input signal in is short, the frequency divider 6-2
It is necessary to select a filter clock CK having a high frequency from the output side and a filter clock CK having a low frequency from the output side of the frequency divider 6-3 when the signal width of the input signal is long. The frequency of the filter clock CK can be selected by operating the clock setting switch 6-4.

[0011]

However, if the clock setting switch 6-4 is operated to select the frequency of the filter clock CK as described above, an erroneous operation may occur. It may not be possible or noise may not be removed.

Therefore, in the present invention, it is not necessary to select the frequency of the filter clock, and even if the input signal contains noise, the signal width of the input signal is switched by a contact or the like. Even if the chattering is included, it is an object of the present invention to make it possible to accurately count the number of input signals by fuzzy inference based on the pulse width and pulse ratio of the input signals.

[0013]

In order to achieve such an object, the digital input circuit of the present invention has a filter means, a measuring means, a fuzzy inference means, and a counter means, and the filter means is an input. A signal is input to a plurality of flip-flops having a cascade connection structure, the signals are sequentially inverted in response to a filter clock in the flip-flops, and the output of each flip-flop is ANDed to obtain an output signal. Yes, the measuring means measures the pulse width and the pulse ratio of the input signal (the ratio of the pulse width of the previous input signal and the pulse width of the current input signal) from the output signal from the filter means. The inference means is to perform a fuzzy inference as to whether the input signal is noise-like or normal signal-like based on the both measured values. Data unit is configured to measure the predetermined sampling time, within the sampling period,
It is characterized in that the number of pulses of a normal signal from the fuzzy inference means is counted and the counted value is output as a signal.

[0014]

Even if the input signal includes noise but is output from the filter circuit, the fuzzy inference means
The noise in the input signal will be removed by fuzzy inference, and the remaining normal signal will be counted by the counter means. Also, when the input signal contains chattering, the chattering causes the normal signal to be detected from the filter circuit. If it is output with, the fuzzy inference means outputs only a normal signal and eliminates chattering.

[0015]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of a digital input circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation.

In FIG. 1, 20 is a filter circuit and 22
Is a pulse width measurement circuit, 24 is a pulse ratio measurement circuit, 26 is a fuzzy inference unit, 28 and 30 are output conversion circuits, and 32 and 3
4 is the first and second counters respectively, 36 is the output circuit, 3
Reference numeral 8 is an input terminal and 40 is an output terminal. Further, FF6 is an RS type flip-flop, G6 is an AND gate,
G7 is an OR gate, and G8 is a tristate buffer.

The filter circuit 20 has the same circuit configuration as that of the filter circuit 4 of FIG. 4, and includes a shift register 4-1, a noise removing circuit 4-2, an AND gate G1, and an AND gate G1.
G5 and RS type flip-flop FF5, and they are configured with the same connection as in FIG.
In operation, the input signal a is input to four cascaded D-type flip-flops, and the flip-flops of the flip-flops are sequentially inverted and shifted in response to the filter clock CK1. It operates so as to obtain an output signal b by ANDing the outputs. Of the input signals a from the input terminal 38, those that exceed the cycle of four times the filter clock CK1 are output as the output signal b. , And the input signal a having a period equal to or shorter than that period is filtered so as not to be output. In this example, the high-speed to medium-speed input signal a1 including noise is also changed to the low-speed input signal a2 including chattering.
Also, since the low-speed input signal a3 having neither noise nor chattering has a cycle of four times the filter clock CK1 or more, these are output from the filter circuit 20.

The pulse width measuring circuit 22 is the filter circuit 2
The pulse width of the output signal b of 0 is measured, and the measured value is converted into a plurality of bits corresponding to the fuzzy inference unit 26 and output. The pulse ratio measuring circuit 24 measures the ratio of the pulse width of the current output signal b to the pulse width of the previous output signal b of the filter circuit 20 (current pulse width / previous pulse width), and The fuzzy inference unit 26 converts into a plurality of bits and outputs the converted bits.

The fuzzy inference unit 26 includes both measurement circuits 22,
24. Fuzzy inference, which will be described later, is performed on the basis of both data of the pulse width and the pulse ratio from each of them, and when the input signal a is fuzzy inferred to be a low speed normal signal, the determination signal c corresponding thereto is output to the output conversion circuit. When the input signal a is fuzzy inferred to be a normal signal of high speed to medium speed, the output conversion circuit 28 outputs the judgment signal d corresponding thereto.
Respectively, to output.

The output conversion circuits 30 and 32 respectively convert the fuzzy inference outputs having a plurality of bits from the fuzzy inference unit 26 into fuzzy inference outputs f and e having a 1-bit structure and output the fuzzy inference outputs f and e. That is, the output conversion circuit 30 converts the fuzzy inference signal c that the input signal a from the fuzzy inference unit 26 is low speed, and outputs the converted signal f to the output circuit 40 as it is as a counting signal. Then, the signal is output to the OR gate G7 as a reset signal k for the first and second counters 32 and 34 and the flip-flop FF6 to invalidate the count of the first counter 32. The output conversion circuit 28 converts the fuzzy inference signal d from the fuzzy inference unit 26 that the input signal a is a normal signal of high speed to medium speed, and converts the converted signal e into the first counter 32 and the flip-flop FF6. Output.

The first counter 32 includes a fuzzy inference unit 26.
Then, the number of the signals e formed by the output conversion circuit 28 of the fuzzy inference signal d judged that the input signal a is a normal signal of high speed to medium speed is counted. That is, the first counter 32 counts the signal e, updates the count value sequentially as v1, v2, ..., V4 each time the count number increases by 1, and outputs the count value to the three-state buffer G8. ..

The flip-flop FF6 is set at the rising edge of the conversion signal e from the output converting circuit 28, and is reset at the rising edge of the resetting signal k from the OR gate G7. Then, the flip-flop FF6 is
By this setting, the set output g is output from the output terminal Q, and the AND gate G6 is opened.

The second counter 34 counts the filter clock CK1 input when the gate of the AND gate G6 is opened as a count pulse h, and when the count value is a predetermined value, counts up and outputs a count-up output i. To the three-state buffer G8,
The three-state buffer G8 is turned on. here,
The second counter 34 operates to count the count pulse h and measure the sampling time while the set output g is input from the output terminal Q of the flip-flop FF6, and controls the on-timing of the three-state buffer G8. I am able to do it.

The output circuit 36 outputs the count output j from the first counter 32 via the slithate buffer G8.
Further, the fuzzy inference unit 26 outputs a signal f as a counting pulse.

Next, the fuzzy inference unit 26 will be described. The fuzzy inference unit 26 has the following fuzzy rules.

If WID = PB & PRO = PB then SIG = PB if WID = NB & PRO = ZR then SIG = ZR if WID = ZR & PRO = ZR then SIG = ZR if WI = PB & PRO = ZR BN SIG = PB then PRO NB where if is the conditional part (the antecedent part), and the
n is the conclusion part (consequent part), WID is the antecedent part variable of the current pulse width measurement value from the pulse width measurement circuit 22, and PRO is the pulse ratio (current time) from the pulse ratio measurement circuit 24. Is the antecedent variable of the measured value, and SIG is the antecedent variable of the pulse determination result, that is, the normality, noise-likeness and chattering-likeness of the pulse of the input signal. Also, the label WID
, PB has a large pulse width of the input signal a, ZR
Is the pulse width of the input signal a is medium, NB is the input signal a
Has a small pulse width. In the case of the label PRO, the pulse width of the input signal a this time of PB has become sharply larger than that of the previous time. In ZR, the pulse width of the input signal a this time was almost the same as that of the previous time. In the NB, the pulse width of the input signal a this time becomes sharply smaller than that of the previous time. In the label SIG, PB determines that the input signal a is a low-speed normal signal, ZR determines that the input signal a is a high-speed to medium-speed normal signal, and NB determines that the input signal a is noise. The membership functions of WID, PRO, and SIG are as shown in FIG.

The inference method in the fuzzy inference unit 26 uses the MIN-MAX logical product method. First, for each fuzzy rule, each antecedent variable WID, PRO.
The minimum value of each membership value is selected as the suitability of the antecedent part by using the membership functions of WID and PRO of FIG. And each fuzzy rule ~
The membership function shown in FIG. 3 of each consequent part variable SIG is cut by each antecedent part variable conformity. By this cutting, the membership value of the consequent part variable of each fuzzy rule ~ is obtained, but the one with the largest membership value among the same consequent part variables is selected, and From the inside, the one having the largest position data on the X coordinate axis on the membership function of SIG in FIG. 3, that is, the one on the right side is selected by the right priority height method.

As described above, when the input signal a is fuzzy inferred from the fuzzy inference unit 26 by such fuzzy inference, the judgment signal c corresponding to it is fuzzy inferred to be high to medium speed. When it does, the decision signal d corresponding to it is output, respectively.

The operation will be described with reference to the timing charts of the signals in the respective parts of FIG.

(A) When the input signal a1 is input to the filter circuit 20: This input signal a1 includes a high-speed input signal and a medium-speed input signal. Particularly, a high-speed input signal is shown in FIG. It's noise as you fill it in. When such a input signal a1 is input, the filter circuit 20, when the pulse width of each pulse forming the input signal a1 is four times or more of the cycle of the filter clock CK1, inputs the normal input signal a1. Is output as a filter, and is not output when the cycle is four times or less. In the case of the input signal a1 shown in FIG. 2, both noise and normal signals are filtered as normal signals of high speed to medium speed and output as the output signal b. The pulse width measuring circuit 22 measures the pulse width of the input signal a1 from the output signal b and outputs the measured value to the fuzzy inference unit 26 and also to the pulse ratio measuring circuit 24. The pulse ratio measurement circuit 24 stores the pulse width of the previous input signal a1, measures the ratio between the pulse width of the current input signal a1 and that of the previous input signal a1, and outputs the measured value to the fuzzy inference unit 26. .. The fuzzy inference unit 26 performs fuzzy inference according to the above fuzzy inference using the measured values of the pulse widths and pulse ratios from the respective measurement circuits 22 and 24 as antecedent variables, and removes noise in the input signal a1. And outputs the signal d. This signal d is converted into a signal e by the output conversion circuit 28.

The signal e is sent to the first counter 32.
And the flip-flop FF6. In the first counter 32, the number of signals e is counted value v1,
Count as v2. The count value in this case is v4 because the number of pulses forming the input signal a1 is four, excluding noise. The count value output from the first counter 32 is output by the second counter 34.
Counts the filter clock CK1 as a count pulse h through the AND gate G6 and counts up (sampling time). The count-up output i is given to the three-state buffer G8 to turn on the three-state buffer G8. When it becomes, it is output to the output circuit 36. At this time, the count value output j from the first counter 32 is given to the first and second counters 32 and 34 and the flip-flop FF6 via the OR gate G7 as the reset output k, and thus they are reset.

(B) When the input signal a2 is input to the filter circuit 20: The input signal a2 contains chattering when the width of the signal is switched by a contact or the like, and p1 and p2 are Each is chattering, p
3 is a normal input signal. Therefore, it is necessary to remove the chattering p1 and p2 from the count target. First, the filter circuit 20 filters the input signal a2 as a cycle that is four times as long as the filter clock CK1 or more, outputs it as an output signal b, and outputs it to the pulse width measurement circuit 22. The pulse width measuring circuit 22 performs the above-mentioned measurement and outputs the measured value to the pulse ratio measuring circuit 24. The pulse ratio measuring circuit 24 also performs the same measurement as described above. Both of these measured values are output to the fuzzy inference unit 26. The fuzzy inference unit 26 performs the same fuzzy inference as described above. In this fuzzy inference, the chattering p1 and p2 are judged to be high-speed input signals, and the corresponding judgment signal d is
Regarding the signal p3, this is judged to be a low-speed input signal, and corresponding judgment signals c are output. These are converted by the output conversion circuits 30 and 28, respectively, and the signals f and e are converted.
Becomes The signal f is directly output as a counting pulse from the output circuit 36, and the signal e is counted by the first counter 32, but the signal f is given to the first counter 32 as a reset signal k via the OR gate G7. Therefore, the count of the first counter 32 is reset. In this example, the count value of the first counter 32 is v2, and it is shown that the count value is reset corresponding to the signal f.

(C) When the input signal a3 is input to the filter circuit 20: The filter circuit 20 receives the input signal a3.
3 is filtered as normal and is output to the pulse width measuring circuit 22. The operation thereafter is the same as that described above, but in the fuzzy inference unit 26, both measurement circuits 22,
Fuzzy inference is performed according to the measured value from 24, and the determination signal c that the input signal a3 is slow is output. This judgment signal c is given to the output circuit 36 via the output conversion circuit 30.

As described above, in the present embodiment, the input signals a1, a2 and a3 are selected from among the input signals a1, a2 and a3 without the user performing the operation of switching the filter clock between CK1 and CK2 with the conventional clock setting switch or the like. First, for the input signal a1, noise is removed by the fuzzy inference unit 26, and then the count value of the first counter 32 is directly output to the output circuit 36. For the input signal a2, chattering is generated. Only the part of p3 that has been removed is used as a pulse for counting, and the input signal a3
However, the frequency of the filter clock is automatically output as a counting pulse to the output circuit 30 without any consideration by the user regarding the pulse width of the input signal and without being affected by chattering. Can be switched.

[0036]

As is clear from the above description,
According to the invention, it comprises a filter means, a measuring means, a fuzzy inference means and a counter means, the filter means comprising:
An input signal is input to a plurality of flip-flops having a cascade connection configuration, the flip-flops are sequentially inverted in response to the filter clock, and the output of each flip-flop is logically ANDed to obtain an output signal. And the measuring means measures the pulse width and pulse ratio of the input signal (the ratio of the pulse width of the previous input signal and the pulse width of the current input signal) from the output signal from the filter means, The fuzzy inference means fuzzy infers whether the input signal is noise-like or normal signal-like based on the both measured values, and the counter means measures a constant sampling time and, within the sampling time, fuzzy The number of pulses of a normal signal from the inference means is counted and the count value is output as a signal. Therefore, even if the input signal contains high-speed to medium-speed noise and is output from the filter circuit, the fuzzy inference means removes the noise in the input signal by fuzzy inference, and the remaining normal The signal will be counted by the counter means, and
If the input signal includes chattering and the chattering is output from the filter circuit together with the normal signal, the fuzzy inference means outputs only the low speed normal signal and eliminates the chattering.

Therefore, according to the present invention, it becomes unnecessary for the user to switch and select the filter clock by the setting operation, and the chattering can be removed from the input signal without being affected by noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a digital input circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a diagram showing a membership function in a fuzzy inference unit according to an embodiment.

FIG. 4 is a circuit diagram of a digital input circuit according to a conventional example.

FIG. 5 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 20 Filter Circuit 22 Pulse Width Measuring Circuit 24 Pulse Ratio Measuring Circuit 26 Fuzzy Inference Unit 32, 34 Counter

Claims (1)

[Claims] 1. A filter means (20) and a measuring means (22,
24), fuzzy inference means (26), and counter means (24, 26), and the filter means (20) inputs an input signal to a plurality of flip-flops in cascade connection and In order to obtain an output signal by logically inverting the outputs of the respective flip-flops in response to the filter clock, the measuring means (22, 24) outputs the output signal from the filter means (20). To measure the pulse width and pulse ratio of the input signal (the ratio between the pulse width of the previous input signal and the pulse width of the current input signal), and the fuzzy reasoning means (26) Fuzzy inference is performed based on whether the input signal is noise-like or normal signal-like, and the counter means (24, 26) has a fixed sampling time. A digital input circuit, which measures the number of pulses of a normal signal from the fuzzy inference means (26) within the sampling time and outputs the count value as a signal.