JPH0548437U - Frequency multiplier circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a frequency multiplier that does not cause jitter in the output value. A first frequency dividing circuit for frequency-dividing an input pulse signal into a 1/2 frequency signal, a second frequency dividing circuit for frequency-dividing a sufficiently small clock signal by a predetermined value, and a first frequency dividing circuit. A counter for counting the number of clock signals divided by the second divider circuit included in the pulse output period of the input pulse signal divided by the divider circuit, and the number counted by the counter is latched Latch circuit, a third frequency divider circuit for dividing the clock signal by the number latched in the latch circuit, and a retiming circuit for generating timing signals for the counting operation in the counter and the latch operation in the latch circuit. When the difference between the number counted by the counter and the number latched by the latch circuit is 1 in the frequency multiplication circuit provided, the timing operation for performing the latch operation is performed. A comparator circuit is provided to inhibit the generation of the trigger signal.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a frequency multiplication circuit that multiplies and outputs the frequency of a pulse signal whose frequency changes.

[0002]

[Prior Art]

 FIG. 3 is a diagram showing a configuration of a frequency multiplication circuit which has been conventionally used.

The duty ratio of the input pulse signal fin is 50% by the frequency dividing circuit 301 which is the first frequency dividing circuit, and the input pulse signal fin is converted into a pulse signal having a frequency of ½ of the input pulse signal fin, and the two input signals are input. Input to one input terminal of the AND gate 303. The other input terminal of the AND gate 303 is supplied with the clock signal CLK divided into 1 / A by the frequency dividing circuit 302 which is the second frequency dividing circuit. Here, the frequency of the input pulse signal fin, the frequency of the clock signal CLK, and the frequency dividing value A in the frequency dividing circuit 302 are set so that the output frequency of the frequency dividing circuit 302 is sufficiently higher than the output frequency of the frequency dividing circuit 301. Therefore, the clock signal CLK divided into 1 / A appears in the output of the AND gate 303 only during the period of the pulse output of the division circuit 301. The output of the AND gate 303 is supplied to the counter 304 as a clock signal, and the counter 304 counts the number of clocks (pulses) and outputs a signal indicating the count value. The output signal is latched by the latch circuit 305 and output to the frequency dividing circuit 306 which is the third frequency dividing circuit as the value N that determines the frequency dividing ratio. The clock signal CLK is also input to the frequency dividing circuit 306, and the clock signal CLK is frequency-divided by the value N to output the output signal fout.

Here, the frequency of the output signal fout is CLK / N, but the value of N is 1 / fin = N / (CLK / A) (1) from the width of each pulse. , And the output fout is defined as fout = A · fin (2), then fout = CLK / N (3), and the output signal fout is A times the input pulse signal fin. Frequency appears.

FIG. 4 is a circuit diagram embodying the block diagram shown in FIG.

[0006] The circuit shown in FIG. 3 is constituted of a flip-flop circuit 401 ₁ to 401 _6, the AND gate 40 2 _{1-402 4,} divider circuit 403, the up-counter 404, a latch circuit 405 and the down counter 406 ..

The flip-flop circuit 401 ₁ in the figure constitutes the frequency dividing circuit 301 shown in FIG. 3, and the down counter 406, the flip-flop circuit 401 ₂ and the AND gate 402 ₂ constitute the frequency dividing circuit 306 in FIG. To do.

[0008] D flip-flop circuit 401 ₁ is flip-flop intended to be used as a 1/2 frequency divider circuit, is supplied an input pulse signal fin to the clock terminal, the data terminal D is supplied inverted output There is. As a result, a Q output and an inverted output with a frequency of fin / 2 and a duty of 50% are obtained. The Q output is input to one input terminal of the AND gate 402 ₁ and the data terminal D of the flip-flop circuit 401 ₃ .

[0009] The clock signal CLK is supplied to the clock terminal of the flip-flop circuits 401 ₂ to 401 ₆ after being frequency divider 403 and the down counter 406, and inverted. The divider circuit 403 divides the supplied clock signal CLK into 1 / A and outputs it to the other input terminal of the AND gate 402 ₁ .

The up counter 404 inputs the output of the AND gate 402 ₁ and counts the number of pulses thereof. This count value N is sent to the down counter 406 after being latched by the latch circuit 405. The count value N input in the down counter 406 counts down at the period of the clock signal CLK, and this value is zero when one of the input terminals and The flip-flop circuit 401 ₂ Data ripple carry signal AND gate 402 ₂ Output to the terminal. The clock signal CLK is inverted and input to the flip-flop circuit 401 ₂ , and its Q output which is the output signal fout is supplied to the other input of the AND gate 402 ₂ . Further, since the output of the AND gate 40 2 ₂ is supplied to the load terminal of down counter 406, the down counter 406 to load the data each time the ripple carry signal described above is output, the input signal fin is A times The output signal fout multiplied by is output.

Each flip-flop circuit 401₃~ 401₆And each AND gate 402₃, 402_FourIs a retiming circuit for generating the reset signal of the up-counter 404, the latch circuit 405, and the clock signal, respectively, and is connected in order so that the Q output of each flip-flop circuit is supplied to the data terminal. ing . And gate 402₃The flip-flop circuit 401_FourQ output and flip-flop circuit 401_FiveAnd the inverted output of the_FourThe flip-flop circuit 401_FiveQ output and flip-flop circuit 401 ₆ Both the inverted output and the inverted output of are input. Each AND gate 402₃, 402_FourIs supplied to the clock terminal of the latch circuit 405 and the reset terminal of the up counter 404, whereby the up counter 404 and the latch circuit 405 update the data.

[0012]

[Problems to be solved by the device]

 In the conventional frequency multiplier circuit described above, the number N of the clock signal CLK divided into 1 / A included in the pulse output of the input signal fin divided by 2 is performed to count the number N. Although the frequency operation is performed, the value of N fluctuates within a range of ± 1 depending on the phase of the clock signal CLK divided into 1 / A as shown in FIG. There is a problem that this fluctuation appears in the output signal fout as jitter.

The present invention has been made in view of the above-described conventional technique, and an object of the present invention is to realize a frequency multiplication circuit that does not cause jitter in the output value.

[0014]

[Means for Solving the Problems]

 The frequency multiplying circuit of the present invention comprises a first frequency dividing circuit for dividing an input pulse signal into a 1/2 frequency signal and a second frequency dividing circuit for dividing a sufficiently small clock signal by a predetermined value. A circuit, a counter for counting the number of clock signals divided by the second divider circuit included in the pulse output period of the input pulse signal divided by the first divider circuit, A latch circuit that latches the number counted by the counter, a third frequency divider circuit that divides the clock signal by the number latched by the latch circuit, a counting operation in the counter, and a latch circuit in the latch circuit. In a frequency multiplication circuit comprising a retiming circuit for generating a timing signal for latch operation, the number counted by the counter and the latch circuit If the difference between the number that is 1, comparison circuit inhibits the generation of the timing signal for latch operation is provided.

[0015]

[Action]

 When the difference between the number counted by the counter and the number latched by the latch circuit is 1 by the comparison circuit, generation of the timing signal for performing the latch operation is prohibited, and the count number is the clock signal. Since the latch operation is not performed when the phase fluctuates, the jitter due to this does not occur in the output signal.

[0016]

【Example】

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention.

The configuration and operation of each of the flip-flop circuits 101 _{1 to} 101 ₆ , AND gates 102 ₁ to 102 ₄ , frequency dividing circuit 103, up counter 104, latch circuit 105, and down counter 106 in FIG. since the flip-flop circuit 401 ₁ to 401 ₆ shown, the aND gate 402 ₁ to 402 _4, the frequency divider circuit 403, up the loop counter 404 is similar to the latch circuit 405 and the down counter 406, the description thereof will be omitted.

[0019] In this embodiment, adder circuit 107 _1, 107 ₂ constituting the comparison circuit In addition, comparators 108 _1, 108 _2, NOR gate 109, AND gate 102 _5, 102 ₆ and a flip-flop circuit 101 ₇ It is provided.

The count value N output from the up counter 104 is sent to the comparator 108 ₁ and the adder circuit 107 ₂ in addition to the latch circuit 105, and the latch output in the latch circuit 105 is added to the adder circuit 107 in addition to the down counter 106. It is sent to ₁ and the comparator 10 8 _2. The outputs of the comparators 108 ₁ and 108 ₂ are input to the NOR gate 109, and the output of the NOR gate 109 is inverted and supplied to one input terminal of the AND gate 102 ₅ . The Q output of the flip-flop circuit 101 ₁ is inverted and supplied to the other input terminal of the AND gate 102 ₅ , and its output is supplied to the clock terminal of the flip-flop circuit 101 ₇ . The output of the AND gate 102 ₄ is inverted and input to the set terminal of the flip-flop circuit 101 ₇ , and its Q output is supplied to one input terminal of the AND gate 102 ₆ . The other input terminal of the AND gate 102 ₆ is supplied with the output of the AND gate 102 ₃ , and the output is supplied to the clock terminal of the latch circuit 105.

Next, the operation of this embodiment will be described.

The adder circuit 107 ₁ adds 1 to the value currently latched by the latch circuit 105 and outputs the value to the comparator 108 ₁ . The comparator 108 ₁ compares this value with the count value N in the up counter 104, and outputs a high level signal when these values match. On the other hand, the adder circuit 107 ₂ adds 1 to the count value N of the up counter 104 and outputs it to the comparator 108 ₂ . Comparator 10 8 ₂ compares the value latched at the value and the current latch circuit 105 outputs a high level signal when these values match. Since the output of each comparator is supplied to the input terminal of the NOR gate 109, if the output of the NOR gate 109 is equal to the value currently latched in the latch circuit 105 and the count value N of the up counter 104, Alternatively, when the difference between these respective values is 2 or more, it becomes a high level, and the AND gate 102 ₅ , the flip-flop circuit 101 ₇ and the AND gate 102 ₆ operate to supply the clock signal to the latch circuit 105. As a result, the latch circuit 105 latches the new count value N output from the up counter 104.

When the difference between the value currently latched in the latch circuit 105 and the count value N in the up counter 104 is 1, one of the comparators outputs a high level and the output of the NOR gate 109. Becomes low level, supply of the clock signal to the latch circuit 105 is prohibited, and the latch circuit 105 maintains the value currently latched.

In the present embodiment, when the count value N fluctuates within the range of ± 1 as described above, the latch operation by the latch circuit 105 is prevented, and the jitter resulting from this appears in the output value. It was prevented.

FIG. 2 is a circuit diagram showing the configuration of the second embodiment of the present invention.

In this embodiment, the input data to each adder circuit and each comparator in the first embodiment shown in FIG. 1 is made different. Since the other structure is similar to that of the first embodiment, the same reference numerals as those in FIG.

In the present embodiment, the values currently latched by the latch circuit 105 are input to each of the adder circuits 107 ₁ and 107 ₂ . The adder circuit 107 ₁ adds _{1 to} this input value and outputs it to the comparator 108 ₁ , and the adder circuit 107 ₂ subtracts 1 from this input value and outputs it to the comparator 108 ₂ . In addition to these inputs, the count value N output from the up counter 104 is also input to each comparator, and when the input values match each other, a high level is output as in the case of the first embodiment. Therefore, also in the present embodiment, the latch operation by the latch circuit 105 is prohibited when the count value N fluctuates within ± 1 as in the first embodiment.

[0028]

[Effect of the device]

 In the present invention, when the difference between the number counted by the counter and the number latched by the latch circuit is 1, by providing the comparison circuit for inhibiting the generation of the timing signal for performing the latch operation, This has the effect of preventing the appearance of jitter in the output value.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

FIG. 4 is a circuit diagram showing the configuration of a conventional example in detail.

FIG. 5 is a diagram for explaining a change in a count value N depending on a clock phase.

[Explanation of symbols]

101 _{1 to} 101 ₇ flip-flop 102 _{1 to} 102 ₆ AND gate 103 frequency divider circuit 104 up counter 105 latch circuit 106 down counter 107 ₁ , 107 ₂ adder circuit 108 ₁ , 108 ₂ comparator 109 NOR gate

Claims (1)

[Scope of utility model registration request] 1. A first divider circuit for dividing an input pulse signal into a 1/2 frequency signal, and a second divider circuit for dividing a sufficiently small clock signal by a predetermined value. A counter for counting the number of clock signals divided by the second divider circuit included in the pulse output period of the input pulse signal divided by the first divider circuit; A latch circuit for latching the selected number, a third frequency divider circuit for dividing the clock signal by the number latched in the latch circuit, timing of the count operation in the counter and the latch operation in the latch circuit In a frequency multiplication circuit including a retiming circuit for generating a signal, a difference between the number counted by the counter and the number latched by the latch circuit. When 1 is 1, a frequency multiplying circuit is provided, which is provided with a comparison circuit for inhibiting generation of a timing signal for performing a latch operation.