JPH0548461A - A/d converter - Google Patents

Abstract

PURPOSE:To improve the resolution and the versatility by providing 1st and 2nd counters to the A/D converter, counting a clock signal only during the count operation of the 1st counter to obtain a digital value proportional to an input voltage and using a setting value for the 1st counter to be a prescribed count time. CONSTITUTION:A V/F converter 11 outputs a pulse of a frequency F proportional to an analog input voltage V. A 1st counter 12 counts number of pulses by a value N set by a computer 13 and an on-state is obtained at an output OUT for that time. A 2nd counter 14 counts the number of clocks from a reference oscillator 15 only for a period when the output OUT of the counter 12 is in the on-state to obtain a count M. The computer 13 obtains a digital data proportional to the analog input based on a preceding setting data and a coefficient. Based on the data, the setting value N of the 1st counter 12 is adjusted to make almost the count time constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A for converting an analog signal into a digital signal and loading it into a computer or the like.
The present invention relates to a / D converter.

[0002]

2. Description of the Related Art Various control devices using a computer as a control center convert many analog signals of measured values and set values into digital signals and perform data processing to improve control performance.

A conventional A / D converter is shown in FIG. In the system shown in FIG. 3A, an analog voltage from a setting device 1 such as a potentiometer is converted into a digital signal by an A / D converter 2 and is taken into a computer 3. In the method of FIG. 2B, the analog voltage from the setter 1 is converted into a pulse having a proportional frequency by the voltage-frequency converter 4,
This pulse is used as the count input of the counter 5, and the counter 5 is caused to count for the gate signal period of the fixed time from the computer 3, and the count value of the counter 5 is taken into the computer 3 as a digital signal proportional to the analog voltage.

The setter 1 is replaced with a sensor and a voltage amplifier to capture the measured value.

[0005]

In the conventional device, the A
Various types of / D converters 2 are commercially available, but those having a resolution of 10 bits or more are expensive.

On the other hand, in the case of using the V / F converter 4 and the counter 5, in order to improve the resolution, the counting time (sample time) is lengthened or the full-scale frequency of the V / F converter 4 is increased. .. However, if you increase the counting time,
The conversion time (data input interval) becomes long, such as 0.1 seconds, and the problem of responsiveness remains in the acquisition of measured values.
Conversely, when increasing the full-scale frequency, expensive V /
It becomes an F converter.

For example, to obtain a resolution of 16 bits, a full-scale frequency is 1 MHz and a counting time of 65 ms is required.

An object of the present invention is to provide an A / D converter having a voltage-frequency converter and a counter, which has a high full resolution while having a low full-scale frequency and a short counting time, and which has high versatility. To provide.

[0009]

In order to solve the above-mentioned problems, the present invention provides a voltage-frequency converter which obtains a pulse having a frequency proportional to an analog input voltage, and a value N set with the pulse as a count input. A first counter for counting, a second counter for counting clock signals only during the counting operation of the first counter, and a count value M of the second counter
From the data n to obtain a digital data n proportional to the analog input voltage, obtain a value for making the counting time of the first counter substantially constant, and give a set value N of the first counter. It is characterized by having.

[0010]

According to the present invention having the above structure, the full scale and the counting time are set low by lowering the frequency of conversion and counting by the V / F converter and the first counter, and the counting of the first counter is performed. High resolution can be obtained by converting the data obtained by counting the clock by the second counter into digital data converted at time. In addition, the set value N of the first counter
Is set to a substantially constant counting time, so that a wide range of analog input voltages can be supported without causing deterioration in response.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an apparatus showing an embodiment of the present invention. The V / F converter 11 outputs a pulse having a frequency F proportional to the analog input voltage V. The first counter 12 counts the pulses from the V / F converter 11 by a value N set (for example, preset) from the computer 13, and obtains an ON state at the output OUT during this period. Also, the counter 12
Starts counting the first pulse F when the trigger signal (G input) from the computer 13 is given, and turns off the output at the final count N. Therefore, the count of the counter 12 is completely synchronized with the output pulse of the V / F converter 11.

The second counter 14 is reset when the output OUT of the counter 12 is turned on, counts the clock from the reference oscillator 15 (or the computer 13) for the period T _C in which the output OUT is turned on, and counts the count value. Get M.

The computer 13 is started by using the output OUT at the end of counting of the counter 12 as an interrupt signal INT or by receiving the end of counting of the counter 12 by polling. The processing of the computer 13 by this activation is as shown in FIG.

The computer 13 takes in the data M of the counter 14 (step S1), and n = (as a value n as digital data proportional to the analog input from this data M, the previous setting data N _i-1 and the coefficient K _C. N _i-1 × K _C ) / M is calculated (step S2), and the coefficient K _N
Setting data N _i (= n × K _N ) multiplied by is obtained (step S3), this setting data N _i is stored in the counter 12 (step S4), and a trigger for the counter 12 is generated (step S5). Here, the coefficient K _C is the computer 1
It is a coefficient that is converted into the data actually needed within 3.
It is determined from the clock frequency of the reference oscillator 15 and the like. Also,
The coefficient K _N is used to make the next sampling time from the current data n a substantially constant time T _C.

The operation waveform diagram of this embodiment is as shown in FIG. A pulse having a frequency proportional to the analog input voltage V is taken out as the output F of the V / F converter 11, and the counter 12 starts counting in synchronization with the signal F by the trigger input following the setting of the setting data N from the computer 13. At the same time (time t ₁ ), at the same time, the output out of the counter 12 is turned on and the counter 14 is instantly reset.

Accordingly, the counting of the counter 14 is started at the same time when the counting of the counter 12 is started, and the counting value of the counter 14 increases with respect to the counting value of the counter 12 by the ratio of the clock frequency f _C and the input F of the counter 12. The data M is proportional to the signal F.

When the count value of the counter 12 reaches the set data N (time t ₂ ), its output out is switched from on to off, the counting of the counter 14 is stopped at the same time, and the interrupt INT is sent to the computer 13. Be seen.

By this interrupt, the computer 13 stores the data M as a value proportional to the analog input voltage V by loading the data M and calculating the digital data n from this data M according to the procedure of FIG. By changing the coefficient K _N to obtain the next setting data N _i ,
The set value N is stored in the counter 12, and the counter 12
The counting operation of the counters 12 and 14 is restarted by the trigger of.

[0019] In this case, set by the multiplication of K _N data N
Is a constant counting time T _C even when the frequency of the counter input F changes.
Therefore, in order to make the digital data n actually used proportional to the analog input, conversion is performed by the coefficient K _N used for the previous N setting.

According to this embodiment, the counter 12 sets the setting data N corresponding to the measurement time (sampling time) T _C.
The counter 14 counts the clock at the time T _C during the counting to obtain digital data proportional to the analog input V.

Therefore, the counting is completely synchronized with the output of the V / F converter 11, and there is no deviation in the timing of starting and ending the counting, and a highly accurate A / D converter is obtained.

The resolution of the digital data n to be obtained is determined by the count value M of the counter 14, and this M
In order to keep the counting time T _C substantially constant, M = f _C × T _C , and the resolution is determined by f _C and T _C. This is
It is not affected by the value of the setting data N, that is, the full scale of the V / F converter 11 is low and the first counter counting time is low, so that high resolution can be realized. For example, to obtain 16-bit resolution, F = 200KH
z, f _C = 8 MHz and T _C = 8.2 ms are sufficient, the full scale can be lowered, and the counting time T _C can be shortened to about 10 ms. Furthermore, the versatility can be enhanced by making the analog input range optional.

In the embodiment, the computer 13
The processing of FIG. 2 can be configured such that arithmetic means dedicated to the A / D conversion device is provided and only the digital data that has been A / D converted is provided to the computer 13 from this arithmetic means.

[0024]

As described above, according to the present invention, V / F
Set value N at low frequency by converter and first counter
Count the clock with the second counter during the counting time up to
Digital data proportional to the analog input voltage is obtained from this count value, and the set value of the first counter is set based on the data so that the count time becomes almost constant. Therefore, the V / F converter and By lowering the frequency and counting time of the first counter, a general inexpensive V / F converter can be used, and a device with high resolution and high versatility can be obtained without lowering the response.

[Brief description of drawings]

FIG. 1 is a device configuration diagram of an embodiment.

FIG. 2 is a processing procedure diagram of a computer in the embodiment.

FIG. 3 is a waveform chart of each part of the embodiment.

FIG. 4 is a configuration diagram of a conventional device.

[Explanation of symbols]

11 ... V / F converter, 12 ... Counter, 13 ... Computer, 14 ... Counter, 15 ... Reference oscillator.

Claims (1)

[Claims] 1. A voltage-frequency converter that obtains a pulse having a frequency proportional to an analog input voltage, and a first counter that counts the pulse to a set value N by using the pulse as a count input.
A second counter that counts clock signals only during the counting operation of the first counter, and digital data n proportional to the analog input voltage is obtained from the count value M of the second counter, and the digital data n is obtained from the data n. An A / D conversion device, comprising: an arithmetic unit that obtains a value for making the counting time of the first counter substantially constant and gives the set value N of the first counter.