JPH054847B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a transistor differential amplifier circuit suitable for use in an integrated circuit device.

(Prior Art) A transistor differential amplifier circuit shown in FIG. 2 is often used in conventional integrated circuit devices. In FIG. 2, 11 and 12 are first and second input terminals, 1
3 is the power supply voltage V _CC terminal, 14 is the power supply voltage V _EE terminal,
15 is an output terminal. Q1 and Q2 are differential pairs
A PNP transistor, each emitter of which is connected in common, is connected to the V _CC terminal 13 through the first current source I1.
It is connected to the. The base of Q1 is connected to the first input terminal 11 and its collector is connected to the V _EE terminal 14
It is connected to the. The base of Q2 is connected to the second input terminal 12 and its collector is connected to the output terminal 15
and the collector of transistor Q3.

This transistor Q3 is the transistor Q4, Q
5 and resistors R1 and R2 (R1=R2) constitute a current mirror circuit. That is, Q3
The emitter of Q4 is connected to the _VEE terminal 14 through a resistor R1, and its base is connected to the base of Q4. The emitter of Q4 is connected to the V _EE terminal 14 through a resistor R2, and its collector is connected to the V _CC terminal 13 through a second current source I2 and the Q4
It is connected to the base of 5. Q5 collector is
It is connected to V _CC terminal 13, and its emitter is Q3,
Connected to the common base of Q4. Note that the current value ib of the second current source I2 is set to 1/2 of the current value ia of the first current source I1.

The transistor differential amplifier circuit having the above configuration has a first
The output current ia of the first current value I1 is distributed to the transistors Q1 and Q2 according to the difference between the signals S1 and S2 supplied to the second input terminals 11 and 12, and the collector currents iC1, Let iC2 be 1/2ia+α and 1/2ia−α, respectively. Here, the collector current iC3 of the transistor Q3 is the output current ib of the second current source I2 which outputs a current that is 1/2 of the first current value 11.
Since it is a value reflected by a current mirror circuit consisting of resistors R1 and R2, it is 1/2 of the output current ia of the first current source I1. Therefore, the output current iout to the output terminal 15 is
The value is obtained by subtracting the collector current iC3=1/2ia of Q3 from the collector current iC2=1/2ia-α of Q3, and the output signal Sout becomes a signal proportional to the difference between the input signals S1 and S2.

(Problems to be Solved by the Invention) However, the transistor differential amplifier circuit having the above configuration has the following problems. That is, if the current amplification factors of the differential pair transistors Q1 and Q2 are β, the current values of the current sources I1 and I2 are respectively 2I0 and I0, and the error of the current mirror circuit is ignored, the collector currents of the transistors Q1 and Q2 are iC1, iC2 is actually shown in the following equations.

iC2=I0...(1) iC1=2β/β+1I0−iC2 =2β/β+1I0−I0 =β−1/β+1I0…(2) As is clear from equations (1) and (2), the differential pair transistor Q1, Since the collector currents iC1 and iC2 of Q2 have a finite current amplification factor β, a current difference occurs even in a balanced state, and an offset occurs here, as well as a so-called input bias current due to the base currents of Q1 and Q2. Occur. The existence of this input bias current causes problems such as limiting the use of high resistance values and the realization of high gain when the differential amplifier circuit is actually used. In particular, when PNP transistors are used as the differential pair transistors Q1 and Q2, the above problem becomes more pronounced because the current amplification factor of the PNP transistors tends not to be very large in the integrated circuit device.

It is an object of the present invention to provide a transistor differential amplifier circuit suitable for use in an integrated circuit device, which can improve the above-mentioned problems, prevent the occurrence of offset in differential pair transistors, and suppress input bias current. shall be.

[Structure of the invention]

(Means for solving the problem) A transistor differential amplifier circuit according to the present invention includes:
The first and second electrodes have the same characteristics and are connected to each control electrode.
first and second transistors to which an input signal is supplied and one of the controlled electrodes is commonly connected; and a first current that supplies current to the commonly connected controlled electrodes of the first and second transistors. a second current source that generates a current having a predetermined ratio to the current value of the first current source, and a current generated by the second current source that is derived and connected to the first and second transistors. a third transistor having similar characteristics; a first current mirror circuit that supplies a current equivalent to the output current of the third transistor to the other controlled electrode of the second transistor; a second current mirror circuit that supplies each control electrode of the first and second transistors with a current equivalent to the current flowing through the control electrode of the transistor,
The output current is configured to be taken out from the other controlled electrode of the second transistor.

(Function) The transistor differential amplifier circuit with the above configuration is
A third transistor having the same characteristics as the first and second transistors is connected between the second current source and the first current mirror circuit.
By connecting two transistors, the difference in current between the other controlled electrodes of the first and second transistors is eliminated to prevent offset, and a current equivalent to the current flowing through the control electrode of the third transistor is connected to the second transistor. By causing the input bias current to flow to the control electrodes of the first and/or second transistors through the current mirror circuit, the input bias current flowing to the control electrodes of the first and second transistors is canceled out and suppressed.

(Embodiment) An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows a configuration in which the present invention is applied to the circuit shown in FIG. 2. Here, the same parts as in FIG. 2 are denoted by the same reference numerals, and the explanation thereof will be omitted. Note that the transistors Q3, Q4, Q
5 and resistors R1 and R2 (R1=R2) is defined as a first current mirror circuit.

That is, the first and second input terminals 11,
12 are connected to the collectors of transistors Q6 and Q7, respectively. Transistors Q6 and Q7 constitute a second current mirror circuit together with transistors Q8 and Q9. That is, Q6, Q7, Q
8 bases are commonly connected and each emitter is connected to V _EE
The collector of Q8 is connected to the base of Q9, and the collector of Q9 is connected to V _CC terminal 13.
and its emitter is connected to the common base of Q6, Q7, and Q8. On the other hand, between the collector of the transistor Q4 and the second current source I2,
A PNP transistor Q10 is interposed. This transistor Q10 is a differential pair transistor Q1, Q
It has the same characteristics as 2, and its emitter is the current source I.
2, its collector is connected to the collector of Q4, and its base is connected to the collector of Q8.

In other words, this transistor differential amplifier circuit is
A differential pair transistor Q is connected between the second current source I2 and the transistor Q4 of the first current mirror circuit.
By connecting a transistor Q10 with the same characteristics as 1 and Q2, differential pair transistors Q1 and Q2
This eliminates the difference between the collector currents iC1 and iC2 and prevents offset. Also, transistor Q10
By causing a current equivalent to the base current of Q1 to flow through the bases of the differential pair transistors Q1 and Q2 through the second current mirror circuit, the input bias current generated at the bases of Q1 and Q2 is canceled.

In other words, the current amplification factors of the transistors Q1, Q2, and Q10 are β, and the current amplification factors of the first and second current sources I1 and I2 are
If the current values of are respectively 2I0 and I0 and the errors of the first and second current mirror circuits are ignored, the collector currents of transistors Q1, Q2, and Q10 are
iC1, iC2, and iC10 are each expressed as follows.

iC10=β/β+1I0…(3) iC2=iC10=β/β+1I0…(4) iC1=2β/β+1I0−iC2 =2β/β+1I0−β/β+1I0 =β/β+1I0…(5) As is clear from the above equation , transistor Q1,
Collector currents of Q2 and Q10 iC1, iC2, iC1
0 will be the same, so no offset will occur.

Further, base currents iB1, iB2, and iB10 of transistors Q1, Q2, and Q10 are expressed by the following equations, respectively.

iB1=iC1/β=1/β+1I0...(6) iB2=iC2/β=1/β+1I0...(7) iB3=iC3/β=1/β+1I0...(8) As is clear from the above equation, transistor Q1,
Since the base currents of Q2 and Q10 are equal to each other,
The base current of transistor Q10 is transferred to differential pair transistors Q1,
By folding back to the base of Q2, the base current can be accurately canceled. Therefore, the input bias current can be completely suppressed.

Therefore, the transistor differential amplifier circuit configured as described above can prevent the offset of the differential pair transistors and suppress the input bias current, so it can be used as a differential pair transistor.
No harm will occur even if a PNP transistor is used.
Therefore, it can be said to be a very effective means for integrated circuit devices.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a transistor differential amplifier circuit suitable for use in an integrated circuit device, which can prevent the occurrence of offset in differential pair transistors and suppress input bias current. can.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a transistor differential amplifier circuit according to the present invention, and FIG. 2 is a circuit diagram showing the configuration of a conventional transistor differential amplifier circuit. 11, 12...Input terminal, 13...Power supply voltage V _CC terminal, 14...Power supply voltage V _EE terminal, 15...Output terminal,
S1, S2...input signal, Sout...output signal, Q1,
Q2...Differential pair transistor, I1, I2...Current source.

Claims (1)

[Claims] 1. First and second transistors that have the same characteristics, each control electrode is supplied with a first and second input signal, and one controlled electrode is commonly connected, and the first and second transistors have the same characteristics. a first current source that supplies current to a connected controlled electrode; a second current source that generates a current having a predetermined ratio to the current value of the first current source; A third transistor having the same characteristics as the first and second transistors generates a generated current, and a current equivalent to the output current of the third transistor is applied to the other controlled electrode of the second transistor. and a second current mirror circuit that supplies a current equivalent to the current flowing through the control electrode of the third transistor to each control electrode of the first and second transistors. A transistor differential amplifier circuit, wherein the output current is extracted from the other controlled electrode of the second transistor.