JPH054865B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention converts a signal received as a ternary signal into two
The present invention relates to a decoder that performs maximum likelihood decoding to reduce code errors when identifying the code of a value.

[Prior art]

In some cases, a binary code signal is converted into a ternary code signal for transmission or recording. The ternary signal is
It can be constructed so as not to contain a direct current component, and is often used in systems that cannot or are difficult to transmit or record direct current.

The method of converting a binary signal to a ternary signal is as follows:
For example, (1) each time a 1 occurs, it is converted to +1 and -1 alternately, and 0 is converted to 0, (2) when it changes from 0 to 1, it is converted to +1, and when it changes from 1 to 0, it is converted to -1. There are methods such as setting it to 0 when the same level continues. To reverse the conversion from ternary to binary, first convert the received signal to ±1, 0 using thresholds of 0.5, -0.5.
, and perform the inverse transformation of the above transformation.

In general, since noise tends to be superimposed on the received signal, so-called code errors occur in the above-mentioned identification process. Maximum likelihood decoding is known as an identification method that reduces code errors. The maximum likelihood decoding method for ternary signals is described by H. Kobayashi: Application of
Probabilistic Decoding to Digital Magnetic
Recording Systems: IBM Journal of
It is described in detail in Research and Development Jan., 1971, but the main points are described below.

For the ternary signals shown in (1) and (2) above, if the signal becomes +1, the next value will be 0 or -1, and if it becomes -1, the next value will be 0 or +1.
It has the property of becoming That is, there are two states: a state in which the next value is 0 or -1 (this is referred to as odd) and a state in which the next value is 0 or 1 (this is referred to as even). A value corresponding to the probability of each state is called a likelihood, and a method of selecting a higher likelihood is called a maximum likelihood decoding method. Let m _O (n) be the likelihood of state odd at time n, and let the likelihood of state even be
Let m _E (n) be the received value and y _o be the received value. If the noise follows a Gaussian distribution, m _O (n+1) = max {m _O (n), m _E (n) + y _o −0.5}
………(1) m _E (n+1)=max{m _O (n)−y _o −0.5, m _E (n)}
......(2) holds true. Here, max {A, B} means that the larger of A and B is taken.

The above formula means the following. At time n+1, the state is
In the case of odd, at time n, the state is odd and
There may be even cases. The probability of odd at time n is
If we consider that the probability of m _O (n) and even is m _E (n), the probability that the states of odd and even become odd at time n+1 are m _O (n) and m _E (n), respectively. +y _o -0.5. The reason for this is detailed in the above-mentioned document, and will not be explained here. The state is odd at time n+1
If so, it is considered that the state transition with the larger probability caused the state to become odd at time n+1. In other words, if m _O (n) > m _E (n) + y _o −0.5 in equation (1), if time n+1 is odd, time n is also odd.
In the case of m _O (n)<m _E (n)+y _o -0.5, if time n+1 is odd, time n is even.

In this way, assuming that time n+1 is odd,
odd−odd state transition (no state change), even−
It is possible to select which of the odd state transitions (with a state change) has occurred. In exactly the same way, time n
Assuming that +1 is even, m _O −y _o −0.5＞ in equation (2)
If m _E , odd−even state transition, m _O −y _o −0.5<m _E
Then, we can choose an even-even state transition. Then, the probability that time n+1 is odd is the probability of the selected state transition, and similarly, the probability that time n+1 is even is also the probability of the selected state transition, so
m _O (n+1) and m _E (n
+1) can be obtained. That is, m _O , m _E
If an appropriate initial value is given to , the likelihood of each state can be obtained using the received value at each time, and the state at each time can be
You can select the state transition (presence or absence of a state change) of the path flowing into the odd state and the state transition (presence or absence of a state change) of the path flowing into the even state.

By illustrating how the state changes at each time in this way, a diagram called a trellis diagram in FIG. 1 is obtained. There are always two lines between each time, but some are interrupted and some are continuous. The maximum likelihood decoding method is a method in which successive changes are estimated as correct state changes, and the decoded value at each time is estimated based on this state.
It is said that by using maximum likelihood decoding, for example, when the received signal-to-noise ratio is 13 dB, the bit error rate with normal decoding methods is about 10 ^-3 , but this can be improved to about 10 ^-5 . There is.

A conventionally known circuit configuration for realizing the maximum likelihood decoding method is shown in FIG. Three-value reception signal to reception terminal 1
give y _o . Memories 2 and 3 have likelihoods m _O (n) and m _E
(n) is temporarily stored. 4 and 5 are likelihood calculation circuits, m _E (n) + y _o −0.5 and m _O (n)−y _o −, respectively.
Find 0.5. Comparison circuits 6 and 7 are respectively m _O (n) and m _E
(n)+y _o -0.5, m _E (n) and m _O (n) - y _o -0.5 are determined, and the selection circuits 8 and 9 output the larger one using the comparison results. This output result is the result of equations (1) and (2).
Since they correspond to m _O (n+1) and m _E (n+1), these are stored in the memories 2 and 3 as the next likelihood.
On the other hand, the decoded value estimation circuit 10 obtains the decoded value at the output terminal 11 using the above comparison result. The details of the decoded value estimating circuit 10 are described in the above-mentioned literature, and are omitted here.

When estimating state changes using the circuit shown in FIG. 2, the following problems arise. The state change is obtained from a closed circuit using a memory, a likelihood calculation circuit, a comparison circuit, and a selection circuit. As described above, there are drawbacks such as a large number of circuits and a large circuit scale. Furthermore, since it is a closed circuit, the overall operating speed is limited by the sum of the delay times of each circuit. In other words, the large number of circuits is a factor that makes it difficult to achieve high-speed operation.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to simplify a circuit that implements a state estimator in a maximum likelihood decoder for ternary signals, reduce the overall circuit scale, and at the same time enable high-speed operation of the circuit.

[Summary of the invention]

In order to achieve the above object, the present invention is characterized in that the state estimator of the maximum likelihood decoder is implemented using the difference in likelihood between two states.

More specifically, "0 or positive, 0 or negative"
A ternary signal consisting of repeated levels of , and the above 3
A state estimator receives the likelihood difference between two states of the value signal as an input and outputs the likelihood difference after one data cycle and the presence or absence of a change in the state; A decoder is configured with a decoded value estimator that outputs a decoded value.

First, the principle of the present invention will be explained.

Subtract m _E (n) from both sides of equations (1) and (2) above.
Also, we newly set Δm(n)=m _O (n)−m _E (n) ………(3). From this, m _O (n+1)−m _E (n)=max {Δm(n), y _o −0.5}
………(4) m _E (n+1)−m _E (n)=max{Δm(n)−y _o −0.5,
0} ......(5) is obtained. Furthermore, finding the difference between equations (4) and (5), Δm(n+1)=max{Δm(n)−0.5} −max{Δm(n)−y _o −0.5,0}
......(6) is obtained.

Equation (6) has exactly the same function as Equations (1) and (2) above.
In other words, if Δm(n)>y _o −0.5, time n+
If 1 is odd, time n is also odd, and if the inequality is reversed, time n is even. Also, Δm(n)
In the case of -y _o -0.5>0, if time n+1 is even, time n is odd; if the inequality is reversed, time n is even. However, the value to be temporarily stored here is only the likelihood difference Δm(n), which is half the value conventionally required.

Furthermore, due to the magnitude relationship in { } of equation (6), 4
Although I mentioned here that two cases occur, in reality, the following three cases are sufficient. That is, [1] Δm(n)≧y _o +0.5 ………(7) [2] y _o +0.5＞Δm(n)＞y _o −0.5 ………(8) [3] Δm( n)≦y _o −0.5 ………(9) Furthermore, the following code is used to indicate the change in state.
Consider d _O (n+1) and d _E (n+1) anew. That is, d _O (n+1) = 0: Both times n and n+1 are odd d _O (n+1) = 1: Time n is even, and n+1 is odd d _E (n+1) = 0: Both times n and n+1 are even d _E (n+1) =1: time n is odd, n+1 is even Using these and equation (6), the results of the state estimator in each case can be found as follows.

[1] Δm (n+1)=y _o +0.5 ………(10) d _O (n+1)=0 ………(11) d _E (n+1)=1 ………(12) [2] Δm( n+1)=Δm(n) ………(13) d _O (n+1)=0 ………(14) d _E (n+1)=0 ………(15) [3] Δm(n+1)=y _o − 0.5 ………(16) d _O (n+1)=1 ………(17) d _E (n+1)=0 ………(18) According to the above principle of the present invention, only the likelihood difference Δm is stored. Then, the following likelihood difference and the presence or absence of a state change are automatically given by equations (10) to (18) according to the three types of cases determined by the magnitude relationship with the received value y _o .

[Embodiments of the invention]

FIG. 3 shows the configuration of a first embodiment of a maximum likelihood encoder according to the present invention. Here, the received value y _o at the input terminal 12 is converted into a binary code by the A/D converter 13 . Even if y _o is quantized to about 4 bits, the performance of the maximum likelihood decoder without quantization is significantly less degraded. Also, from equations (10), (13) and (16), it can be seen that ∆m changes in amplitude by only 1/2 of _yo , and if _yo is quantized with 4 bits, ∆m can be given with 3 bits. . 1
4' is a ROM (Read Only Memory), and uses a total of 7 bits, 4 bits of _yo and 3 bits of Δm(n), as an address input. Also, the output of ROM is Δm
3 bits of (n+1), d _O (n+1), d _E (n+1)
Each bit is 1 bit, totaling 5 bits. Also, ROM
The data for each address is (10) according to equations (7) to (9).
~(18).

.DELTA.m(n+1) is temporarily stored in a 3-bit latch 15 every data cycle, and is used as the ROM address input at the next time. A result indicating a change of state d _O
(n+1) and d _E (n+1) are output from terminals 16 and 17, and are used as inputs to a state estimator described later.

As is clear from comparing FIG. 3 with FIG. 2, the first embodiment consists only of a normal-sized ROM 3-bit latch with 7 bits for input and 5 bits for output.
The circuit scale is extremely small. Furthermore, the operating speed of the circuit is limited only by the delay of the two circuits, the ROM and the latch, and it is easy to increase the speed.

As a method for processing signals at high speed, polyphase processing can be used in which the signal is divided into a plurality of sequences and processed in parallel. In the case of maximum likelihood decoding, the likelihood is 1
This cannot be divided and processed in parallel because it is determined from the likelihood before the time and the received value. However, if the configuration of FIG. 3 of the present invention is extended, polyphase processing becomes possible.

FIG. 4 shows the configuration of another embodiment of the maximum likelihood encoder according to the present invention, which achieves high speed by two-phase processing.

If Δm(n) and y _o are given by equations (7) to (18), Δm(n
+1), d _O (n+1), d _E (n+1) are found, but using Δm (n+1) obtained here and y _o+1 obtained at the next time, Δm (n+2), d _O (n+2), d _E (n+
It is easy to understand that 2) can be obtained. Therefore,
Consider the received value y _o divided into even time y _2K and odd time y _2k+1 , give y _2k , y _2k+1 and Δm (2k), and Δm
(2k+2), d _O (2k+1), d _O (2k+2), d _E (2k+
1) You can create a table of numbers to obtain d _E (2k+2). In FIG. 4, the received value y _o applied to the input terminal 12 is binary encoded by the A/D converter 13 and serially-parallel converted using the shift register 18.
It is divided into y _2k and y _2k+1 . The ROM 14' stores the above-mentioned numerical table, with addresses Δm(2k), y _2k , and y _2k+1 , Δm(2k+2) in the latch 15, and d _O (2k+
1), d _O (2k + 2) to shift register 19, d _E
(2k+1) and d _E (2k+2) are output to the shift register 20. Since the latch 15 operates at twice the data cycle of the received value y _o , if a ROM and latch with the same speed as in Fig. 3 are used, the overall operating speed can be increased to twice that in Fig. 3. . Note that d _O (2k+
1), d _O (2k+1), d _E (2k+1), and d _E (2k+2) are parallel-serial converted in shift registers 19 and 20 to become d _O
(n+1) and d _E (n+1) are output to terminals 17 and 18, and the overall operation is as a state estimator having the same input/output relationship as in FIG. That is,
Although the configuration shown in Figure 4 requires a large-capacity ROM (assuming y _o is 4 bits, the address is 11 bits and the data output is 7 bits), it realizes an operation equivalent to two-phase processing. , the operating speed has been doubled. If a larger capacity ROM is used, 3
Phase, four-phase, etc. processing is also possible.

In FIGS. 3 and 4, an example was described in which y _o is quantized by 4 bits. If this number of bits is reduced, the required circuit scale will be further reduced, but on the other hand, the effectiveness of the maximum likelihood decoding method will be reduced due to quantization errors. Here, 3
Consider the example of bit quantization. That is, +
Levels between 1 and -1 are represented by eight representative values. For example, suitable typical values are ±1/8, ±3/8, ±5/8, and ±7/8. By the way, it can be easily imagined from the normal decoding method that uses ±0.5 as a threshold and determines the received value y _o as +1, 0, or -1, but if the received value y _o
The code error improvement by maximum likelihood decoding is large when the value is around 0.5. This is because, if there is no noise, the received value y _o has only three values, ±1 and 0. Furthermore, when the noise is small, y _o concentrates around ±1 and 0, and code errors due to noise do not occur. Also, noise so large that the received value, which should normally be 0, takes a value near +1, for example, rarely occurs.
If this occurs, even if maximum likelihood decoding is used, it will be reduced to 0.
It is difficult to judge. Therefore, normal decoding will result in a code error, but maximum likelihood decoding may correctly decode if the received value is ±
This is a case of around 0.5.

Therefore, the representative values during quantization are not taken at equal intervals as described above, but the values around ±0.5 are made finer than the others.

For example, ±3/16, ±7/16, ±9/16, ±13/16. The measurement result of the bit error rate in this case is
As shown in the figure, it can be seen that the improvement in the bit error rate is greater than when the same 8 representative values are selected at equal intervals, and the characteristic approaches that when 16 representative values are used.

The embodiment of the structure of the present invention is the same as that shown in FIG. In this case, the A/D converter uses 4 bits and _yo is 4 bits, but the ROM14
Within ±1/16, ±5/16, ±3/16, ±11/16
If we consider that ±15/16 is ±13/16 and create a numerical table, y _o will actually be equivalent to 3 bits, and Δm will be 2 bits. Therefore, the ROM address is 4 + 2 = 6 bits, and the output is 2 + (1 x 2) = 4 bits by adding d _O and d _E. Both will be 1 bit less. especially
The ROM capacity is increased by 1/2 x 4/5 = 0.4 times, so the circuit size can be reduced with less performance deterioration.

FIG. 6 shows an embodiment in which the state estimator is implemented using an analog circuit. y _o given to terminal 13 is NPN
It is connected to the base of the transistor 21, and by appropriately setting the bias, the potential of the base is selected to be y _o −0.5. When Δm(n) is connected to the base of the NPN transistor 22 and the emitters of both transistors are connected in common, the emitter has max.
{Δm(n), y _o −0.5}−ε is obtained. Here, ε is the potential difference between the base and emitter of the transistor.
On the other hand, y _o is also connected to the base of the NPN transistor 23, and the base potential is set to y _o +
Set it to 0.5. The emitter potential of transistor 23 is
y _o +0.5−ε. Furthermore, the transistor 21,
The emitter of transistor 22 is connected to the base of PNP transistor 24, the emitter of transistor 23 is connected to the base of PNP transistor 25, and transistor 2
When connecting 4 and 25 emitters, min{max{Δm(n), y _o −0.5}−ε, y _o +0.5−
ε}+ε=min{max{Δm(n), y _o −0.5}, y _o +
0.5} is obtained. Here, min{A, B} means the smaller of A and B. Above min { }
When calculated according to equations (7) to (9), we find that Δm(n+1
)
It turns out that it matches. That is, Δm(n+1) is obtained from the emitters of transistors 24 and 25. This is held in the sample value holding circuit 26 for one data period and supplied to the base of the transistor 22 as the likelihood of the next time. Note that a comparator 27 determines the magnitude of the base voltages of the transistors 21 and 22.
Then, if the comparator 28 further determines the magnitude of the base voltages of the transistors 21 and 23, d _O (n+
1), d _E (n+1) is obtained, so terminals 16,1
Output to 7. In the configuration shown in FIG. 6, two switch circuits with connected emitters and a sample value holding circuit form a closed circuit for determining the likelihood, and high speed can be easily achieved. Also, such a configuration is (3) ~
It is expressed by equation (18). This is made possible by the principles of the present invention.

In the above embodiment, from the received signal y _o , codes d _O (n+1) and d _E (n+1) indicating the presence or absence of a state change are used.
This paper describes the state estimator that obtains the state. Here, d _O
Estimation of decoded values using (n+1) and d _E (n+1) will be described. Here, an example will be taken where the original ternary signal changes to +1 and -1 each time the decoded value becomes 1, and becomes 0 when it is 0. Figure 7 shows the changes between the two states even and odd, d _O (n+1), d _E (n+1)
An example of the relationship between and decoded value is shown below. To obtain a decoded value from this, (1) Let d _O (n+1) be a temporary decoded value.

(2) However, when d _O (n+1)=1,
The previous time d _O (n+1) when the logical sum of d _O (n+1) and d _E (n+1) became 1 is inverted.

It's fine if you do this. This logical process traces back a path from the current state (time n+1) of the trellis diagram in Figure 7 toward the past, and then creates a path that does not break on the way as a state transition to a certain past point in time. This is equivalent to selecting (state transition) and using the presence or absence of the state change as the decoded value. An embodiment that realizes this is shown in FIG. Of d _O (n+1) and d _E (n+1) given to input terminals 29 and 30, d _O (n
+1) is an N-stage D-type flip-flop 31-1~
31-N. On the other hand, d _O (n+1) + d _E (n+1) obtained by the OR gate 32 is also
The delay is performed by type flip-flops 33-1 to 33-N. The position where d _O and d _O + d _E are both 1 is
is detected by AND gates 34-1 to 34-N, and _dO at that time is Exclusive OR gate 35-1 to 35-3.
5-N is inverted. This result is transferred to the flip-flops 31-2 to 31-N in the next stage, but immediately after that, a clock with one data period interval is received at the terminal 36 to drive the flip-flops 31 and 33.
The contents after 3-2 are set to 0. As a result, flip-flops 33 are all 0 or the previous d _O
Only the time when +d _E = 1 becomes 1, and d _O
= 1, the d _O at that time is inverted, and the output 3
8 as a decoded value. Note that since N is finite, when d _O = 1, the previous d _O
In some cases, the information +d _E =1 has passed through the flip-flop 33-N. In this case, the above-mentioned literature describes a method of inputting Δm(n) to the terminal 39, determining whether it is positive or negative using the comparator 40, and estimating the state with a high likelihood as the current state.
This effect is not directly related to the present invention and will therefore be omitted.

Above, an example was shown in which a ternary signal is obtained as a received signal. However, even if the received signal is a binary signal, by converting it into a ternary signal and then performing maximum likelihood decoding, it may be possible to improve the bit error rate of decoding the binary signal as it is.

As a method of converting a binary signal to a ternary signal, 2
There is a method of delaying the value signal for a certain period of time and adding or subtracting it from the original binary signal.

For example, consider an FM signal as a binary signal.
An FM signal is such that, for example, the level always changes at a data change point, and even at the center of the data when the data is 0. Further, consider 1/2 of the data cycle T as the above-mentioned fixed time. The original data at this time, the FM signal and the T/2 delayed
The sum with the FM signal is shown in Figure 9 a, b, and c. As is clear from c, a ternary signal is obtained that changes by ±1 every time the original data becomes 1, and becomes 0 when the original data is 0. Instead of directly decoding b, c is It is possible to decode using the maximum likelihood decoder of the present invention.

Further, as the next example, an NRZ binary signal will be considered, and the data period T will be considered as a constant delay time. At this time, the original NRZ signal and the T-delayed
The difference in NRZ signals is shown in Figures 9d and e. As is clear from e, a ternary signal is obtained which changes by ±1 every time the original data changes from 0 to 1 or from 1 to 0, and becomes 0 otherwise, using the maximum likelihood decoder of the present invention. can be decrypted. However, the relationship between e and a is
Since the relationship between c and a is slightly different, in e, by integrating the code after decoding in the decoding estimator shown in FIG.
The sign of is obtained.

In addition, as binary signals, Modified FM,
The present invention can be applied to many codes such as a code called Miller Square.

Note that adding and subtracting the signal with the original signal after delaying the signal by a certain time τ means sinωt+sinω(t-τ)=2cosωτ/2sinω(
t−τ/2)……(19) sinωt−sinω(t−τ)=2sinωτ/2cosω(
t-τ/2)...(20) As is clear from the relationship, this is equivalent to applying a 2cosωτ/2 or 2siinωτ/2 filter to the original signal. This filter operation changes the frequency distribution of noise contained in the original signal, and the total noise power may increase or decrease. If noise increases due to filter operation, the effect of ternarization and maximum likelihood decoding will be lost, but if the original signal has a lot of noise at high frequencies, a filter with a characteristic of 2cosωτ/2 will reduce the noise. The filter operation is performed by adding the original signal and the delayed signal, or by subtracting the original signal and the delayed signal, since the noise in the original signal is often reduced at low frequencies by a filter with a characteristic of 2sinωτ/2. 3 without increasing noise due to
It can be converted into a value, and the effect of maximum likelihood decoding can be demonstrated. In this way, which addition or subtraction to select or what to use as the delay time τ can be determined so that the increase in noise due to addition and subtraction is minimized, or so that the noise is reduced due to addition and subtraction.

〔Effect of the invention〕

As described above, in the present invention, in the state estimation section of a decoder that performs maximum likelihood decoding of a ternary signal, four operations, which conventionally required likelihood calculation, comparison, selection, and temporary storage, are now performed. By using the likelihood difference between the two states, it became possible to realize the first three operations at once. This not only reduces the overall circuit scale, but also makes it possible to improve the operating speed, which was previously limited by the total delay time of the four operations. Furthermore, parallel processing through multi-phase processing, which was previously impossible, has become possible, and this has also led to further improvements in operating speed. Also, 3
When quantizing value signals, it has become possible to further reduce the circuit scale by performing quantization at non-uniform intervals.
As a result, although this is a decoding method that is effective in improving the bit error rate, it has become possible to solve the problems of maximum likelihood decoders, which had a complex circuit scale and were considered difficult to operate at high speed.

Furthermore, by converting it into a ternary signal before decoding, it can now be used in the present invention.

[Brief explanation of drawings]

Fig. 1 is a trellis diagram showing state changes of a ternary signal, Fig. 2 is a diagram showing the configuration of a conventional maximum likelihood decoder,
FIG. 3, FIG. 4, FIG. 6, and FIG. 8 are all configuration diagrams of embodiments of the maximum likelihood decoder according to the present invention, and FIG. 5 is an actual measurement example of the effect of the present invention on the code error rate.
FIGS. 7 and 9 are diagrams showing signal changes according to the present invention. 1, 12, 13, 29, 30, 36, 39...input terminal, 11, 16, 17, 38...output terminal, 2
3...Memory, 4,5...Likelihood calculation circuit, 6,7,2
7, 28, 40... Comparison circuit, 8, 9... Selection circuit,
10...Decoded value estimator, 13...A/D converter, 1
4, 14'...ROM, 15...Latch, 18...Serial-parallel converter, 19,20...Parallel-serial converter, 21,2
2, 23, 24, 25...transistor, 26...sample value holding circuit, 31, 33, 41...D flip-flop, 32...OR gate, 34...AND gate, 35...exclusive OR gate, 37...NAND gate.

Claims (1)

[Claims] 1. A code signal encoded into three values of positive level, zero level, and negative level according to a specific encoding rule, and the positive level and negative level appear alternately with each other. In a maximum likelihood decoder that decodes a code signal in which a first state in which the next state is a zero level or a negative level and a second state in which the next state is a zero level or a positive level occur alternately. , the likelihood difference between the likelihood of the first state and the likelihood of the second state, and the received value of the code signal are input, and the value obtained by adding or subtracting a predetermined number to the received value is calculated. Based on the size relationship, the likelihood difference after one data period and 1
a state estimation unit that selects and outputs first and second codes respectively indicating the presence or absence of a state change of a path flowing into a first and second state after a data period; a storage means for temporarily storing the output likelihood difference for the next state estimation; and a storage means for sequentially inputting the first and second codes output from the state estimating section, and at least one of them for a predetermined number of data. The current first,
a decoded value estimation unit that performs logical processing equivalent to tracing back the maximum likelihood path by the number of data points from one of the second states, and outputs the presence or absence of a state change at the time of tracing back the number of data points. A maximum likelihood decoder characterized by: 2 The state estimating unit includes an AD converter that converts the received value of the code signal into a digital signal, an output of the holding means obtained as a digital signal, and the output of the holding means obtained as a digital signal.
The maximum likelihood decoder according to claim 1, further comprising a memory for reading out the likelihood difference and the first and second codes stored as a numerical table using the output of the AD converter as an address. 3 The state estimating unit includes an AD converter that converts the received value of the code signal into a digital signal, a shift register that converts the output of the AD converter at an even number time and the output at an odd number time into parallel outputs, and the above-mentioned. A memory for reading out the first and second codes of the likelihood difference stored as a numerical table and the above for two times, using the parallel output of the shift register and the output of the holding means obtained as a digital signal as an address. The maximum likelihood decoder according to claim 1, further comprising: means for parallel-to-serial transformation of the read first code for two times and second code for two times and outputting the parallel-to-serial transform. 4. Claim 2, wherein the AD converter converts a signal level near a threshold between three values of the code signal into a digital signal using a finer quantization step than other signal levels. Maximum likelihood decoder as described in Section. 5 The state estimator receives the received value of the code signal and the output of the holding means as base inputs, and receives the signal from the two NPN transistors whose emitters are commonly connected, the signal from the common connection node of the emitters of the NPN transistors, and the signal from the common connection node of the emitters of the NPN transistors. 2. Two PNP transistors each having a received value of a code signal as a base input, emitters connected in common, and an output of the emitters as a likelihood difference after one data period. Maximum likelihood decoder. 6. Claim 1, wherein the ternary code signal is a code signal synthesized from the sum or difference of a binary code sequence and a sequence obtained by delaying the binary code sequence for a certain period of time. Maximum likelihood decoder as described in Section.