JPH0548663B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to, for example, a CCD solid-state imaging device,
The present invention relates to a charge detection circuit that detects photoelectrically converted signal charges and extracts them as output signals.

[Conventional technology]

For example, in a solid-state imaging device using a CCD,
In general, the photoelectrically converted signal charge is detected and extracted as an output signal as follows.

That is, FIG. 4 shows an example of an output extraction circuit of a CCD solid-state imaging device.
This is an example in which the operation method of the image sensor is a frame transfer method, and the decimal carrier stored as information is an electron. In the figure, the part to the left of the broken line is the CCD device side.
The right part is a sampling hold circuit as a waveform shaping circuit.

In the figure, 1 indicates the configuration of the imaging device, and 1a is the output end of the output extraction circuit.

2 is a photosensitive area of the CCD imaging device 1;
3 indicates its storage region, 4 indicates a read register, and 5 indicates an output gate and a reverse biased output diode portion.

The signal charge generated in the photosensitive area 2 is transferred to the accumulation area 3.
At the same time, the next photoelectric conversion operation is performed in the photosensitive area 2. The signal charges temporarily accumulated in the accumulation region 3 are transferred to the readout register 4 for each horizontal column, and are transferred to the output gate and output diode portion 5.
are retrieved in chronological order via .

And output gate and output diode part 5
The output terminal of is grounded via a capacitor 6 and connected to the source of FET 7, the drain of FET 7 is supplied with DC voltage _ER , and the gate is supplied with a preset pulse Pa synchronized with the transfer clock of readout register 4. (FIG. 5A) is supplied.

Further, the connection point between portion 5 and capacitor 6 constitutes a buffer amplifier for impedance conversion.
It is connected to the gate of FET8, the drain of this FET8 is supplied with DC voltage E, and the source is connected to output terminal 1a.

In such a circuit, during the period T _P when the pulse Pa is at a high level, FET7 is turned on,
The capacitor 6 is charged and preset (hereinafter referred to as precharged) to a voltage E _R. Then, when the period T _S in which the pulse Pa is at a low level, the FET
7 is turned off, and the voltage across the capacitor 6 decreases in accordance with the output signal charge. Therefore, the voltage E _R
When the reference level is set as the reference level, the voltage across the capacitor 6 during the period T _S becomes the signal level.

Here, since the pulse Pa is synchronized with the transfer clock of the readout register 4, the charge detection output voltage V _O repeats the reference level and signal level for every one stage of the readout register 4, that is, every one bit.
will appear across the capacitor 6. And this is the FET8 that makes up the buffer amplifier.
It is led out to the output end 1a through.

In this case, in reality, the pulse Pa jumps into the signal path through the stray capacitance between the gate and source of the FET 7, so the output voltage V _O appearing at the output terminal 1a is affected by this jump, as shown in FIG. 5B. voltage E _P is superimposed. However, since this jump voltage E _P is almost constant, this voltage
There is no problem in considering the signal level using a voltage higher by E _P as the reference level, so in reality, there is no harm in considering the voltage E _R +E _P higher by this voltage E _P as the reference level.

The output V _O taken out to the output terminal 1a in this way is used for sampling by the sampling hold circuit 10.
Supplied to the drain of FET11. This FET1
A sampling pulse Pb (Fig. 5C) that becomes high level during the period T _S of the signal level of the output V _O is supplied to the gate of No.
The FET 11 is turned on and the signal level of the output V _O is sampled. Then, the hold capacitor 12 is charged or discharged to this sampled signal level, and the signal level is held in this capacitor 12. This hold voltage
V _H is taken out through FET 13 that constitutes a buffer amplifier. In addition, 9 is the load resistance of FET8,
14 is a load resistance of FET13.

By the way, as mentioned above, in order to convert the charge accumulated in the CCD solid-state imaging device into voltage and take it out, it is necessary to precharge the capacitor 6 for each bit if the decimal carrier is an electron. be.

However, during this pre-charge operation, the FET
Noises such as internal noise of FET 7 and power supply noise of this FET 7 occur, and the reference precharge level fluctuates due to this noise. The noise level N generated during this precharge period T _P is the capacitor 6
It is held during one bit period τ _B =T _P + _TS by .
In other words, the noise is output in a sampled and held manner.

Therefore, due to this noise, the output voltage V _O
As shown by the broken line in Figure B, the signal level during the period T _S also fluctuates. Therefore, if the signal level portion of the output V _O is simply sampled and held as in the circuit example of FIG. 4, there is a problem that the signal component S mixed with the noise component N is extracted.

An invention for effectively eliminating noise during the precharge operation was previously proposed by the present applicant in Japanese Patent Application No. 1985-1985. This invention takes advantage of the fact that the noise level is constant during one bit period τ _B , and in principle there should be no signal component during the precharge period _TP , as shown in FIG. 5B. Within the 1-bit interval τ _B , the time point
The difference is calculated between the precharge level at _P1 and the signal level at time _P2 . That is,
Now set the correct noiseless precharge level to 0.
Then, the level at time P ₁ is due to the noise component, and the level at time P ₂ is the sum of the signal component and the noise component, so if we take the difference between the two, the noise component is removed and only the signal component is obtained. It is something that can be done.

[Problem that the invention seeks to solve]

The above invention is based on the premise that the precharge level is not affected by the signal level at all, but in practice there are the following problems.

That is, if the buffer amplifier made up of the FET 8 has a wide band compared to the signal frequency and has good frequency characteristics, the above premise can be established.

However, the signal frequency obtained at the output terminal 1a is a signal of about 10 MHz, and a broadband buffer amplifier that covers a band of 100 MHz, which is 10 times that frequency, with good frequency characteristics is required.

However, it is difficult to construct such a buffer amplifier, and the current situation is that a buffer amplifier with poor frequency characteristics must be used.

If a buffer amplifier with such poor frequency characteristics is used, the output V _O will have an output signal waveform as shown in Figure 5D because the level of the precharge period T _P will be affected by the signal output level of the previous bit. .

In this case, the signal output according to the previous invention
In V _O , the signal component of each bit is affected by the signal of the previous bit. In the case of a CCD color solid-state imaging device, a point-sequential color filter is used, and the color component usually differs for each bit. Therefore, as mentioned above, being affected by the signal component of one bit before causes color mixture, which causes the problem that the colors appear muddy on the playback screen.

The present invention is intended to provide an output buffer amplifier for a CCD imager that does not cause the above-mentioned color mixture even when an output buffer amplifier having poor frequency characteristics is used.

[Means for solving problems]

In this invention, as shown in FIG. 5D,
The signal level of a certain bit (time point _P2 ) and the precharge level of the next bit (time point P2)
P ₃ ) is calculated and used as an output signal.

[Effect]

The level at time P ₂ includes the signal component and the nozzle component, while the level at time P ₃ is
It is the sum of the reference level including the influence of the signal component at time P ₂ and the noise component. Therefore, considering that the change in noise is sufficiently larger than the bit period, the noise component is removed from the output, and even if there is an effect from the signal component, it is the effect of the 1-bit signal itself. Therefore, there is no risk of color mixing.

〔Example〕

FIG. 1 shows an embodiment of the present invention, in which the output V _O obtained at the terminal 1a (FIG. 2A) is output to a sampling hold circuit 2 as a signal level detection circuit.
1. On the other hand, this sampling and holding circuit 21 is supplied with a sampling pulse SP ₁ ( _B in the same figure) having a period τ _B and a phase at the end of the period T _S in each 1-bit period τ B, and outputs V _O The signal level portion of is sampled and held. output
V _O is also supplied to a sampling hold circuit 22 as a reference level detection circuit. This sampling hold circuit 22 has a period τ _B ,
A sampling pulse SP ₂ (C in the same figure) having a phase within the precharge period _TP in each 1-bit period τ _B is supplied, and the precharge level of the output V _O is sampled and held. Then, the hold output of the sampling hold circuit 21 is delayed by a time τ corresponding to the phase difference between the pulse SP ₁ and the pulse SP ₂ in the delay circuit 23 and is supplied to one input terminal of the comparison circuit 24 as a difference forming circuit. At the same time, the hold output from the sampling and holding circuit 22 is supplied as is to the other input terminal of the comparison circuit 24. Therefore, as shown in FIG. 2, in this comparator circuit 24, for example, the signal level in one bit period τ _B1 is compared with the precharge level in the next one bit period τ _B2 , and the difference between the two is calculated. The output is obtained as a charge detection signal output. That is, in this case, even if the precharge level is affected by the signal level of the previous bit due to the poor frequency characteristics of the output buffer amplifier, the next 1-bit period τ _B2 is affected by the signal level of the 1-bit period τ _B1. Since the difference between the precharge level and the signal level of one bit period τ _B1 is extracted as an output, the output is not affected by the signal of the previous bit. Furthermore, the influence of noise during pre-charging can be effectively eliminated using the same principle as the previously proposed invention.

FIG. 3 shows another embodiment of the present invention, in which a sampling and holding circuit 25 is used instead of the delay circuit 23 to perform a signal delay operation.

That is, the output of the sampling and holding circuit 21 is supplied to the comparison circuit 24 via the sampling and holding circuit 25, and the sampling pulse SP ₂ that is supplied to the sampling and holding circuit 22 is supplied to the sampling and holding circuit 25.

〔Effect of the invention〕

In this invention, in order to remove precharge noise, the difference between the precharge level part and the signal level part is obtained as a signal output. Rather than taking the difference between the two bits, the signal output of a certain bit is
Since it is obtained as the difference between the signal level of that bit and the precharge level part of the next bit, even if the frequency characteristics of the output buffer amplifier of the CCD imaging device are poor, the signal output of each bit is equal to that of the previous bit. You can get something that is not affected by the signal. Therefore, there is no risk of color mixture occurring in the CCD color solid-state imaging device.

[Brief explanation of the drawing]

Fig. 1 is a system diagram of an embodiment of the present invention, Fig. 2 is a diagram for explaining the same, Fig. 3 is a system diagram of another embodiment of the invention, and Fig. 4 is a system diagram of an example of a conventional circuit. FIG. 5 is a diagram for explaining the same. 1 is a CCD image sensor, 8 is an FET as an output buffer amplifier, 21 and 22 are sampling and hold circuits, and 24 is a comparison circuit for obtaining a subtracted output.

Claims (1)

[Claims] 1. In a charge detection circuit comprising a CCD device and a waveform shaping circuit connected to the output side of the CCD device, the CCD device converts the output from the CCD charge transfer element into a predetermined voltage for each bit. A charge detection signal is generated by repeating a reference level section preset to a reference level section and a signal level section formed by charging or discharging from the predetermined voltage according to the output charge, and this charge detection signal is passed through a buffer amplifier for impedance conversion. The waveform shaping circuit includes a signal level detection circuit that detects the level of the signal level part of a certain bit of the charge detection signal from the buffer amplifier, and a reference level part of the bit next to the certain bit. A charge detection circuit comprising: a reference level detection circuit for detecting the level of the signal level portion; and a difference forming circuit for calculating the difference between the detected level of the signal level portion and the reference level portion.