JPH0550760B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to an audio signal detection circuit, particularly a circuit that determines the presence or absence of an audio signal input used in an input device of an audio processing device, and which reacts to ambient noise. The present invention relates to an audio signal detection circuit that prevents this from occurring.

(Prior Art) Input devices for audio processing systems that are equipped with circuits that automatically operate upon detecting the presence or absence of audio signal input or are useful for data reduction have come into use. Further, in the above-mentioned input device, an A/D converter that converts an analog signal whose amplitude changes continuously into a discrete digital signal and outputs the signal is often used.

FIG. 2 shows an example of a conventional audio signal detection circuit.
FIG. 3 is an explanatory diagram of the operation of the circuit shown in FIG. 2.

Audio input is converted into an electrical signal by a microphone 1, and this signal is input to an n-bit A/D converter 4 via an analog amplifier 2 and a low pass filter 3 (hereinafter referred to as LPF). The input signal is converted into an analog signal in the n-bit A/D converter 4.
Digital conversion is performed and an n-bit digital signal is output. This n-bit digital signal is input to the comparator 5 (in addition to being processed by the main unit). A comparison level is preset in the comparator 5 as a digital value, and when the n-bit digital signal exceeds this comparison level, a "1" level is outputted and supplied to the detector 6. The detector 6 is composed of an RS flip-flop and an m-bit counter, and when the comparator 5 outputs a "1" level, the RS flip-flop is set and the voice detection output becomes "1", and the m-bit counter is reset. When the comparator 5 outputs the "0" level, the reset of the m-bit counter is released and counting starts. After a time determined by the clock frequency and the number of bits, the counter output is output and the RS
The flip-flop is reset and the voice detection output becomes "0". The clock frequency and the number m of bits of the counter are set so that the reset signal of the RS flip-flop is delayed to such an extent that the voice detection output does not become "0" while voice is being input.
When the audio detection signal is “0”, there is “no audio input”,
When it is "1", it indicates "audio input is present".
For the voice input A as shown in FIG. 3, the voice detection signal becomes like C shown in FIG. At that time, the output of the comparator 5 becomes as shown in B shown in FIG.

(Problems to be Solved by the Invention) In the conventional voice detection circuit described above, a comparison level is set in the comparator 5 in advance, but if this comparison level is small, it is likely to malfunction due to noise, and if the comparison level is large, the voice signal will not be detected. There was a problem that the detection ability of

Furthermore, the center of the waveform of the LPF 3 shown in Fig. 2 is normally set to the center of the dynamic range of the A/D converter 4, but if it deviates from this, an error will occur in the comparison level of the above setting by the offset, so it must be strictly This method has the disadvantage that a large amount of offset adjustment is required.

In addition, when an impulse noise like D shown in FIG. 3 is input to the input signal, a comparator output like E shown in FIG.
There was also a drawback that the audio signal was output in response to impulse noise, as shown in F shown in the figure.

In addition, when a long-term noise such as the commercial power frequency is input, the comparator output and voice detection output, such as G shown in Figure 3, respond to It also had the disadvantage of causing malfunctions.

An object of the present invention is to solve the above-mentioned drawbacks and to enable audio signal detection in an environment where the S/N ratio cannot be very large.

(Means for Solving the Problems) Therefore, the audio signal detection circuit of the present invention includes an A/D conversion means that converts an input analog audio signal into a digital audio signal, and a digital audio signal that converts the digital audio signal into a digital audio signal at a predetermined sampling period. a delay means for outputting the digital audio signal after delaying the delay time; a subtracting means for subtracting the digital audio signal outputted from the delaying means and the digital audio signal outputted from the A/D conversion means and outputting a difference; an absolute value calculation means for calculating the absolute value of the difference and outputting it as audio information, and comparing the output of the absolute value calculation means with a predetermined comparison level,
Comparing means for selectively outputting a first signal level and a second signal level according to the comparison result; an integrator that counts down to update the count value when the signal level is 2 and outputs the updated count value, and outputs a voice detection signal when the count value exceeds a predetermined count value. The present invention is characterized in that it includes a detection means for detecting.

(Function) With the audio signal detection circuit having such a configuration, it is possible to detect an audio signal that has excellent discrimination between audio signals and noise and does not react to impulsive noise and long-period noise.

(Embodiment) FIG. 1 is an embodiment of the present invention, and FIGS. 4, 5, and 6 are explanatory diagrams of input signals and output signals. In Figure 1, 7 is a microphone, 8 is an analog amplifier (AMP), 9 is an LPF, and 10 is an n-bit A/
11 is a delay device, 12 is a subtracter, 13 is a circuit for converting to an absolute value, 14 is a comparator, 15 is an integrator, and 16 is a detector.

The audio input is converted into an electrical signal by the microphone 7 and input to the analog amplifier 8 . After high frequency components are removed from the output of the analog amplifier 8 by the LPF 9, it is input to an n-bit A/D converter 10 and converted into an n-bit digital signal. When an n-bit digital signal is obtained by the l-th sampling, and the n-bit digital code is expressed as PCM _l , the delay unit 11 delays the signal by one sampling period inputted to PCM _l . The output will be PCM _l-1 . When these PCM _l and PCM _l-1 are input to the subtractor 12, the difference d _l is obtained as d _l = (PCM _l
−PCM _l-1 ). Although d _l takes both positive and negative values, it is converted into an absolute value via the absolute value circuit 13 and output as |d _l |. |d _l | is a quantity representing the magnitude of change in the input waveform. This |d _l | is input to the comparator 14. The other comparison level is preset in the comparator 14, and when |d _l | is greater than this comparison level, it outputs the "1" level, and when it is below the comparison level, it outputs the "0" level. The output of this comparator 14 is input to an integrator 15. The integrator 15 has an up-down counter (hereinafter referred to as U/D counter) and two 3-input AND
The circuit consists of one two-input OR circuit and a detector that detects that the count content of the U/D counter is 0, for example, 30. In this case, the above U/D counter is 0 to 30.
An up or down count is performed in between, but this range may be adjusted depending on the S/N ratio environment in which the microphone 7 is placed. In this embodiment, the explanation will be continued in the case of 30 instead of 0.

The output of the comparator 14 is the U/D counter U/
At the same time as being input to the D selection terminal, one of the three inputs
Input to AND circuit. The remaining two inputs of this 3-input AND circuit are the negative phase signal of the 30 detector output, which outputs "1" when the count content of the U/D counter reaches 30, and
These three inputs are the signals that output the clock.
The output of the AND circuit is input to one input terminal of the two-input ORD circuit.

The output of the two-input OR circuit serves as the clock input of the U/D counter.

With this configuration, the U/D counter starts counting when the comparator output is at the "1" level and the output from the 30 detection circuit is at the "0" level, that is, when the count content of the U/D counter is not 30. Only 2 is counted in count mode. When the count reaches 30 in the middle of counting, no clock is output from one of the three-input AND circuits, and the count does not increase.

When the comparator output is "0", the count mode of the U/D counter is set to down. Also, the opposite phase of the above comparator output is the other 3 input AND
The remaining two input signals of the 3-input AND circuit are connected to one input terminal of the circuit and have the opposite phase of the 0 detector output which outputs "1" when the count content of the U/D counter becomes 0. signal and a clock signal that outputs one clock within one sampling cycle, and the output of the three-input AND circuit is the two-input OR circuit.
It is input to the other input terminal of the circuit. 2 inputs
As mentioned above, the output of the OR circuit is connected to the clock input terminal of the U/D counter. With this configuration, the U/D counter counts when the comparator output is at the "0" level and the output from the "0" detection circuit is at the "0" level, that is, when the count content of the U/D counter is not 0. is counted by 1 in down mode, and when the count content is 0, the other 3 inputs AND
The circuit does not output a clock and does not count down.

Now, the detector 16 determines whether or not there is an audio signal. The detector 16 consists of an RS flip-flop consisting of two 2-input NOR circuits and two
and a count content detection circuit of the U/D counter. The U/D counter output is input to the two detection circuits, each of which has a different detection level. In this embodiment, the detection circuit inputting the output to the reset side of the RS flip-flop is a detection circuit for detecting 10, and the detection circuit inputting the output to the set side is a detection circuit for detecting 20. By setting the detected value on the set side to be slightly larger than the detected value on the reset side in this way, it is possible to add hysteresis to the detection of the presence or absence of an audio signal by the U/D count, and the sensitivity of the detector becomes oversensitive. You can prevent what will happen.

FIG. 4 is a diagram showing the operation when an audio signal is input.

For an audio input J, the output of the n-bit A/D converter 10 becomes K. The output of the n-bit A/D converter 10 is an n-bit digital signal output that outputs n binary signals in one sampling. It is expressed as a waveform output through the The absolute value of the step of this K step-like waveform corresponds to the above |d _l |.
When this |d _l | becomes larger than the comparison level in the comparator 14, the output of the comparator 14 becomes the "1" level and becomes the output indicated by L. The integrator 15 operates in response to the comparison output of L, and the count content of the U/D counter, which is a component of the integrator 15, has a waveform shown by M. In this case, the bottom level of the waveform indicates 0 and counts up to 30.

The outputs of the two detection circuits of the detector 16, in this example the 20 detection circuit and the 10 detection circuit, have waveforms shown at N and O, respectively.

As a result, the output of the detection 16 becomes P and is output as the audio signal detection output.

FIG. 5 shows the operation of the circuit of this embodiment when impulse noise is input.

In the figure, Q is an impulse noise input, and then the n-bit digital signal output is as shown in R. The output of the comparator 14 becomes S, and the U/D of the integrator 15
The count contents of the counter are as shown in T. As is clear from T, the count content does not exceed 20 and the voice detection output remains at "0", indicating that it does not respond to impulse noise.

FIG. 6 is an explanatory diagram of the operation when long-period noise U is input to the circuit of this embodiment.

V indicates the n-bit digital output at that time, and |d _l | is extremely small. Therefore, the comparison output W does not exceed the comparison level of the comparator 14.
remains at the "0" level. Therefore, the U/D counter holds 0, and the voice detection output holds "0", that is, a silent output. Thus, it can be seen that the circuit shown in FIG. 1 according to the embodiment of the present invention does not react even to long period noise. Furthermore, as is clear from the circuit shown in _FIG .
It can be seen that even if there is an offset error between the analog system and digital system of the D converter 10, the offset is removed by the calculation of _dl , and a stable audio signal can be detected.

Furthermore, in the circuit of this embodiment, since the audio signal is detected via the output of the integrator 15, the audio detection signal has a phase lag compared to the actual audio signal input.
At this time, the counting method of the U/D counter used in the integrator 15 is 2 counts when up and 1 count when down, so the phase delay when the audio signal starts is the same as when the audio signal ends. This is smaller than the phase delay when Therefore n
By inputting the bit digital signal output to a delay device that provides a phase delay therebetween and using the output as the digital output of the audio signal, a voice detection signal that stably includes the input audio signal can be obtained as a result.

(Effects of the Invention) As described above in detail, the audio signal detection circuit according to the present invention has excellent discrimination between audio signals and noise, and can detect audio signals that do not react to impulsive noise and long-period noise. Detection can be performed.
Therefore, the various drawbacks of the prior art described above can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an audio signal detection circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional audio signal detection circuit, FIG. 3 is an explanatory diagram of the operation of a conventional audio signal detection circuit, and FIG. 5 and 6 are explanatory diagrams of the operation of the audio signal detection circuit of the present invention. 1, 7... Microphone, 2, 8... Analog amplifier, 3, 9... LPF, 4, 10... n-bit A/D converter, 5, 14... Comparator, 6, 16...
...Detector, 11...Delay device, 12...Subtractor, 1
3... Absolute value circuit, 15... Integrator.

Claims (1)

[Scope of Claims] 1. A/D conversion means for converting an input analog audio signal into a digital audio signal; a delay means for delaying the digital audio signal by a predetermined sampling period and outputting the delayed signal; and the delaying means. subtracting means for subtracting the digital audio signal output from the A/D converting means and the digital audio signal output from the A/D converting means and outputting a difference; and calculating the absolute value of the difference and outputting it as audio information. Absolute value calculating means; Comparing means for comparing the output of the absolute value calculating means with a predetermined comparison level and selectively outputting a first signal level and a second signal level according to the comparison result; an integrating means for updating the count value by up-counting when the signal level is a first signal level and down-counting when the signal level is a second signal level according to the output of the comparing means, and outputting the updated count value; An audio signal detection circuit comprising: a detection means for outputting an audio detection signal when the count value exceeds a predetermined count value.