JPH0550834U - Micro variable delay circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] High delay accuracy is obtained and stable against temperature changes. [Structure] The delay stages 21 _{1 to} 21 _n are connected in cascade,
Each delay stage outputs the signal from the preceding stage to the latter stage as a logical level by the buffer 22, the input side of the buffer 22 is grounded through a series circuit of a plurality of MOS switches 23 ₁ to 23 _m , and its adjacent MOS switches. The connection is also grounded. The load capacity when the MOS switches are turned on hangs down to the input side of the buffer 22 by the number of times the buffers 22 in the MOS switches 23 ₁ to 23 _m are turned on. The amount of output delay becomes large.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to, for example, a minute variable delay circuit capable of giving a minute delay of the order of nS or μS and changing the amount of the delay.

[0002]

[Prior Art]

FIG. 3 shows a conventional minute variable delay circuit. A plurality of delay stages 11 _{1 to} 11 _n are cascade-connected, and each of the delay stages 11 _i (i = 1, 2, ... N) is branched into a path 12 directly passing an input signal and a path passing through a delay element 13. Then, the multiplexer 14 selects one of the outputs and outputs it.

Depending on the control state of each multiplexer 14 in the delay stages 11 _{1 to} 11 _n , various paths are provided between the input terminal 15 and the output terminal 16 of this variable delay circuit, so that the input terminal 15 is The input signals have different delay amounts obtained at the output terminal 16. The control circuit 17 controls the multiplexer 14 of each delay stage 11 _i from the plurality of paths according to the target delay amount to obtain the target delay amount.

The delay element 13 is generally formed by a gate array by using a propagation delay T _pd that a signal passes through a gate.

[0005]

[Problems to be solved by the device]

The conventional minute variable delay circuit is made of a gate array and uses its propagation delay T _pd , but it is difficult to adjust this delay amount, and due to changes in ambient temperature, fluctuations in power supply voltage, etc. Since the propagation delay T _pd fluctuates, it is difficult to reduce the change step amount of the delay amount to, for example, about 20 pS. could not . Further, since many unnecessary paths are provided and a delay occurs in each multiplexer 14, the higher the precision, the longer the fixed delay portion.

[0006]

[Means for Solving the Problems]

 According to this invention, the input side of the buffer that outputs a logic level is grounded through a plurality of MOS switches, and the number of the plurality of MOS switches to be turned on is changed according to the set delay amount.

[0007]

【Example】

FIG. 1A shows an embodiment of this invention. In this example, a plurality of delay stages 21 _{1 to} 21 _n are connected in series between the input terminal 15 and the output terminal 16. Each delay stage 21 _i (i = 1, 2, ... N) is provided with a buffer 22 which receives a signal from the preceding stage and outputs it at a logical level to the latter stage, and the input side of the buffer 22 is a plurality of MOS switches. It is grounded through 23 ₁ to 23 _m . In this example, the MOS switches 23 ₁ to 23 _m are connected in series, one end of which is connected to the input side of the buffer 22, the other end is grounded, and the connection point of each adjacent MOS switch 23 is grounded.

Each of the MOS switches 23 ₁ to 23 _m of each delay stage 21 _i is individually on / off controlled by the control circuit 24, and the number of MOS switches to be turned on is set according to the set delay amount. When, for example, only the MOS switches 23 ₁ and 23 ₂ are turned on and the other MOS switches are turned off in the delay stage 21 ₁ , the load capacitances when the MOS switches 23 ₁ and 23 ₂ are turned on are C _1n and C ₂ respectively. _2n, the load capacitance C _3f when MOS switch 23 ₃ off, MOS switches 23 _1, 23 each gate input load capacity of ₂ C _{1 g,} C _{2 g} If you equivalent circuit is as shown in Figure 2A. Here, C _3f <C _1n , C _2n , C _1g , C _2g . In this way, the input side of the buffer 22 is grounded through the parallel connection of the capacitors C _1n , C _2n , C _1g , C _2g and C _f .

Therefore, as shown in FIG. 1B, the input signal 25 input to the delay stage 21 ₁ has a dotted line 2 due to the capacitances C _1n , C _2n , C _1g , C _2g and C _f hung on the input side of the buffer 22. As shown in FIG. 6, the rising and falling edges are gentle, and the output signal of the buffer 22 is as shown by the dotted line 27. On the other hand, when the MOS switch 23 ₁ is off and the other MOS switches are off or on, the equivalent circuit of the delay stage 21 ₁ is the MOS switch 23 ₁ on the input side of the buffer 22 as shown in FIG. 2B. Since only the load capacitance C _1f at the time of off is hung and this capacitance C _1f is small, the rounding of the waveform of the input signal 25 due to this is very small, and the output signal is the solid line 28 in FIG. 1B. Like The output of the solid line 28 has the minimum delay with respect to the input signal 25, and the output of the dotted line 27 is delayed from the output of the solid line 28 by Δt.

When the MOS switches 23 ₁ and 23 ₃ are on, the MOS switch 23 ₂ is off, and the other MOS switches are on or off, the load capacitance C _1n when the MOS switch 23 ₁ is on, as shown in FIG. 2C. The gate input load capacitance C _1g and the load capacitance C _2f when the MOS switch 23 ₂ is off are _hung in the buffer 22. The delay of the output signal at this time is larger than the output of the solid line 28 in FIG. 1B and smaller than the output of the dotted line 27.

As described above, as the number of turning on the MOS switches 23 ₁ to 23 _m from the buffer 22 side increases, the delay amount of the output signal in the delay stage 21 _{1 with} respect to the input signal increases. The other delay stages 21 _{2 to} 21 _n operate similarly. Therefore, various delay amounts can be obtained between the input terminal 15 and the output terminal 16 by selectively controlling the MOS switches 23 ₁ to 23 _m of the delay stages 21 _{1 to} 21 _n by the control circuit 24. .

[0012]

[Effect of the device]

 As described above, according to the present invention, the delay amount is controlled by the number of the on-load capacitances of the MOS switches hanging at the input of the buffer 22, so that the delay circuit is composed of the same devices as the conventional delay circuit. In this case, the delay step can be set to about 20 pS in the present invention, whereas the delay step can be set to about 100 pS in the related art, and a highly accurate delay can be performed.

Since the load capacitance of the MOS switch fluctuates due to temperature change by two digits or more than the temperature fluctuation of the gate propagation delay T _pd , the set delay amount is unlikely to be affected by temperature fluctuation. In this device, the fixed delay is almost zero because the passage is not switched.

[Brief description of drawings]

FIG. 1A is a circuit diagram showing an embodiment of the present invention, and B is a waveform diagram for explaining the operation thereof.

FIG. 2 is a diagram showing an equivalent circuit for explaining the operation of FIG. 1A.

FIG. 3 is a block diagram showing a conventional minute variable delay circuit.

Claims (1)

[Scope of utility model registration request] 1. A buffer for outputting a logic level, and a plurality of MOS switches connected between the input side of the buffer and the ground, wherein the MOS switches are turned on according to a set delay amount. A minute variable delay circuit configured to change the number to be changed.