JPH0551179B2 - - Google Patents
Info
- Publication number
- JPH0551179B2 JPH0551179B2 JP61011770A JP1177086A JPH0551179B2 JP H0551179 B2 JPH0551179 B2 JP H0551179B2 JP 61011770 A JP61011770 A JP 61011770A JP 1177086 A JP1177086 A JP 1177086A JP H0551179 B2 JPH0551179 B2 JP H0551179B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor chip
- electrode
- electrode connection
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に係り、特
に、フエースダウンボンデイング法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a face-down bonding method.
半導体集積回路等の半導体チツプをパツケージ
あるいは配線基板上に組み込むに際し、半導体チ
ツプをフエースダウンすなわち下向きにし電極部
との接続をワイヤでなく、より広い面積を持つた
面で接続するフエースダウンボンデイング法は、
ワイヤボンデイングを伴うフエースアツプボンデ
イング法に比べて、接続後の機械的強度が強く、
ボンデイングすなわち接続の回数も1回で済むこ
とから有益な方法であるとされている。
When a semiconductor chip such as a semiconductor integrated circuit is assembled onto a package or wiring board, the face-down bonding method is used to place the semiconductor chip face down, i.e., face down, and connect the electrode part with a surface with a larger area rather than with wires. ,
Compared to the face-up bonding method that involves wire bonding, the mechanical strength after connection is stronger.
It is said to be an advantageous method because only one bonding or connection is required.
このフエースダウンボンデイング法では通常、
半導体チツプの電極部にあらかじめバンプを形成
しておき下向きに融着して接続する(フリツプチ
ツプ方式)か又は、基板上の電極部にあらかじめ
バンプを形成しておき、半導体チツプを下向きに
して融着する(ペデスタル方式)かの方式により
半導体チツプと基板(パツケージ)との接続を行
なうようにしている。 This face-down bonding method usually
Bumps are formed in advance on the electrode portion of the semiconductor chip and the chips are fused downward (flip chip method), or bumps are formed in advance on the electrode portion of the substrate and the semiconductor chip is fused facing downward. The semiconductor chip and the substrate (package) are connected by the pedestal method.
このバンプはクロム(Cr)−銅(Cu)、アルミ
ニウム(Al)−シリコン(Si)、アルミニウム−
銅、アルミニウム−銅−シリコン、鉛(Pb)−錫
(Sn)等の合金、チタン(Ti)、アルミニウム、
クロム、ニツケル等の金属あるいはこれらの積層
体から構成されており、基板上の所望の位置に半
導体チツプを載置した状態で200〜500℃の高温に
加熱し、融着することにより電気的接続を達成す
るものである。 This bump is chromium (Cr) - copper (Cu), aluminum (Al) - silicon (Si), aluminum -
Alloys such as copper, aluminum-copper-silicon, lead (Pb)-tin (Sn), titanium (Ti), aluminum,
It is made of metals such as chromium and nickel, or a laminate of these metals, and electrical connections are made by heating the semiconductor chip to a high temperature of 200 to 500°C and fusing it with the semiconductor chip placed on the desired position on the substrate. The goal is to achieve the following.
しかるに、これらの方法では、
(1) バンプ形成に要する工程が複雑でコストが高
い。 However, in these methods, (1) the steps required for bump formation are complicated and costly;
(2) バンプを溶融状態に加熱する際、クラツクが
発生し易い。(2) Cracks are likely to occur when the bump is heated to a molten state.
(3) 半導体チツプ内の素子領域にバンプを構成す
る金属が拡散し、素子の特性が劣化する。(3) The metal forming the bumps diffuses into the element region within the semiconductor chip, degrading the characteristics of the element.
(4) バンプを構成する金属が加熱溶融する際に流
れ、シヨートが発生する等により、製造歩留り
が悪い。(4) When the metal forming the bump is heated and melted, it flows and shoots are generated, resulting in poor manufacturing yield.
等の不都合があつた。There were other inconveniences.
本発明は前記実情に鑑みてなされたもので、上
記不都合を廃し、製造が容易で、信頼性の高い半
導体装置の実装方法を提供することを目的とす
る。 The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a method for mounting a semiconductor device that eliminates the above-mentioned disadvantages, is easy to manufacture, and is highly reliable.
そこで本発明では、基板上の電極接続部と、半
導体チツプ上の電極接続部とが当接するように熱
収縮性および絶縁性を有する熱硬化性接着剤によ
つてこれら電極接続部以外の部分を接着せしめる
ようにしている。
Therefore, in the present invention, a thermosetting adhesive having heat-shrinkable and insulating properties is used to seal the parts other than the electrode connecting parts on the substrate and the electrode connecting parts on the semiconductor chip so that they come into contact with each other. I'm trying to glue it together.
すなわち、電極接続部を除く位置に絶縁性接着
剤を塗布し、加圧しつつ加熱することにより、絶
縁性接着剤を収縮および硬化せしめ、電極接続部
の圧接と電極接続部周辺位置で接着剤の硬化によ
る接着とを達成するようにしたものである。 That is, by applying an insulating adhesive to a position other than the electrode connection part and heating it while applying pressure, the insulating adhesive is contracted and hardened, and the adhesive is applied to the electrode connection part and the area around the electrode connection part. Adhesion is achieved by curing.
すなわち、例えば、第1図aに示す如く半導体
チツプの電極部1aに金属のバンプ2を形成する
と共に、基板3上の電極接続部3aを除く所定位
置に熱収縮性であつてかつ熱硬化性の絶縁性接着
剤4を充填する。
That is, for example, as shown in FIG. 1a, metal bumps 2 are formed on the electrode portions 1a of the semiconductor chip, and heat-shrinkable and thermosetting bumps are formed at predetermined positions on the substrate 3 except for the electrode connection portions 3a. Fill with insulating adhesive 4.
そして、第1図cに示す如く基板上に半導体チ
ツプを載置し、加圧しつつリフロー炉で加熱し接
着剤を硬化させる。 Then, as shown in FIG. 1c, a semiconductor chip is placed on the substrate, and the adhesive is cured by heating in a reflow oven while applying pressure.
このとき、接着剤は、硬化反応が進むにつれ
て、溶媒や反応生成物の気発により、収縮するた
め、半導体チツプと基板の電極間での密着性が増
し、電気的接続性が向上する。 At this time, as the curing reaction progresses, the adhesive shrinks due to the vaporization of the solvent and reaction products, thereby increasing the adhesion between the semiconductor chip and the electrodes of the substrate and improving electrical connectivity.
このようにして確実な接続が可能となる。 In this way, a reliable connection is possible.
また、半導体チツプの電極部にバンプを形成す
る代わりに、第1図bに示す如く、基板3上の電
極接続部3aにバンプ2を形成するようにしても
よい。 Furthermore, instead of forming the bumps on the electrode portions of the semiconductor chip, the bumps 2 may be formed on the electrode connection portions 3a on the substrate 3, as shown in FIG. 1B.
以下、本発明の実施例について、図面を参照し
つつ詳細に説明する。
Embodiments of the present invention will be described in detail below with reference to the drawings.
第2図a乃至dは、イメージセンサの駆動用
ICの実装工程を示す図である。 Figure 2 a to d are for driving the image sensor.
FIG. 3 is a diagram showing an IC mounting process.
まず、第2図aに示す如く、ガラス基板11上
に、受光素子部との接続用の金属膜からなる配線
パターン(信号引き出し線)12を形成し、この
うちの電極パツド部12a上に、厚膜法により膜
厚1μmのアルミニウム(Al)からなるバンプ1
3を形成する。 First, as shown in FIG. 2a, a wiring pattern (signal lead line) 12 made of a metal film for connection with a light receiving element part is formed on a glass substrate 11, and on an electrode pad part 12a of the wiring pattern 12, Bump 1 made of aluminum (Al) with a thickness of 1 μm using the thick film method
form 3.
次いで、第2図bに示す如くレジンコータによ
り、熱硬化型のエポキシ接着剤14を順次、該基
板上の所定の位置に充填する。 Next, as shown in FIG. 2B, a thermosetting epoxy adhesive 14 is sequentially filled into predetermined positions on the substrate using a resin coater.
続いて、第2図cに示す如く、143ピンの駆動
用IC15を順次、該基板上の配線パターン12
の所定位置に載置し、加圧により仮接着する。 Subsequently, as shown in FIG.
Place it in a predetermined position and temporarily adhere it by applying pressure.
そして最後に、シリコーン系の封止用樹脂16
をレジンコータにより塗布し、リフロー炉に入
り、150℃30分で接着剤および封止樹脂を同時に
硬化させ、第2図dに示す如く、駆動用ICの接
着および封止を行なう。 And finally, silicone sealing resin 16
was applied using a resin coater, and the adhesive and sealing resin were simultaneously cured at 150° C. for 30 minutes in a reflow oven, and the driving IC was bonded and sealed as shown in FIG. 2d.
このようにして、1回の加熱工程で、多数個の
半導体チツプの実装を行なうことができ、極めて
作業性が良好である上、電極間が、加圧状態で接
着されているため、電気的接続性が良好で信頼性
も高い、また、バンプは融着ではなく、押圧状態
で、駆動用ICの電極部に接触していればよいた
め、加熱温度も低く(接着剤の硬化温度)、素子
領域へのバンプ構成金属の拡散等による素子特性
の劣化もない。 In this way, a large number of semiconductor chips can be mounted in a single heating process, and workability is extremely good. In addition, since the electrodes are bonded under pressure, electrical Good connectivity and high reliability. Also, since the bumps only need to be in contact with the electrodes of the drive IC in a pressed state rather than fused, the heating temperature is low (adhesive curing temperature). There is no deterioration of device characteristics due to diffusion of bump constituent metal into the device region.
また、単純な垂直加圧により、容易にかつ信頼
性よく電気的く好な電気的接続および接着性を可
能にし、各導電性パターンの周囲を絶縁性樹脂に
よつて固着するとともに良好に絶縁しており、隣
接電極間のシヨートの発生もない。 In addition, simple vertical pressure enables easy and reliable electrical connection and adhesion, and the periphery of each conductive pattern is fixed with insulating resin and well insulated. Therefore, there is no occurrence of shoots between adjacent electrodes.
更に、仮に接続不良が発生した場合、有機溶剤
等で、接着剤を融解除去するのみで、再使用する
ことができるため、歩留りが向上する。 Furthermore, if a connection failure occurs, the adhesive can be reused simply by melting and removing it with an organic solvent or the like, which improves yield.
加えて、ワイヤボンデイング法等による実装に
加えて占有面積が小さいため、実装密度を上げる
ことができ、装置の小形化をはかることができ
る。 In addition, since it occupies a small area in addition to being mounted using a wire bonding method or the like, it is possible to increase the packaging density and downsize the device.
なお、実施例ではイメージセンサーの駆動用
ICを複数個実装する場合について説明したが、
単一の半導体チツプの実装あるいはハイブリツド
ICの製造をはじめ、いろいろな場合に適用可能
であり、この方法はワイヤボンデイング実装や、
タブ(TAB)、インナーイードボンデイング等の
ギングボンデイングに比べ、タクトタイム、材料
コスト等、トータルコストの点でも十分に優れて
いる。 In addition, in the example, it is used for driving the image sensor.
I explained the case where multiple ICs are mounted, but
Single semiconductor chip implementation or hybrid
This method can be applied to various situations including IC manufacturing, and this method can be used for wire bonding mounting,
Compared to bonding such as tab (TAB) and inner edge bonding, it is sufficiently superior in terms of takt time, material cost, and total cost.
また、実施例では、バンプは、基板上に形成し
たが、半導体チツプ側に形成してもよく、また、
回路パターン上、半導体チツプあるいは基板上の
電極部が凸状となつている場合には、特にバンプ
を形成することなく、そのまま使用すればよい。
更に、バンプを構成する金属については、実施例
に限定されることなく、金(Su)、銅(Cu)、ク
ロム(Cr)等あらゆる金属を使用することが可
能である。 Further, in the embodiment, the bumps were formed on the substrate, but they may also be formed on the semiconductor chip side.
If the electrode portion on the circuit pattern, semiconductor chip, or substrate has a convex shape, it may be used as is without forming any bumps.
Further, the metal constituting the bump is not limited to the examples, and any metal such as gold (Su), copper (Cu), chromium (Cr), etc. can be used.
更に、接着剤は、エポキシ樹脂に限定されるこ
となく、シリコーン系樹脂、ポリイミド系樹脂
等、熱収縮性であつてかつ熱硬化性の接着剤であ
ればよい。 Furthermore, the adhesive is not limited to epoxy resins, but may be any heat-shrinkable and thermosetting adhesive such as silicone resin or polyimide resin.
以上説明してきたように、本発明によれば、絶
縁性の熱硬化性接着剤によつて電極接続部以外の
部分を接着せしめることにより基板上の電極接続
部と半導体チツプ上の電極接続部とが押圧状態で
当接するようにしているため、接着温度が低い上
工程が簡略であつてコストも低くかつ、信頼性の
高い半導体装置を得ることができる。
As explained above, according to the present invention, by bonding the parts other than the electrode connection parts with an insulating thermosetting adhesive, the electrode connection parts on the substrate and the electrode connection parts on the semiconductor chip are bonded together. Since they are brought into contact with each other in a pressed state, it is possible to obtain a semiconductor device with a simple upper process requiring a low bonding temperature, a low cost, and high reliability.
第1図は、本発明の半導体装置の実装方法の概
略的説明図、第2図a乃至dは、本発明の実施例
のイメージセンサ駆動用ICの実装工程図である。
1……半導体チツプ、1a……電極接続部、2
……バンプ、3……基板、3a……電極接続部、
4……絶縁性接着剤、11……ガラス基板、12
……配線パターン、12a……電極パツド部、1
3……バンプ、14……エポキシ接着剤、15…
…駆動用IC、16……封止用樹脂。
FIG. 1 is a schematic explanatory diagram of a method for mounting a semiconductor device according to the present invention, and FIGS. 2 a to 2 d are process diagrams for mounting an image sensor driving IC according to an embodiment of the present invention. 1... Semiconductor chip, 1a... Electrode connection part, 2
...Bump, 3...Substrate, 3a...Electrode connection part,
4... Insulating adhesive, 11... Glass substrate, 12
... Wiring pattern, 12a ... Electrode pad part, 1
3...Bump, 14...Epoxy adhesive, 15...
...Drive IC, 16...Sealing resin.
Claims (1)
路素子等からなる半導体チツプを実装するに際
し、 該基板上の電極接続部を除く所定の位置に熱収
縮性かつ熱硬化性の絶縁性接着剤を塗布する塗布
工程と、 該基板の電極接続部と該半導体チツプとが互い
に当接して電気的接続が可能となるように、両者
を加圧しつつ加熱し、該基板上に該半導体チツプ
を接着せしめる接着工程とを 具えた半導体装置の製造方法。 2 前記基板は電極接続部としての電極パツド上
にバンプを形成してなるものであることを特徴と
する特許請求の範囲第1項記載の半導体装置の製
造方法。[Claims] 1. When mounting a semiconductor chip consisting of a semiconductor integrated circuit element, etc. on a substrate provided with a wiring pattern, a heat-shrinkable and thermosetting material is placed at predetermined positions on the substrate excluding electrode connection portions. a coating step of applying an insulating adhesive; and a step of applying an insulating adhesive onto the substrate by heating and applying pressure to the electrode connection portion of the substrate and the semiconductor chip so that they come into contact with each other and electrical connection is possible. A method for manufacturing a semiconductor device, comprising an adhesion process for adhering semiconductor chips. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is formed by forming bumps on electrode pads serving as electrode connection parts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61011770A JPS62169433A (en) | 1986-01-22 | 1986-01-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61011770A JPS62169433A (en) | 1986-01-22 | 1986-01-22 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62169433A JPS62169433A (en) | 1987-07-25 |
| JPH0551179B2 true JPH0551179B2 (en) | 1993-07-30 |
Family
ID=11787208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61011770A Granted JPS62169433A (en) | 1986-01-22 | 1986-01-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62169433A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0720958U (en) * | 1993-09-29 | 1995-04-18 | 陽 石川 | Retractable shield sheet |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2647047B2 (en) * | 1995-03-01 | 1997-08-27 | 日本電気株式会社 | Flip chip mounting method for semiconductor element and adhesive used in this mounting method |
| JP3801674B2 (en) * | 1995-12-15 | 2006-07-26 | 松下電器産業株式会社 | Electronic component mounting method |
| JP3065549B2 (en) | 1997-01-09 | 2000-07-17 | 富士通株式会社 | Semiconductor chip component mounting method |
| US20020014688A1 (en) * | 1999-03-03 | 2002-02-07 | Suresh Ramalingam | Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials |
| JP2000299553A (en) * | 1999-04-13 | 2000-10-24 | Ricoh Microelectronics Co Ltd | Manufacture of electronic circuit board |
| CN112968109A (en) * | 2020-11-27 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Driving back plate and manufacturing method thereof |
| WO2023119469A1 (en) * | 2021-12-22 | 2023-06-29 | 株式会社Fuji | Electrical circuit forming method and electrical circuit forming apparatus |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56167340A (en) * | 1980-05-27 | 1981-12-23 | Toshiba Corp | Junction of semicondctor pellet with substrate |
| JPS60262430A (en) * | 1984-06-08 | 1985-12-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0682708B2 (en) * | 1985-12-05 | 1994-10-19 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
-
1986
- 1986-01-22 JP JP61011770A patent/JPS62169433A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0720958U (en) * | 1993-09-29 | 1995-04-18 | 陽 石川 | Retractable shield sheet |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62169433A (en) | 1987-07-25 |
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