JPH0551993B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an initial value setting circuit for a memory cell array in a semiconductor memory device. In a semiconductor memory of a read/write type at any time, such as a dynamic RAM, the state ("0" or "1") of each memory cell when the power is turned on is not uniquely determined. Therefore, conventionally, in microcomputer systems equipped with memory whose initial state is undefined, for example, when writing image data to the memory and using it, data is written only to a predetermined area in the memory and other It was not possible to create a white or black background by directly using the initial state of the memory. In other words, in conventional dynamic RAM, it was unclear whether the initial state of each memory cell would be "0" or "1", so before operating the system, data was transferred one bit at a time to each memory cell in the memory cell array. (Initial value) had to be written. Therefore, especially in a system having a large capacity memory or a plurality of memories, there is an inconvenience that it takes a very long time to initialize all memory cells. Accordingly, the present invention provides a semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in a matrix, at the time of initial setting.
By simultaneously writing “0” or “1” to all memory cells belonging to the same row in the memory cell array, multiple bits can be initialized at the same time. This reduces the time required to initialize the entire memory cell array. The aim is to significantly reduce time. The present invention will be explained below using the drawings. First of all, the dynamics to which the present invention is applied
The basic circuit configuration of the RAM memory cell array and sense system will be explained with reference to FIG. In the circuit shown in Figure 1, the N-channel
MISFET (Metal Insulator Semiconductor
N-channel IGFET (Insulated-Gate Field Effect Transistor)
Transistor) as an example. The 1-bit memory cell M-CEL has a capacitor C S for information storage and a capacitor C _S for address selection.
MISFET Q _M , and information of "1" and "0" is stored in the form of whether or not there is a charge in the capacitor C _S. To read information, turn on MISFETQ _M.
This is done by connecting _CS to a common column data line DL and sensing how the potential of the data line DL changes depending on the amount of charge accumulated in _CS . Assuming that the potential previously charged in the stray capacitance C _O of the data line DL is the power supply voltage V _CC , if the information stored in C _S is "1" (potential of V _CC ), then at address time data line
The potential of DL remains the potential of V _CC , and if it is “0” (0V), the potential of data line DL is {C _O · V _CC −C _S (V _W −V _th )}/ It becomes C _O. however,
V _W is the gate voltage of MISFETQ _M , V _th is
This is the threshold voltage of MISFETQ _M. Here, the difference between logic “1” and logic “0”, that is, the detected signal amount ΔV _S is ΔV _S = (V _DL ) “ ₁ ” − (V _DL ) “ ₀ ” = (V _W − V _th )・C _S /C _O. When V _W = V _CC , the signal amount ΔV _S becomes ΔV _S = (V _CC −V _th )·C _S /C _O. Since the memory cells are made small and many memory cells are connected to a common data line to form a highly integrated and large capacity memory matrix, C _S ≪ C _O , that is, C _S /C _O , becomes a very small value. Become. Therefore ΔV _S
is a very weak signal. A dummy cell D-CEL is used as a reference for detecting such a minute signal. D-
CEL is manufactured under the same manufacturing conditions and design constants as M-CEL, except that the capacitance value of capacitor C _ds is approximately half that of C _S . The capacitor C _ds is charged to ground potential (the other electrode is fixed at V _CC ) by MISFETQ _D2 prior to addressing.
Therefore, the common column data line DL at address
The signal change amount ΔV _R given to the memory cell (ΔV _{S ) is expressed by the following equation, similarly to that of the memory cell (ΔV S} ). However, V _DW
is the gate voltage of MISFETQ _D2 , and V _th ′ is
This is the threshold voltage of MISFETQ _D2 . Assuming that ΔV _R =(V _DW −V _th ′)·C _ds /C _O V _DW =V _CC , ΔV _R is expressed by the following formula. ΔV _R =(V _CC −V _th ′)·C _ds /C _O As mentioned above, since C _ds is set to approximately half of C _S , ΔV _R is approximately equal to half of ΔV _S. Therefore, "1" and "0" information can be determined depending on whether the potential change applied to the data line DL of the memory cell is smaller or larger than that of the dummy cell (ΔV _R ). SA ₁ is a sense amplifier that expands the difference in potential change that occurs during addressing into the sensing period determined by the timing signal (sense amplifier control signal) φ _PA (the operation will be described later). Its input/output nodes are coupled to complementary data lines DL _1-1 and DL _1-1 . Data line DL _1-1 ,
The number of memory cells coupled to DL _1-1 is made equal to increase detection accuracy, and one dummy cell is coupled to each of DL _1-1 and _{DL 1-1} . Each memory cell is also coupled between one word line WL and one of a complementary pair of data lines. Each word line WL
crosses both data line pairs, so even if the noise component generated on the word line WL is transferred to the data line due to capacitive coupling, the noise component appears equally on both data lines, and the differential sense-up SA offset by. A pair of dummy word lines DWL _1-1 and DWL are connected so that when a memory cell coupled to one of the complementary data lines DL _1-1 and _{DL 1-1} is selected, a dummy cell is always coupled to the other data line. One of _1-2 is selected. This sense amplifier SA ₁ has a pair of cross-coupled MISFETs Q _S3 and Q _S9 , and uses their positive feedback action to differentially amplify minute signals. This positive feedback operation starts at the same time that MISFETQ _S10 starts conducting due to the timing signal (sense amplifier control signal) φ _PA , and based on the potential difference applied during addressing, the higher data line potential (V _H ) is slower. The one with the lower speed (V _L ) descends at a faster speed while the difference between them widens. Thus V _L is the threshold voltage V _Th of the cross-coupled MISFET
The positive feedback operation ends when V H falls to 0 V, and V _H remains at a potential smaller than V _CC and larger than V _Th , and V _L eventually reaches 0 V. During addressing, the stored information in the memory cell that is once destroyed is recovered (rewritten) by directly receiving the potential of V _H or V _L obtained by this sensing operation. However, if V _H falls below V _CC by more than a certain level, a malfunction will occur that will be read as a logic "0" after reading and rewriting several times. The active restore circuit AR ₁ was provided to prevent this malfunction, and this AR ₁ has the function of selectively boosting only V _H to the potential of V _CC without having any effect on V _L. There is. The capacitance of C _B11 and C _B12 changes depending on the voltage applied to the terminal on the left side of the drawing.
It is an MIS type variable capacitance element, and it should be understood that logically it can act as a capacitor at a higher voltage than the threshold voltage V _Th , and cannot act as a capacitor at a lower voltage. When MISFETQ _S4 and Q _S5 are made conductive by the timing signal (active restore control signal) φ _rg , the variable capacitance element C _B belonging to the data line at the potential of V _H is charged, and then signal) When _φrs becomes high level, MISFETQ _S6 or
The gate potential of Q _S7 becomes sufficiently higher than V _CC and the potential of V _H is restored to V _CC . In this case, in order to reduce the power loss of Q _S6 and Q _S7 , each V _Th is designed to be smaller than the MISFET without an asterisk. When timing signal φ _PC is high level (V _CC
MISFETs Q _S2 and Q _S3 conduct, and the stray capacitance C _O of the complementary data line pair DL _1-1 , _1-1 is precharged to V _CC . At this time, MISFET Q _S1 is also conductive at the same time, so even if an imbalance occurs in the precharging by Q _S2 and Q _S3 , the complementary data line pair DL _1-1 , _1-1 is short-circuited and set to the same potential condition. MISFETQ _S1 to Q _S3 have V _Th lower than MISFETs without * to prevent voltage loss between their respective sources and drains.
is set low. At this time, the timing signal (discharge control signal) φ _dc causes MISFET Q _d2 to conduct, and the dummy cell D-CEL is similarly reset to a predetermined state. Timing signal (address buffer control signal)
The row address signals A _O to A _i supplied from the address buffer ADB at the timing of φ _AR (see Figure 3) are decoded (deciphered) by the row/column decoder RC-DCR and output as the word line control signal _φ Addressing of the memory cell M-CEL and the dummy cell D-CEL is started simultaneously with the rise of the dummy cell D-CEL. As a result, a voltage difference of approximately ΔV _S /2 is generated between the complementary data line pair DL _1-1 , _1-1 based on the stored contents of the memory cells, as described above. Timing signal (sense up control signal) _φPA
As soon as MISFETQ _S10 starts to conduct, sense amplifier _SA1 starts positive feedback operation and amplifies the detection signal of ΔV _S /2 generated at the time of address. After the amplification operation is almost completed, the above-described active restore circuit AR ₁ restores the logic "1" level to V _CC in synchronization with the timing signal (active restore control signal) φ _rs . Timing signal (address buffer control signal)
Column address signals A _i+1 to A _j sent from address buffer ADB in synchronization with φ _AC are low.
The information stored in the memory cell M-CEL at the column address selected by the timing signal (column switch control signal) φ _Y is decoded by the column decoder RC-DCR and then sent to the column switch C-DCR.
It is transmitted to the common data lines CDL ₁ , ₁ via SW ₁ . Next, the main amplifier/data output buffers OA & DOB operate according to the timing signal (data output buffer and main amplifier control signal) φ _OP , and the read storage information is sent to the output terminal D _put of the chip. Note that this OA&DOB is a timing signal (data output buffer control signal) when writing.
φ Disabled by _RW . During a write operation, precharging, addressing, and sensing are exactly the same as in the read operation described above. Therefore, complementary data line pair DL _1-1 ,
Memory information of the memory cell to which writing should originally be performed is read out from DL _1-1 regardless of the logical value of the input write information D _io . Since this read information is to be ignored in the write operation described later, the operation up to this point can be considered to be essentially row address selection. Similar to the read operation, the data line pair DL _1-1 , _1-1 located in the selected column is connected to the common data line via the column switch C-SW ₁ in synchronization with the timing signal (column switch control signal) _φY .
Combined with CDL ₁ , ₁ . Next, complementary write input signals dio _{and io} supplied from the data input buffer DIB in synchronization with the timing signal (data input buffer control signal) _{φRW are} applied to the memory cell M- through the column switch C- _SW1 .
Written to CEL. At this time, the sense amplifier
Although SA ₁ is also operating, the output impedance of the data input buffer DIB is low, so the information appearing on the column data line pair DL _1-1 , _1-1 is determined by the information on the input D _io . Note that in the refresh operation, the information that is being lost stored in the memory cell M-CEL is temporarily read out to the column common data line DL, and the read information is sent to the sense-up _SA1 and the active restore circuit.
This is done by writing the memory cell M-CEL again to the level restored by _AR1 .
Therefore, the refresh operation is similar to the row addressing or sensing period operation described in the read operation. However, in this case, the column switch C- _SW1 is made inactive and refresh is performed simultaneously for all columns and for each row in turn. The normal read/write operation and refresh have been explained above, and next, the initial setting operation according to the present invention will be explained. In the first embodiment, the above circuit configuration is used in a modified form, and the dummy cell D-CEL is
The circuit for generating the timing signal φ _dc supplied to the gate terminal of MISFETQ _D2 is configured as shown in FIG. In other words, the timing signal _φdcp is generated via the timing generators 11 and 12 based on the signal (row address/strobe signal) supplied from the outside, and the timing generator is generated based on the signal (column address/strobe signal). The timing φ _dc is generated in the signal generation circuit 14 from the initialization signal φ _INT generated by the generator 13 . During normal read and write operations, the initialization signal _φINT is set to low level.
Based on the falling edge of the signal, the timing signal φ _dc
is changed from high level to low level as shown by the solid line in FIG. This charges the capacitor C _ds in the dummy cell to ground potential, and then
MISFETQ _D2 is turned off and read and write operations are performed as described above. When it is determined that the mode is the initial setting mode, for example, by a combination of appropriate falling timings of the signals and the signals, the timing generator 13 generates a high-level initialization signal φ _INT . Then, the timing signal φ _dc generated from the signal generation circuit 14 is
As shown by the broken line in the figure, the level is continuously set to high. Therefore, dummy cell D-CEL has dummy word line DWL _1-1 set to the selection level.
MISFETQ _D1 is turned on and the sense amplifier
Even if SA ₁ starts sensing operation by timing signal φ _PA , capacitor C _ds and MISFETQ _D1 , Q _D2
The connection node with is left at ground potential.
As a result, the data line _1-1 is forced to the ground potential, and regardless of the level of the data line DL _1-1 , once "0" is read,
"0" is written into the memory cell M-CEL by the active restore circuit _AR1 . Moreover, at this time, the address decoder RC-
DCR, as in the case of refresh operation,
Not only the above data line DL _1-1 but also other data lines
DL will also be pre-charged. As a result, "0" is simultaneously written into all memory cells connected to the word line WL _1-2 set to the selected level. In the embodiments described above, "0" can be written to the memory cells for each word line at the time of initial setting. Next, an embodiment in which memory cells "0" or "1" can be written in by initial setting will be described with reference to FIGS. 4 and 5. However, in order to make the explanation easier to understand, the complementary data line pairs DL _1-1 and _1-1 are opened to the left and right, and only the main parts of the circuit are shown, and the peripheral parts that have the same configuration as the circuit in Figure 1 are explained here. , illustration and explanation will be omitted. In this example, in the dummy cell D-CEL
Instead of being connected to the ground line, MISFETQ _D2 is connected to the V _DC line 15. Also,
Add a new V _DC generation circuit 16 and the above V _DC line 1.
A level switching circuit 17 is provided for selectively connecting V _DC generating circuit 16 or ground potential. The level switching circuit 17 is controlled by an initialization signal φ _INT generated from the timing generator 13. Above signal φ _INT
During a normal read or write operation in which VDC is set to a low level, the level switching circuit 17 connects the V _DC line 15 to the ground potential. Therefore, at the time of initialization when the initialization signal φ _INT is set to a high level, the V _DC line 15 is connected to the ground potential or to the V _DC generation circuit depending on the write data (initial value). The V _DC generation circuit 16 is configured to generate a voltage V _DC at the same level as the selection signal, such as +5V, in response to the initialization signal φ _INT . Then, when the V _DC line 15 is connected to the V _DC generation circuit 16 by the level switching circuit 17, when the MISFETQ _D2 is continuously turned on by the timing signal φ _dc , the capacitor C _ds and The connection node of V _DC line 15 is set to the same 5V. Therefore, during initial setting, the data line _1-1 is constantly pulled up to 5V. On the other hand, the data line
Even if "1" is written in the selected memory cell, DL _1-1 is only kept at 5V by the stray capacitance C _O of the data line and the charge charged in the capacitor C _S. The sense amplifier SA ₁ always reads data as "0", and then the active restore circuit AR ₁ writes "0" into the selected memory cell. Note that when the V _DC line 15 is connected to the ground potential, "1" is written into the selected memory cell, similarly to the first embodiment. As described above, in the above embodiment, the conventional circuit is hardly changed, and the new timing generator 13 and signal generation circuit 14 are simply provided, or the V _DC generation circuit 16 and the level switching circuit 17 are added. By simply adding this, it is possible to simultaneously write "1" or "0" to all memories for each line. Therefore, the time required for initial setting is significantly reduced compared to the conventional method in which writing is performed bit by bit. Furthermore, in the above embodiment, the initialization signal φ _INT is generated based on a combination of signals and signal timings, but it is generated based on a control signal supplied from a dedicated external terminal. It's okay. or,
RAS signal and signal (write enable signal)
The initialization signal φ _INT can also be generated based on a combination with other external signals such as . Further, as the V _DC generation circuit 16, a dedicated circuit may be provided as in the above embodiment, but it may also be used as an input buffer circuit or an address buffer circuit, so that V _DC (5V ) can be generated and supplied to the dummy cell array via the switching circuit 17. FIG. 6 shows yet another embodiment of the invention. In this embodiment, an initial setting MISFET Q _i is connected to each data line DL in the memory cell array, and an initial setting voltage V _INT is supplied to the source or drain terminal of this MISFET Q _i . Also,
The gate terminal of MISFETQ _i is supplied with an initialization signal φ _INT such as that generated in the timing generator 13 of FIG. 5. The initial setting voltage V _INT is generated in a circuit similar to the V _DC generating circuit 16 in FIG. 5, and is set to 5 V or ground potential (0 V) depending on the data (initial value) to be written. Therefore, at the time of initialization, when a high level initialization signal φ _INT is generated based on the signals,
MISFETQ _i is turned on. At that time, when the voltage V _INT being generated is low level (0V),
Data line DL is forced to 0V. Therefore, the level of the data line DL becomes lower than that of the data line on the dummy cell side, and after "0" is once read from the selected memory cell, the active restore circuit in the sense amplifier SA
“0” is written. On the other hand, if the voltage V _INT is set to 5V, the data line DL is set to 5V regardless of the memory cell, so "1" is written. In this embodiment as well, initial value writing is performed for each word line, similar to refresh. That is, in the external addressing method, word lines are selected one by one by address signals supplied from the outside to address terminals every cycle, and initial values are written. In addition, in a memory with an internal refresh function, an internal address counter is updated by an externally supplied clock signal, and word lines are sequentially selected by this address counter, and each word line is initialized. Writing of values continues. Note that this invention does not apply to dynamic
It can be applied not only to RAM but also to static RAM. Since this invention is configured as described above, it is possible to simultaneously write "0" or "1" to all memory cells belonging to the same row (connected to each word line) in the memory cell array at the time of initial setting. It is possible to initialize multiple bits at the same time. This significantly reduces the time required to initialize the entire memory cell array.
For example, if the memory cell array is configured in a matrix of N.times.N bits, the setting time is reduced to 1/N, that is, 1/256 for a 64K bit RAM.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a dynamic RAM as an example of a semiconductor memory device to which the present invention is applied;
FIG. 2 is a timing chart showing the timing of signals in each part of the circuit, FIG. 3 is a block diagram showing an example of the signal generation system of the initial value setting circuit according to the present invention, and FIG. 4 is a memory to which the present invention is applied. A circuit explanatory diagram showing another example of the configuration of the main part of the circuit, FIG. 5 is a block diagram showing an example of the signal generation system used in this, and FIG. 6 is a still another example of the structure of the main part of the memory circuit. FIG. M-ARY...Memory cell array, M-CEL...
...Memory cell, D-CEL...Dummy cell, DL...
...Data line, WL...Word line, ADB...Address buffer, SA...Sense amplifier, φ _INT ...
Initialization signal.

Claims (1)

[Claims] 1 A plurality of memory cells each consisting of an information storage capacitor and an address selection switch are arranged in a matrix, the input/output terminals of the memory cells are connected to one of a plurality of pairs of mutually exclusive data lines, and the memory cells The control terminal of the address selection switch is connected to one of a plurality of word lines arranged to intersect with the complementary data pair, and each of the complementary data lines is connected to two of the information storage capacitors. A dummy cell consisting of a comparison capacitor having a capacitance value of 1/2, a selection switch, and a charging switch for charging the comparison capacitor is connected to each of the dummy cells, and the address signal for selecting the word line is supplied from the first The address signal for selecting the complementary data line pair is taken in in synchronization with a second control signal applied from the outside, and the address signal is sent to the capacitor in the dummy cell prior to selection of the memory cell. A predetermined charge is charged in advance, and when any memory cell is selected, a dummy cell connected to the data line that is paired with the data line to which the memory cell is connected is selected, and the complementary data is In a semiconductor memory device in which a level difference generated between a pair of lines is amplified by a differential sense-up provided between a pair of complementary data lines and can be output to the outside, a combination of the first and second control signals is provided. In the first mode determined based on the above, a control signal for the charging switch that gives the charge timing to the capacitor in the dummy cell is formed, and the first mode is determined based on the combination of the first and second control signals. In the second mode, a signal for fixing the potential of one of the pair of complementary data lines is formed via the dummy cell, and is supplied to the charging switch, activating the sense-up to activate the selected memory cell. An initial value setting circuit characterized in that the initial value setting circuit is configured such that an initial value is written into the circuit.