JPH0552500B2 - - Google Patents

Description

[Detailed Description of the Invention] News can be broadcast using telephone lines or by using the vertical blanking period of television broadcasting.
Systems for transmitting information such as electricity forecasts and notices include captain systems and television text multiplex broadcasting systems.

On the transmitting side, characters such as letters, numbers, or symbols are converted into code signals and transmitted.
On the receiving side, the original character is decoded from the code signal and displayed on the screen of the television receiver.

For example, in the case of the letter "A", the code signal "41" (hexadecimal value) indicating the letter "A" from the transmitting side is 8
It is converted into bit binary code and sent. Then, on the receiving side, this code signal “41”
is supplied to a character generator to form a luminance signal that is the pattern of the letter "A", thus displaying the letter "A" on the screen of the receiver.

In this case, smoothing is actually performed to make the displayed characters easier to see.

That is, FIG. 1 schematically shows an example of the original pattern of the letter "A" written on the character generator, and this original pattern is composed of, for example, a dot matrix of 5 x 7 dots. .

FIG. 2 also shows the letter "A" displayed on the screen of the receiver. However, smoothing is not performed. Further, L ₁ to _{L 14} indicate scanning lines, the scanning line L _2n+1 shown by the broken line is formed during the odd field period, and the scanning line L _2n shown by the solid line is formed during the even field period. In addition, Du indicates a dot (bright spot) of the basic size, and since the output of the character generator (Fig. 1) is used for both the odd field period and the even field period, the display as shown in the figure It becomes a pattern.

On the other hand, when smoothing is performed, the letter "A" is displayed as shown in FIG. 3, and a half dot Dh having a width 1/2 of the original dot Du is added. Therefore, it becomes smoother and easier to see than the letter "A" before smoothing in FIG. 2.

When performing this smoothing, there are basically only two combinations of half dots Dh for each unit dot Du as shown in FIG. 4, and half dots Dh are added to all characters in the combinations shown in FIG. 4.

FIG. 5 shows an example of a circuit for performing such smoothing. That is, in FIG. 5, 21 indicates a character generator for display data, which has an original pattern of, for example, 5.times.7 dots as shown in FIG. 1, for example. and,
The character generator 21 includes video RAM.
(not shown) by supplying the character code CHR as an upper address, this code
The original pattern corresponding to CHR is selected, and
By supplying the row signal DRS as a lower address, it is specified which row of the selected original pattern.
The data of the desired character is 1 by DRS.
Five bits per row are sequentially extracted.

Further, 22 indicates a character generator for reference data, which is the character generator 2.
Same as 1, character code CHR
is supplied as the upper address, but another row signal RRS is supplied as the lower address. This row signal RRS is one line lower than the row of the original pattern specified by the row signal DRS during the odd field period.
This signal specifies the next row above, and during the even field period, specifies the row one below the row specified by the row signal DRS.

Furthermore, 31 indicates a shift register for 6-bit display data. This register 31 corresponds to register 3 in Fig. 1, and its lower 5 bits are
The output data of the character generator 21 is supplied to _D0 to _D4 , and the clock forming circuit 30
Pulse CLK with a period corresponding to the horizontal scanning speed from
is supplied as a shift clock, and the register 31
data is shifted toward the most significant bit. In this case, one period of the pulse CLK corresponds to the horizontal width of the unit dot Du, but the pulse CLK
is “1” in the first half cycle and “0” in the second half cycle
shall be.

Further, 32 indicates a shift register for 6-bit reference data, and the output data of the character generator 22 is supplied to the lower 5 bits _R0 to _R4 , and the pulse CLK is supplied as a shift pulse to the register. 32 data is shifted towards the most significant bit.

The output of bit _D4 of register 31 is then supplied to CRT display 50 through OR circuit 41. Therefore, in this state, the display 50 displays a character that has not been smoothed, as shown in FIG. 2, for example.

Furthermore, bit _D5 of register 31, bit _R4 of register 32, and pulse CLK are supplied to AND circuit 42, and bit D5 of register 32 is supplied to AND circuit 42.
_R5 is supplied to the AND circuit 53 through the inverter 44, and its AND output Pf is supplied to the OR circuit 41. Also, bit D ₃ of register 31,
Bit R ₄ of the register 32 and the inverted pulse of pulse CLK are supplied to the AND circuit 43, and bit R ₃ of the register 32 is supplied to the AND circuit 54 through the inverter 45, and the AND output Pb is supplied to the OR circuit 41. is supplied to

Therefore, the signals Pf and Pb are as follows: Pf= _{D 5.5.R 4.CLK} Pb= _{D 3.4.3 .}
A half dot Dh is displayed as shown in B.
That is, in FIGS. 6A and 6B, one square corresponds to a unit dot Du, a square with a diagonal line corresponds to a displayed unit dot Dh (level "1"), and a square without a diagonal line corresponds to an undisplayed unit dot Du ( level “0”)
shows. Also, during an odd field period, a half dot Dh is displayed by the line currently being displayed and the line above it, so during the odd field period, the line shown in Fig. 6A is displayed, and during the even field period, the current display is displayed. Since a half dot Dh is displayed by the line being displayed and the line below it, the result is as shown in FIG. 6B during the even field period. Half dots Dh (half-width squares with diagonal lines) are displayed by the signals Ph and Pb.

Therefore, as shown in FIGS. 6A and 6B, half dots Dh are displayed and smoothing is performed.

However, when smoothing is performed as described above, there is actually a time delay in the circuit, so the position of the displayed half dot Dh shifts.

That is, it is assumed that the time delays in the circuits 31 to 45 are uniformly equal to the time τ. Further, it is assumed that the original pattern of the character to be displayed is, for example, a dot arrangement as shown in FIG. 7A.

Then, when horizontal scanning (reading) is performed on the dots on this original pattern during a certain horizontal period, bit D ₄ of the register 31 and output Q ₄₁ of the OR circuit 41 with respect to the clock CLK become as shown in FIG. 7B. , C, the signals are delayed by the time τ, respectively. Therefore, during this horizontal period, the signal
_Q41 causes the unit dot Du to be displayed as shown in FIG. 7E (for simplicity, the half dot Dh in this horizontal period is omitted).

Then, when horizontal scanning is performed on the dots below the original pattern in FIG. 7A in the next horizontal period, assuming that it is an odd field period (FIG. 6A),
The waveforms of each part are as shown in FIG. 7D ( ₅ is the output of the inverter 44). Therefore, in this horizontal period, unit dots Du and half dots Dh are displayed by the signal _Q41 as shown in FIG. 7F (for simplicity, the half dots Dh by the signal Pb are omitted).

Therefore, the half dot Dh is shifted to the right compared to the surrounding unit dots Du, and moreover, it is half the original dot.
The image will be displayed even narrower than the width of the image. Furthermore, at this time, noise dots Dn that do not originally exist
is added.

Also, the frequency of the clock CLK is 5.73MHz, so one period of the clock CLK, that is,
Since the temporal width of the unit dot Dn is extremely short at 175 μsec, the influence of the time delay τ is large.

Therefore, in general, a delay circuit is provided at each part of the signal line to prevent the half dot Dh from shifting or becoming narrow, or to prevent the generation of noise dots Dn.

However, such a method requires a delay circuit for each signal line, resulting in increased costs. In addition, the time delays of the circuits 31 to 45 differ from circuit to circuit, and even in the same circuit, there are variations depending on the IC used, so the delay time of the delay circuits must be adjusted, which impairs mass production.

This invention attempts to eliminate these problems.

Therefore, in this invention, for example, the ninth
As shown in the figure, a first character generator 21 generates a signal indicating the original dot pattern of the character based on the character code CHR and a first row signal DRS indicating the row number n; 1 for CHR and above line number n
The second line indicating the line number n±1 of the line above or one line below
a second character generator 22 for generating a signal indicative of the original dot pattern of the character based on the row signal RRS of the character; and a first clock pulse having a period equal to the dot period of the character.
CLK, and a clock forming circuit 30 that generates a second clock pulse WCK having a frequency twice that of the first clock pulse and whose phase leads the phase of the first clock pulse;
a first shift register 31 that sequentially shifts signals indicating the original dot pattern of the row number n, which are supplied in parallel from the first character generator, based on the first clock pulse; a second shift register 32 that sequentially shifts signals indicating the original dot pattern of the row number n±1, which are supplied in parallel from the clock generator, based on the first clock pulse; and the first and second shift registers. Based on the output signal of the register, the first character generator generates signals Pf and Pb indicating a half dot pattern related to the original dot pattern generated, and outputs signals Pf and Pb indicating the half dot pattern related to the original dot pattern generated by the first character generator. Logic circuits 41 to 4 that sequentially output signals indicating a pattern
5, and a flip-flop circuit 60 to which the output signal _Q41 of the logic circuit is supplied and successively outputs a signal indicating the original dot pattern and a signal indicating the half dot pattern based on the second clock pulse. It is something.

Thus, in the present invention, the D flip-flop circuit 60 is provided, thereby achieving clock synchronization with the signal _Q41 .

That is, the signal Q ₄₁ is supplied to the D terminal of the D flip-flop circuit 60, and the output signal Q ₆₀ of the Q terminal is supplied to the display 50.
In addition, the clock CLK is output from the clock forming circuit 30.
A clock WCK with twice the frequency is extracted,
This clock WCK is the flip-flop circuit 60
is supplied to the clock terminal CK.

According to such a configuration, the clock CLK,
CLK is formed by dividing the frequency of clock WCK, so clock WCK is the 8th clock with respect to clock CLK.
The phase is advanced as shown in Figures B and E.
Note that FIGS. 8A to 8D are the same as FIGS. 7A to D.

Since the signal Q ₄₁ is loaded into the flip-flop circuit 60 by the rise of this clock WCK, the signal Q ₄₁ (FIG. 8C) in the horizontal period scanning the dots on the original pattern (FIG. 8A) is loaded into the flip-flop circuit 60.
is a signal Q ₆₀ as shown in FIG. 8F, and therefore, the unit dot Du is displayed as shown in FIG. 8H by this signal Q ₆₀ .

Furthermore, the signal Q ₄₁ (D in FIG. 8) during the horizontal period scanning the dots below the original pattern is the signal Q ₆₀ as shown in G in FIG. 8, so this signal Q ₆₀
As a result, unit dots Du and half dots Dh are displayed as shown in FIG. 8I. And at this time,
The half dot Dh does not shift in position or become narrow in width with respect to the surrounding unit dots Du. Further, noise dots Dn are not generated.

Thus, according to the present invention, even if there is a time delay in the circuit, the position of the half dot Dh will not shift,
It is possible to prevent the width from becoming narrow or from generating noise dots Dn.

Moreover, for this purpose, it is only necessary to add the D flip-flop circuit 60, and there is almost no increase in cost. Moreover, various adjustments are not required, and mass productivity is good.

Note that the above is a case where the deviation between the unit dot Du and the half dot Dh and the change in width are compensated for, but there is a difference between the main display signal and the deviation, such as the deviation between the displayed character and its color. It is also possible to compensate for deviations between the sub-display signal and the sub-display signal. Furthermore, the output of the character generator 22 can also be obtained from the character generator 21 in a time-sharing manner. The present invention can also be applied to television teletext receivers, personal computers, and the like.

[Brief explanation of drawings]

1 to 8 are diagrams for explaining this invention, and FIG. 9 is a system diagram of an example of this invention. 21, 22 are character generators, 31,
32 is a shift register.

Claims (1)

[Scope of Claims] 1. A first character generator that generates a signal indicating an original dot pattern of a character based on a first row signal indicating a character code and a line number n; a second character generator that generates a signal indicating the original dot pattern of the character based on a second row signal indicating a row number n±1 one row above or one row below the row number n; A clock generating a first clock pulse having a period equal to the dot period of the character and a second clock pulse having a frequency twice that of the first clock pulse and whose phase leads the phase of the first clock pulse. a first shift register that sequentially shifts signals indicating the original dot pattern of the row number n, which are supplied in parallel from the first character generator, based on the first clock pulse; a second shift register that sequentially shifts signals indicating the original dot pattern of the row number n±1, which are supplied in parallel from the two character generators, based on the first clock pulse; Based on the output signal of the shift register, the first character generator generates a signal indicating a half dot pattern related to the original dot pattern generated, and generates a signal indicating the original dot pattern and the half dot pattern. a logic circuit that sequentially outputs a signal indicating the original dot pattern and a flip-flop that is supplied with the output signal of the logic circuit and successively outputs a signal indicating the original dot pattern and a signal indicating the half dot pattern based on the second clock pulse. A character display device comprising a circuit.