JPH0552533B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an information processing device that employs a advance control method, and more specifically, the present invention relates to an information processing device that employs a advance control method, and more particularly, to a store in which an operand of an instruction is read out prior to execution of the instruction. The present invention relates to a control means for starting rereading of an operand when it is changed in memory by a system instruction.

[Field of application of the invention]

The present invention relates to an information processing device that employs a proactive control method, and more specifically, the present invention relates to an information processing device that uses a advance control method, and more particularly, the present invention relates to an information processing device that uses a advance control method. The present invention relates to a control means for starting rereading.

[Background of the invention]

In a pipeline control type information processing apparatus, each stage of instruction processing such as instruction decoding, operand reading, and instruction execution progresses in an overlapping manner between consecutive instructions. Therefore,
A case may arise in which the operand read by a subsequent instruction precedes the store by a preceding instruction. In an information processing device manufactured under an architecture that requires sequential instruction processing, the operands of the subsequent instruction are read from the storage area that is being modified by the preceding instruction being executed or waiting to be executed. When attempting to execute this, it is necessary to detect this inconsistency, delay reading the operand of this subsequent instruction until the storage area change by the preceding instruction is completed, and then read the operand after resolving the ordering conflict. It is. Generally, this process is performed by OSC
(Operand Store Compare).
When an OSC occurs, operand reading for subsequent instructions is delayed until the OSC is resolved, which disrupts instruction pipeline processing and degrades performance. Therefore, with respect to OSC processing, accurate detection and delayed operand reading are required to be performed as soon as possible if the OSC clears.

Hereinafter, a conventional processing method related to OSC detection will be explained with reference to FIG.

In FIG. 1, 1 is an address adder for calculating the operand address (generally the start address) of an instruction. The operand address is determined, for example, by adding the index value X, base value B, and displacement value D of the instruction, and is set in the address register 3 through line 2. 4 is an operand length control circuit that obtains the operand length of the instruction. The operand length may be determined only from the instruction's operation code, directly specified by the instruction's operand length specification field, or stored in a general-purpose register specified by the instruction's general-purpose register field, etc. However, in any case, it is obtained under the control of the operand length control circuit 4.

The operand address and operand length of the above instruction are determined in synchronization with the decoding of the instruction, and are input to the operand length adder 7 through lines 5 and 6. The operand length adder 7 is for adding the operand length to the operand address.

12-1 to 12-n are store address registers that store store addresses by preceding instructions, and are two sets of address registers into which the outputs of address register 3 and operand length adder 7 are input through lines 8 and 9, respectively. configured. That is, store address registers 12-1 to 12-n
each stores the start address and end address of the operand stored by the instruction, and holds a storage area section that is changed for each operand. 13-1 to 13-n are OSC detection circuits corresponding to store address registers 12-1 to 12-n, and for each operand of fetch and store, it detects the section of the storage area changed by store and referenced by fetch. It is configured so that OSC detection can be performed using a storage area section. 1
0 is a control circuit that initiates the necessary operations when an OSC is detected.

Next, the operation shown in FIG. 1 will be explained. When an instruction that requires an operand store is decoded, the store operand address (start address) calculated in synchronization with this decode is sent via address register 3, lines 5 and 8, and also to the decode. Synchronously, the end address calculated by the operand length adder 7 under the control of the operand length control circuit 4 is sequentially registered via line 9 in each one of the store address registers 12-1 to 12-n. Ru. At this time, the valid bit (not shown) of the corresponding store address register is set at the same time, and the
Act as a comparison address for OSC detection. Further, this valid bit is reset when all the store operations of the instruction, in other words, all the store operations for the storage area that the instruction intends to change, are completed. On the other hand, when an instruction that requires an operand fetch is decoded, the start address of the fetch operand is stored in the address register 3.
The end address is similarly calculated by the operand length adder 7 under the control of the operand length control circuit 4.

The start address and end address of this fetch operand are input to the OSC detection circuits 13-1 to 13-n via lines 8 and 11, and the store addresses registered in the store address registers 12-1 to 12-n are input to the OSC detection circuits 13-1 to 13-n. It is compared to see if it is between the start address and end address of the uncompleted operand,
OSC detection is performed. If an OSC is detected, control is transferred to the control circuit 10 and necessary operations are activated.

FIG. 3 shows an example of the configuration of the control circuit 10 shown in FIG. The output lines 14-1 to 14-n of the OSC detection circuits 13-1 to 13-n are ORed by the OR gate 32, and set in the latch 33 by the line 22 which is the output of the operand read control circuit 30, that is, by the operand read request. . When the line 34, which is the output of the rat 33, is "1", the operand read control circuit 30 is inhibited from decoding a subsequent instruction that involves operand reading. This is Latch 3
Maintain state 3. That is, this is to prevent the latch 33 from being improperly updated by a subsequent instruction. Store control circuit 31 outputs a store operation complete signal on line 24 and resets latch 33. While the line 34 is “1”, reading of the subsequent operand that generated the OSC is inhibited.
When the operand changes from "1" to "0", reading of the operand is activated. When reading the operand, it is actually optimal in terms of performance to be activated upon completion of the instruction that performs the advance store that generated the OSC. However, although there may be multiple preceding store instructions, in this prior art, the subsequent operand read is activated by the first preceding store operation, so when the read is executed, it is possible that the OSC will become the OSC again. There is sex. this is,
This is because the subsequent operand read that caused the OSC does not have a mechanism to identify the preceding store that has caused the conflict among the possible plural preceding stores.

FIG. 4 illustrates a problem that occurs in the present prior art when a plurality of preceding stores exist when an OSC occurs. D, A, B, E ₀ ,
E ₁ and W indicate instruction pipeline processing,
D indicates instruction decoding, A indicates address calculation, B indicates buffer storage readout, T indicates data operation transfer to the unit, E ₀ and E ₁ indicate operation, and W indicates storage to buffer memory. In this example, assume that instruction 1 is a store to address X, instruction 2 is a store to address Y, and instruction 3 is a load from address Y.

FIG. 4 shows the flow of instruction processing based on the prior art. In cycle 5, instruction 3 reads the buffer memory at address Y, but since the update of the area by instruction 2, which is the preceding instruction, has not been completed,
OSC is detected and the device waits for reading. In this prior art, the reading of instruction 3 is started in cycle 8 using the completion of the store by instruction 1 in cycle 7 as a trigger, but the update of the Y address by instruction 2 has not yet been executed, and the OSC occurs again. However, in cycle 8, buffer memory accesses due to the store of instruction 3 and the read of instruction 3 conflict, but it is assumed that the read is performed with priority. this is,
Read delay has a greater influence on pipeline delay, and this is a prioritization system that is generally adopted in pipeline processing to improve performance. The operand read of instruction 3 is executed again in the next cycle (cycle 10) after the store execution of instruction 2, and the data specified by the program can be read for the first time.

FIG. 4 2 shows an ideal example of the operation of this program. This indicates that it is desirable to control the operand read of instruction 3 so that it is executed in the cycle following the completion of the store operation of instruction 2 that generated the OSC.

The feature of the OSC detection method shown in FIG. 1 is that the start address and end address of the store operand are registered in the store address registers 12-1 to 12-n, and the store and fetch operands are stored in the section of the storage area that is actually updated. By comparing the actual referenced storage area and detecting the OSC,
The point is that OSC detection is performed precisely. On the other hand, OSC
In order to improve processing efficiency, it is required to read out the delayed operand as soon as possible when the OSC is cleared, as shown in FIG. was insufficient.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing device using a proactive control method, which retains the detection results of an OSC detection circuit and allows the corresponding operand to be read immediately after the OSC is resolved, thereby further improving instruction processing efficiency. It's about doing.

[Summary of the invention]

A group of registers that stores information related to each operand read after an instruction is decoded until the start of execution is hereinafter referred to as an operand read register group.

In the present invention, a two-dimensional matrix-configured latch group (hereinafter referred to as an OSC latch group) is provided corresponding to each of the store address register group, that is, the OSC detection circuit group and the operand read register group,
Upon an operand read request, the OSC detection results are set in all latches in the OSC latch group corresponding to the operand read register activated by the read request. On the other hand, when a store operation is completed, all latches in the OSC latch group corresponding to the store address register related to the store operation are reset.

Further, in the present invention, means is provided for reading out the logical sum of the values of all the latches in the OSC latch group corresponding to each operand read register, and this read value is reported to the operand reread control circuit.
This report signal becomes "0" after all store operations that generated an OSC for the corresponding operand read request are completed.

With these configurations, operands can be read from memory immediately after the OSC is resolved, and even if an OSC occurs, there is no need to suppress operand read requests of subsequent instructions, further improving instruction processing efficiency. This results in an improvement in

[Embodiments of the invention]

FIG. 2 is a block diagram showing one embodiment of the present invention, and corresponds to the control circuit 10 in FIG. In Figure 2, lines 14-1 to 14-n are OSC in Figure 1.
These are OSC detection result lines corresponding to each of the detection circuits 13-1 to 13-n. Since the detection of the OSC is as explained in FIG. 1, it will be omitted here.
15-11 to 15-mn are OSC latch group, 16-
1 to 16-m are OR circuit groups, 17 is a selector, 1
8 is an operand reread control circuit, 19 and 20 are decoders, 21 is a latch, 30 is an operand read control circuit, and 31 is a store control circuit.

Operand read control circuit 30 outputs an operand read request to line 22, and
A pointer is output on line 23 indicating the operand read register (not shown) activated by the operand read request. When the operand read request line 22 is “1”, the decoder 19
The pointer on line 23 is decoded and the control line group 26-
Set one of 1 to 26-m to "1". Control line group 2
6-1 to 26-m correspond to each register of the operand read register group, and "1" of the control line 26-i
indicates that the i-th operand read register is activated (1≦i≦m).

The store control circuit 31 outputs a store operation completion signal to the line 24, and also outputs a store address register group (12-1 to 12-1 in FIG. 1) to which the store belongs.
A pointer indicating the number 2-n) is sent out on line 25. The decoder 20 is connected to the store operation completion signal line 24.
When is “1”, decode the pointer on line 25,
"1" is output to the control line 27-j (1≦j≦n). The store operation completion signal line 24 becomes "1" when all store operations are completed in the store instruction, and at the same time, the corresponding store address register number is indicated on the pointer line 25.

OSC rat groups 15-11 to 15-mn were OSC rats.
This is a collection of latches for storing detection results. Here, OSC latch 15-ij (1≦i≦m, 1≦j
≦n), the subscript j is the store address register 12-
j, that is, corresponds to the OSC detection circuit 13-j,
Subscript i corresponds to operand read register i. OSC latch 15-ij is "1" on line 26-i
Register the OSC detection result of line 14-j by the signal,
It is set by a "1" signal on line 27-j. The OR circuits 16-1 to 16-m are composed of m OR gates corresponding to the operand read register groups. The OR gate 16-i has n OSC latches 1
Outputs the logical sum of 5-i1 to 15-in.

The latch 21 is the operand reread control circuit 18.
Holds the number of the operand read register related to operand read that should report the presence/absence status of the OSC. The selector 17 is an OR gate 16-1~
This is a circuit that selects one output from m outputs of 16-m according to the value of latch 21, and the selection result is shown on line 2.
8 to the operand reread control circuit 18.

Next, the operation shown in FIG. 2 will be explained. When an instruction requiring operand reading is decoded, the operand reading request line 22 becomes "1" and the number of the activated operand reading register is indicated on the pointer line 23. The value of this pointer line 23 is decoded by the decoder 19, and the value of the control line 26-1 is decoded by the decoder 19.
The corresponding line of ~26-m becomes "1". For example, when operand read register k is activated, control line 26-k becomes "1". On the other hand, the OSC of all preceding store instructions and this operand read is determined by the OSC detection circuit 13-
1 to 13-n. The OSC detection results are output to lines 14-1 to 14-n corresponding to store address registers 12-1 to 12-n, respectively.
Registered in OSC latches 15-k1 to 15-kn.
For example, read operand of operand read register k and store address register 12-l.
between the addresses of store instructions stored in
If OSC occurs, OSC latch 15−kj
"0" is set in (1≦j≦n, j=≠l), and "1" is set in the OSC latch 15-kl. At this time, latch 21 takes the value k, and the output of OR gate 16-k passes through selector 17 to line 2.
8 is selected. When the line 28 is "1", the operand reread control circuit 18 suspends reading and waits for execution. During this time, if an instruction involving a subsequent operand read is decoded, the operand read control circuit 30 sets the operand read request line 22 to "1", outputs the number of the activated operand read register to the pointer line 23, and Starts OSC detection.

On the other hand, store address register 12-j (1≦
The store instructions at the addresses stored in j≦n are executed in order according to the instruction execution order specified by the program. Store address register 1
After execution of the instructions stored in 2-l starts,
When all the store operations are completed, the store operation completion signal line 24 becomes "1". At this time, the pointer line 25 indicates l, and the decoder 20 sets the control line 27-l to "1". As a result, m
OSC latches 15-11 to 15-ml are reset. Therefore, the line 28 changes from "1" to "0", and the operand readout that has been in a waiting state is executed again by the operand rereading control circuit 18. At the same time, the number of the next activated operand read register is set in the latch 21, and the OSC detection result is sent to the selector 17.
becomes selectable.

In the above example, a case has been described in which one preceding store instruction and OSC are issued at the time of an instruction operand read request, but the same applies to the case where a plurality of preceding store instructions and OSC are issued. Synchronize and respond to the completion of the store operation of a store instruction
The OSC latch 15-ij is reset in order and the OSC
When all the store operations that caused the .

〔Effect of the invention〕

According to the present invention, a group of latches (OSC group) having a two-dimensional matrix configuration is provided, and when an operand read request is made, the OSC detection result is set to all latches in the OSC latch group corresponding to the operand read request. By resetting all the latches in the OSC latch group corresponding to the store operation when the store operation is completed, the corresponding operand can be read out from the memory immediately after the OSC is cleared, that is, as shown in FIG. This enables ideal operation and improves instruction processing efficiency. Furthermore, the two-dimensional matrix structure
By providing a group of OSC latches, it is possible to start OSC detection for a subsequent instruction with an operand read even during a period when an OSC occurs in a preceding operand read instruction and that operand read is pending. This also leads to an improvement in instruction processing efficiency.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional configuration example, Figure 2 is a block diagram showing an example of a conventional configuration.
FIG. 3 is a block diagram of an embodiment of the present invention, FIG. 3 is a diagram showing an example of the configuration of a control circuit of the prior art, and FIG. 4 is a diagram illustrating problems of the prior art. 1... Address adder, 3... Address register, 4... Operand length control circuit, 7... Operand length adder, 12-1 to 12-n... Store address register group, 13-1 to 13-n ……
OSC detection circuit group, 15-11 to 15-mn...
OSC latch group, 17... Selector, 18... Operand reread control circuit, 19, 20... Decoder, 30... Operand read control circuit, 31
...Store control circuit.

Claims (1)

[Scope of Claims] 1. An information processing device that adopts a proactive control method, comprising: n preceding store address registers that store store addresses of preceding store instructions; n OSC detection that compares with each preceding store address of n preceding store address registers to detect that the operand read in advance from the storage area is changed by a preceding store instruction (hereinafter referred to as OSC) an m×n OSC that holds the detection results of the OSC detection means corresponding to each of the m preceding Oherand reads and the n preceding store-related instructions;
a group of latches; upon completion of a store operation, one of the m×n OSC latch groups corresponding to the store instruction;
write control means for resetting the OSC latches; m OR circuits for ORing the outputs of the n latches corresponding to each operand read in the m×n OSC latch group; A selector that selects the output of the OR circuit corresponding to the next operand read to be executed, and, if the output of the selected OR circuit indicates OSC, suppresses the read of the operand until it is reset. 1. An information processing device comprising: readout control means.