JPH0552580B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a tracking control device, and more particularly, to a tracking control device that circulates pilot signals of different frequencies to recording tracks formed sequentially in a row across the running direction on a recording medium. This is an automatic track following method (hereinafter referred to as the ATF method) in which a pilot signal is recorded along with a video signal, and during playback, the playback head is tracked to a predetermined track by detecting the difference in frequency between pilot signals reproduced from adjacent tracks. This is suitable for application to a tracking control device.

[Background technology and its problems]

A four-frequency type tracking control device has been proposed in which pilot signals of four frequencies are sequentially recorded on a recording track, but due to the relationship between the tracking error signal and the amount of tracking position deviation, The tracking state is shown in Figure 1. That is, considering the case where the tracking pitch and the head width are approximately equal, the error signal S3 becomes 0 at the phase lock point T0, and at this time the reproducing head is controlled to a correct tracking state. On the other hand, if the reproducing head causes tracking deviation in the positive direction, the amount of tracking deviation increases at a positive slope until it reaches one track pitch, that is, the adjacent track T1. The amount of increase is track T
1, the tracking deviation amount increases by 2 track pitches (T
1 to T3), the error signal S3 decreases with a negative slope, reaches 0 at the position of track T2, and then becomes a negative value. This amount of decrease reaches a negative minimum value at the track T3 position, and when the tracking deviation amount passes this position T3, the error signal increases again with a positive slope for two track pitches, and eventually the error signal reaches the position T4. becomes 0. Thus, a change in the error signal causes a change for one cycle during the tracking deviation T0 to T4 of the track pitch, and as the tracking deviation increases thereafter, this cycle of every four track pitches is repeated.

In response to such changes in the error signal, the tracking control system controls the playback head so that if the error signal increases in the positive direction at the lock position T0, the tracking position deviation amount decreases, or if the error signal decreases in the negative direction. As the time progresses, the playback head is controlled to reduce the amount of tracking deviation. Therefore, the reproducing head will be locked at the phase position T0 where the error signal becomes zero. On the other hand, the error signal also becomes 0 at the phase position T2, but if the error signal slightly increases in the positive direction or decreases in the negative direction from the phase point T2, the amount of tracking deviation increases. Because the reproduction head is controlled, it cannot be a stable point (this is called an oscillation point).

Generate an error signal that changes like this
As an ATF type tracking control device, those shown in FIGS. 2 to 4 have been proposed in principle.

That is, as shown in FIG. 2, this tracking control device receives a signal S1, a part of the playback output of a rotating video head as a recording/playback head, through a pilot signal detection circuit 1 having a low-pass filter configuration, and records the signal on a magnetic tape as a recording medium. A reproduced pilot signal S2 whose component is the reproduced output of the pilot signal being reproduced is generated, and this reproduced pilot signal S2 is applied to the error signal forming circuit 3. The error signal forming circuit 3 sends out a tracking error signal S3 (FIG. 1) formed under the control of the reference signal generating circuit 4.

On the tape 5, as shown in FIG.
₁ , ₂ , ₃ , _{and 4} are recorded together with the video signal on four video tracks T1, T2, T3, and T4.
The sets are formed closely diagonally so that they repeat in a cyclical manner. Here, the effective width of the video head constituting the recording/reproducing head 6 is, for example, a track T1.
~T4 width is selected to be approximately equal to the width of the reproducing head 6 as shown by the solid line in FIG.
If the track that is currently being scanned for playback (this is called the playback track) is correctly tracked, only one pilot frequency component will be included in the playback output by playing back only the pilot signal recorded on that track. , on the other hand, as shown by the broken line, the head 6 is
When the track is shifted to the right or left, the pilot frequency component included in the playback output is reduced to 2 by also playing back the pilot signal recorded on the track adjacent to the right or left side of the playback track.
In addition, the magnitude of each pilot frequency component is made to correspond to the opposing length of the reproducing head facing the corresponding track.

However, the frequencies of the four types of pilot signals ₁ ~
₄ is selected for the lower band of the color component converted to a low frequency (600 to 700 [kHz]), and in the circulating four tracks T1 to T4, for example, the right side centering on odd numbered tracks T1 and T3 is selected. The frequency difference with the pilot signal of the track is _ΔA , and the frequency difference with the pilot signal of the left track is _ΔB . The frequency difference with the pilot signal of the left track is _ΔB , and the frequency difference with the pilot signal of the left track is _ΔA .

Therefore, head 6 is connected to odd-numbered tracks T1 and T.
3, if there is a signal component with a frequency difference of _ΔA as a frequency component of the pilot signal included in the reproduced signal, it is known that the head 6 is shifted to the right, and if there is a signal component with a frequency difference of _ΔB. If there is a component, it can be seen that the head 6 is shifted to the left, and if there is no signal component with a frequency difference of _ΔA and _ΔB , it can be seen that tracking is correct.

Similarly, head 6 is an even-numbered track T.
2. When reproducing T4, if there is a signal component with a frequency difference of Δ _B as a frequency component of the pilot signal included in the reproduced signal, it can be seen that the head 6 is shifted to the right, and if the frequency difference is Δ _A If there is a signal component of , it can be seen that the head 6 is shifted to the left.

In this embodiment, the frequencies 1, 2, 3, and 4 assigned to the first, second, third, and fourth tracks _T1 , _T2 , _T3 , and _T4 are ₁ = 102 [kHz],
₂
= 116 [kHz], ₃ = 160 [kHz], ₄ = 146 [kHz]
Therefore, the difference frequencies Δ _A and Δ _B are Δ _A = | ₁ − ₂ | = | ₃ − ₄ | = 14 [kHz]
...(1) Δ _B = | ₂ − ₃ | = | ₄ − ₁ | = 44 [kHz]
...(2) has been selected.

A reproduced signal S1 having such content obtained from the head 6 is given to a pilot signal detection circuit 1 having a low-pass filter configuration, and a reproduced pilot signal S2 obtained by extracting the pilot signal contained in the reproduced signal S1 is sent to a multiplication circuit 14. It is given as the first multiplication input. The reference pilot signal S11 of the reference signal generating circuit 4 is applied to the multiplication circuit 14 as a second multiplication input.

The reference signal generating circuit 4 includes a pilot signal generating circuit 16 that generates four types of pilot frequency outputs of frequencies ₁ to ₄ , and a rotating drum (not shown) in which the head that scans the tape is connected to a rotating drum (not shown). A switch circuit 17 receives a head switching pulse RF-SW (FIG. 4A) which changes the logic level each time it switches. In this embodiment, the switch circuit 17 has a quaternary counter circuit that performs a counting operation every time the level of the head switching pulse RF-SW changes. The corresponding gate signals are sequentially repeated, and the gates are opened by the gate signals of tracks T1 to T4 to sequentially output the pilot frequencies ₁ to ₄ of the pilot signal generating circuit 16 as shown in FIG. 4B. It is designed to be sent out as a reference pilot signal S11.

Note that the reference pilot signal S11 obtained at the output end of this switch circuit 17 is sent to the video head 6 as a recording pilot signal S4 via the signal line 18 during recording, and thus the video head 6 selects the first to fourth tracks T1. While scanning tracks T1 to T4, pilot signals of corresponding frequencies ₁ to ₄ are sequentially applied to the video head 6 to scan each track T1 to T4.
It is configured to record on T4.

In this way, while the head 6 scans the first to fourth tracks T1 to T4, the reproduced pilot signal S2 obtained at the output terminal of the pilot signal detection circuit 1 is generated in synchronization with the reproduced track. By multiplying the reference pilot signal S11 by the frequency component contained in the reproduced pilot signal S2 when there is a tracking error,
A multiplication output S12 is obtained which includes a signal component having a frequency different from the frequency of the reference pilot signal S11 (actually, the multiplication output S12 also includes other signal components such as the sum frequency component). This multiplication output S12 is given to first and second difference frequency detection circuits 20 and 21, each of which is constituted by a bandpass filter. First difference frequency detection circuit 20
When the multiplication output S12 includes a signal component with a difference frequency _ΔA based on equation (1) above, this is extracted and converted to DC by the DC conversion circuit 22 having a peak detection circuit configuration, and the signal component of the DC level is 1 error detection signal S1
Get 3. Similarly, when the multiplication output S12 includes a signal component of the difference frequency _ΔB based on the above-mentioned equation (2), the second difference frequency detection circuit 21 extracts this and sends it to the DC converting circuit 23. An error detection signal S14 is obtained.

Here, when the head 6 is about to track the first, second, third, and fourth tracks T1, T2, T3, and T4 (therefore, the switch circuit 17 tracks each track T1, T2, as shown in FIG. 4B). ,T
3. The frequency becomes ₁ at the timing corresponding to T4,
₂ , ₃ , and ₄ )) If it is shifted to the right, the reproduced pilot signal S2 obtained based on the reproduced signal S1 of the head 6
As shown in Figure 4 C1, the frequencies ₁ and ₂ , ₂ and
The pilot signals of ₃ , ₃ and ₄ , ₄ and ₁ are included, and the multiplication output S12 is shown in Fig. 4D.
As shown in 1, the difference frequencies Δ _A (= ₁ to ₂ ) and Δ _B
(= ₂ to ₃ ), Δ _A (= ₃ to ₄ ), Δ _B (= ₄
~ ₁ ) is generated sequentially. On the other hand, head 6
is shifted to the left, the reproduced pilot signal S2 sequentially includes pilot signals of frequencies ₄ and ₁ , ₁ and ₂ , ₂ and ₃ , ₃ and ₄ as shown in FIG. As shown in FIG. 4 D2, the multiplication output S12 has a difference frequency Δ _B (= ₄ to ₁ ),
Δ _A (= ₁ to ₂ ), Δ _B (= ₂ to ₃ ), Δ _A (
= ₃ ~ ₄ )
will gradually be included.

Thus, as shown in FIGS. 4E and F (for example, showing a right-shifted state), each time the head 6 switches tracks scanned, the DC level rises from 0.
And second error detection signals S13 and S14 can be obtained from the DC converting circuits 22 and 23.

First and second error detection signals S13 and S1
4 are applied to the subtraction circuit 24 as an addition input and a subtraction input, respectively, thereby producing the first and second error detection signals S13 and S1 as shown in FIG. 4G.
4 is obtained alternately, a subtraction output S15 that changes in an alternating current manner is obtained. This subtracted output S15 is applied to the first input terminal a1 of the direct changeover switch circuit 25, and its polarity is inverted in the inverting circuit 26 and applied to the second input terminal a2. The changeover switch circuit 25 switches the head 6, for example, to odd-numbered tracks T1 and T3 by the head changeover pulse RF-SW.
When scanning the first input terminal a1, the even numbered tracks T2 and T4 are switched to the first input terminal a1 side.
When the head 6 is being scanned, it is switched to the second input terminal a2, and thus, when the head 6 is shifted to the right as shown in FIG. (on the other hand, in the leftward shift state, the DC level output S16 has a magnitude corresponding to the leftward shift amount and becomes negative polarity),
This signal is sent out as a tracking error signal S3 via an output amplification circuit 27 consisting of a DC amplifier.

Incidentally, if the head 6 is shifted to the right, for example, a signal component of the difference frequency _ΔA appears at the output terminal of the multiplier circuit 14 when the reproduced track is an odd numbered track T1, T3, so that the signal component of the difference frequency ΔA appears on the first difference frequency detection circuit 20 side. The output S13 is given to the subtraction circuit 24, and since the changeover switch circuit 25 is switched to the first input terminal a1 at this time, it sends out a tracking error signal S3 of a positive DC level. On the other hand, when the reproduced track is an even numbered track T2, T4, a signal component of the difference frequency _ΔB appears at the output terminal of the multiplication circuit 14, so that the output S14 from the second difference frequency detection circuit 21 side is transmitted to the subtraction circuit 24. , and at this time, the changeover switch circuit 25 is switched to the second
Since the input terminal a2 of the subtraction circuit 24 is switched to the input terminal a2 side, the polarity of the negative output of the subtracting circuit 24 is inverted by the inverting circuit 26 and sent as a tracking error signal S3 of a positive DC level.

Therefore, if this tracking error signal S3 is used as a correction signal in the phase servo circuit of the capstan servo loop and corrected so that the tape running speed is slowed down when it is positive and increased when it is negative, the video head and playback speed are corrected. It can correct the phase shift with the track,
In this way, a correct ATF tracking servo can be realized.

In the above principle configuration, the principle has been described assuming that when the head 6 correctly tracks each track, no difference frequency component is generated at the output terminal of the multiplication circuit 14. However, in reality, even in this tracking state, the reproduced signal S1 of the head is Pilot signals for adjacent tracks on the left and right sides are generated.

That is, in practice, when guard bands are not provided between tracks during recording, newly recorded tracks are sequentially recorded in the recording mode so as to partially overlap already recorded adjacent tracks. Therefore, in this case, the width of the head 6 is larger than the width of the tracks T1 to T4, so that when tracking correctly, the head 6 protrudes into the adjacent tracks on the left and right sides. Therefore, since the head 6 reproduces the pilot signals of the tracks adjacent to the left and right sides, the error detection signals S13 and S corresponding to the signal components of the difference frequencies corresponding to the length of the overhang are generated.
14 (Fig. 4 E and F) to DC converting circuits 22 and 2
It occurs from 3.

Furthermore, when a card band is provided, the width of the head 6 becomes almost equal to the width of the track, but the pilot signals recorded on the adjacent tracks on the left and right sides are mixed into the reproduced signal of the head 6 as a crosstalk signal. do. Therefore, the error detection signal S1
3 and S14 include a signal component of a difference frequency corresponding to a crosstalk signal.

However, since the pilot signals mixed into the reproduced output S1 of the head 6 from the adjacent tracks are simultaneously generated at the output terminal of the multiplication circuit 14 as signal components with difference frequencies _ΔA and _ΔB , the error detection signals S13 and S14 are When they are subtracted from each other in the subtraction circuit 24, they cancel each other out. Moreover, when the head 6 is tracking correctly, the head 6 is in a symmetrical position with respect to the tracks adjacent to the left and right sides.
The protrusion lengths of the left and right sides are almost equal, and the magnitude of the crosstalk is also almost the same for the left and right sides.In the end, the content of the subtraction output S15 is equivalent to the above case in which the width of the head 6 is considered to be almost equal to the width of the track, and Therefore, the tracking operation of the tracking control device is not adversely affected by the difference frequency components occurring simultaneously from the adjacent tracks on both sides, due to the head width being larger than the track width or due to crosstalk.

Note that in the above-mentioned error signal forming circuit 3,
The error detection signals S13 and S14 are obtained based on the signal components of difference frequencies _ΔA and _ΔB between the pilot signals of the reproduced track and its adjacent tracks _.
The levels of _{the four} reproduced pilot signals may be detected by respective reproduced pilot signal detection circuits each having a bandpass filter configuration, and the error detection signals S13 and S14 may be obtained based on the detection outputs.

In the above configuration, for example, if we consider the timing when the reference pilot signal S11 in FIG. 4B sends out a pilot signal of frequency ₁ ,
When the head 6 is at the phase lock position T0 (FIG. 1) where it is tracking correctly, the content of the reproduced pilot signal S2 is frequency ₁ , so the output S12 of the multiplier circuit 14 has the difference frequencies _ΔA and _ΔB. None of these are included. If the reproducing head 6 causes a tracking deviation in the positive direction from this state, the reproducing head 6 will come to face the track T2, so a component of frequency ₂ will be generated in the reproducing pilot signal S2, and this will cause a tracking deviation in the track T2 according to the amount of tracking deviation. As _the opposing area of As the component Δ _A goes from the phase position T0 through T1 to the T2 position, it gradually becomes larger, passes through the maximum value, and then becomes smaller. Accordingly, the error signal S3
The value increases in the positive direction, passes through the maximum value, and decreases as shown in FIG. 1.

When the reproducing head 6 eventually comes to face the track T4, a frequency component ₄ is generated in the reproducing pilot signal S2, and as the head moves from the T2 position to the T4 position through the T3 position, the magnitude of the frequency component ₄ increases. gradually increases through the maximum value and decreases, so that the output S12 of the multiplication circuit 14 has a frequency component of _ΔB , and thus the error signal S3 moves from point T2 to T3 as described above with respect to FIG. It decreases in the negative direction as it passes through T4, and then increases through the minimum value.

In this way, in a 4-frequency ATF type tracking control device, there is one lock position for each of the four tracks. (intime) is quite large.

Incidentally, conventionally, a fixed head records a pulse signal whose polarity is reversed for each vertical synchronization signal of the television signal (therefore, for each track) as a control pulse signal (CTL signal) along the tape feeding direction. A so-called CTL tracking servo system, which performs tracking control using this CTL signal, has been used. In this case, the change in the tracking deviation amount of the error signal is shown in FIG. 5 as shown in FIG.
When tracking deviations occur such as 0, T1, T2, T3..., lock points T0, T2... will occur alternately with oscillation point T3..., thus one lock occurrence will occur for two tracks. It turns out. Therefore, if we compare the case of the CTL method shown in Figure 5 and the case of the ATF method shown in Figure 1, we get
If the time constant characteristics of the servos are selected to be equal to each other, the lock-in time of the ATF method will probabilistically require twice the lock-in time of the CTL method.

[Purpose of the invention]

The present invention has been made in consideration of the above points, and
The aim is to shorten the lock-in time of the ATF servo control device as much as possible, thereby making it possible to stably execute the servo operation of the ATF servo system.

[Summary of the invention]

In order to achieve this purpose, the present invention includes:
When the difference frequency component occurring in the multiplied output of the reproduced pilot signal and the reference pilot signal is not within a predetermined lock-in range, a lock-in error detection signal is generated from the lock-in error detection circuit, and the circulation order of the reference pilot signal is determined by the detection output. By skipping the lock-in time by a predetermined number of steps by the skip control circuit, the lock-in time can be shortened by the skipped amount, and it is also possible to check whether or not the ATF servo system has responded to the skip operation. to be executed as a permissible condition.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to FIG. 6, in which parts corresponding to those in FIG. 2 are denoted by the same reference numerals. The tracking control device of FIG. 6 has an error signal forming circuit 3 and a corresponding switch circuit 17 as in the case of FIG. 2, as well as an oscillation point detection circuit 31 and an oscillation point detection switch circuit 32 corresponding thereto. Similar to the error signal forming circuit 3, the oscillation point detection circuit 31 converts the reproduced pilot signal S2 of the pilot signal detection circuit 1 into a multiplier circuit 35.
The multiplication output S21 is applied to a _ΔA detection circuit 36 and a _ΔB detection circuit 37 having a bandpass filter configuration, and the detection outputs are converted to DC level in DC conversion circuits 38 and 39, respectively, and then applied to a subtraction circuit 40. Subtraction output S2 of the subtraction circuit 40
2 is directly connected to the contact a1 of the switch 41 and is applied to the contact a2 via the inverter 42,
The switch output S23 is applied to the level detection circuit 44 through the amplifier circuit 43 as an oscillation point error signal S24.

The output of the threshold level voltage source 45 is given as a reference signal to the level detection circuit 44, and the oscillation point error signal S24 given from the amplifier 43
When the level of S25 becomes higher than the output of the threshold level voltage source 45, the oscillation point detection signal S25 is sent to the skip judgment circuit 50, and the judgment output 26 obtained at its output terminal is passed through the hold circuit 46 to form an error signal. It is given as a skip signal S27 to the switch circuit 17 of the circuit 3 and the oscillation point detection switch circuit 32. Here, the hold circuit 46 is a flip-flop circuit, and the skip judgment circuit 50
Each time the determination output 26 rises from the logic "L" level to "H", the set operation is repeated to invert the logic level of the skip signal S27.

In this embodiment, the switch circuit 17 has a switch circuit main body 17A that receives pilot signals ₁ to ₄ from the pilot signal generation circuit 16, receives a head switching signal RF-SW as a switching condition signal, and also receives this head switching signal RF-SW. 1/2 frequency divider circuit 1
After frequency division at 7B, contact a of switch 17C
1 to the switch circuit main body 17A as a second control condition signal SEL2. Here, the first control condition signal SEL1 changes in the same way every time the logic level of the head switching signal RF-SW changes (Fig. 7), whereas the second control condition signal SEL2 changes in the same way every time the logic level of the head switching signal RF-SW changes. Since the logic level changes at twice the period of the condition signal SEL1, these two logic signals cause the switch circuit main body 17A to change the frequency when the logic is from "11" to "00" as shown in FIG. Outputs ₁ to ₄ are sent out as a reference pilot signal S11.

On the other hand, the oscillation point detection circuit 32 has a switch circuit main body 32A having the same configuration as the switch circuit main body 17A of the switch circuit 17, and sends the head switching signal RF-SW to the inverter 32B as the first control condition signal SEL1. Reverse and receive (7th
figure). The output S29 of this inverter 32B is given to a 1/2 frequency divider circuit 32C, and as shown in FIG.
The 1/2 frequency divided output S30, which rises to logic "H" level in response to the rise of signal S29 and falls to logic "L" level in response to the next rise of signal S29, is sent to the switch circuit body through contact a1 of switch 32D. 3
It is given as a control condition signal SEL2 of 2A.

Thus, as shown in FIG. 7, the switch circuit body 32A receives the control condition signal "00" and detects the oscillation point of the pilot signal of frequency ₄ when the control condition signals SEL1 and SEL2 for the switch circuit body 17A are logic "11". When the control condition signal to the switch circuit main body 17A is "01", a pilot signal of frequency ₁ is sent as the reference pilot signal S31 in response to the control condition signal "11". When the control condition signal for the switch circuit 17A is "10", the control condition signal "01" is received and a pilot signal of frequency ₂ is sent out as the reference pilot signal S31, and the control condition signal for the switch circuit main body 17A is "00".
When the control condition signal "10" is received, the pilot signal of frequency ₃ is sent out as the reference pilot signal S31.

However, the reproduction reference _pilot signal S11 of the switch _circuit main body 17A represents the frequency sequence of the pilot signal recorded on the tape, and its content is as shown by the solid line arrow in _{FIG .} → ₁ indicates that the pilot signals are recorded in the following order. On the other hand, as is clear from FIG. 7, the reference pilot signal S31 for oscillation point detection has a frequency of 1/1 with respect to one circulation period of the reference pilot signal S11 for reproduction.
The frequencies are switched in an order delayed by four circulation periods. This means that the capstan phase error signal S3 can be obtained as shown by the solid line in FIG. 10 by using the reproduction reference pilot signal S11 having the frequency switching order shown in FIG. The frequency switching order of the reference pilot signal S31 for oscillation point detection shown in the figure is as shown by the broken line in FIG. Delayed phase error waveform K
Based on the relationship shown in 2, the oscillation point detection error signal S
This means that you can get 24.

In other words, by doing this, the maximum value of the waveform K2 (Fig. 10) of the oscillation point detection phase error signal S24 will be at the phase position where the reproducing phase error waveform K1 (Fig. 10) crosses the 0 point while decreasing in the negative direction. (that is, the oscillation point phase position) can be obtained at T2, T6..., so if you use this to select the value of the threshold level power supply 45 of the level detection circuit 44 to the level SH shown in FIG. 10, The level detection circuit 44 outputs the error signal S of the error signal forming circuit 3.
3 enters the range of ±α across the oscillation points T2, T6..., the error signal S24 exceeds the threshold level SH, so the oscillation point detection signal S25 is sent out within this range of 2α. That will happen. This means that the content of the reproduced pilot signal S2, as shown by the dotted arrow in FIG.
When switching in the order of ₁ → ₂ → ₃ → ₄ → ₁ , the oscillation point detection circuit 31 reproduces the regenerated pilot signals S at every other frequency, that is _{, 3} , ₄ , ₁ , ₂ , and ₃ .
2, an oscillation point detection signal S25 is sent out.

The skip permission determination circuit 50 receives the oscillation point detection signal S.
25 as a data input, and an output permission determination circuit 52 having a 5-input AND circuit configuration that receives the stored contents of each bit as an input condition. As the write clock signal S28 for the circuit 51, the output pulse of the write clock forming circuit 53 having a monomultivibrator configuration is obtained.

Here, the write clock forming circuit 53 is activated by the rise and fall of the head switching signal RF-SW when it rises from the logic level "L" to "H" and when it falls from "H" to "L". The logic level of the oscillation point detection signal S25 is written into the judgment data storage circuit 51 by the write clock signal S28 each time the switching signal RF-SW is triggered. The oscillation point detection results in the oscillation point detection circuit 31 during the past five 1/2 cycle sections (therefore, the section in which the playback head scanned tracks for the past five fields) are stored in the judgment data storage circuit 51. is being done.

Here, the level detection circuit 44 has its head at the oscillation point T.
The level detection signal S25, which rises to logic "H" when the head deviates from the phase range 2α (Fig. 10) including 2, T6, etc., is set to logic "H", and when the head deviates from the track to other phase ranges. The oscillation point detection signal S25 is set to logic "L", thereby causing the judgment data storage circuit 51 to set all bits to logic level when the head has been track-shifted near the oscillation point for the past five fields. "H"
The detection data of is stored.

At this time, all the input signals of the output permission determination circuit 52 become logic "H", so that the skip signal S27 of logic "H" is outputted from the output terminal.

On the other hand, if there is a section in which the oscillation point detection signal S25 becomes logic "L" during scanning for the past five fields, the output of the output permission determination circuit 52 cannot become logic "H", and thus Skip operation is not allowed.

The skip signal S27 sent from the hold circuit 46 in this way is transmitted to the switch 17C of the regeneration switch circuit 17 and the switch 32 of the oscillation point detection switch circuit 32, which constitute the skip control circuit.
D as a switching signal. The frequency divided output S27 of the 1/2 frequency divider circuit 17B is inverted and applied to the switching terminal a2 of the switch 17C by the inverter 17D, and thus when the skip signal S27 arrives, the switch 17C switches from terminal a1 to a2. This inverted signal is given to the switch circuit main body 17A as the control condition signal SEL2. Similarly, the switching terminal a2 of the switch 32D of the oscillation point detection switch circuit 32 is connected to the divided output S of the 1/2 frequency dividing circuit 32C.
30 is inverted and given by an inverter 32E, and when the skip signal S27 arrives, this inverted signal becomes the control condition signal of the switch circuit main body 32A.
Given as SEL2.

In this way, the switch circuit bodies 17A and 32A
The control condition signal SEL2 is the skip signal S2.
7, the logic level is inverted, and as is clear from FIG.
It means to advance or delay by one minute period. For example, when control condition signals of logic "11" and "00" are applied to the switch circuit bodies 17A and 32A, respectively, the frequencies of the pilot signals S11 and S31 are ₁ .
and ₄ . In this state, the control condition signal
If the logic level of SEL2 is inverted, control condition signals of logic "10" and "01" will be given to the switch circuit bodies 17A and 32A, respectively, so the frequency of the pilot signals of the reference pilot signals S11 and S31 will be It will be switched to ₃ and ₂ .

In this way, the reference pilot signals S11 and S3
When the frequency of one head is switched, the tracking control device sets the capstan servo system to a state in which the tracking phase is skipped by 1/2 cycle period (i.e., a state in which the adjacent track with one head is tracked). Control.

In the configuration shown in FIG. 6, when the tracking control device is in the lock-in state, the signals of each part become as shown in FIG. 11. That is, the circulation order of the pilot frequency of the reproduction reference pilot signal S11 (FIG. 11B) is synchronized with the circulation order of the pilot frequency of the reproduction pilot signal S2 (FIG. 11D), and the oscillation point detection reference pilot signal S31
The circulation order of the pilot frequency (FIG. 11C) is delayed by 1/4 period with respect to the circulation order of the pilot frequency of the reproduced pilot signal S2. Therefore, the difference frequency component of the pilot signal does not occur in the multiplication output S12 of the error signal forming circuit 3 (the 11th
Therefore, the error signal S3 of the error signal forming circuit 3 (FIG. 11G) becomes 0. On the other hand, the multiplication output S21 (FIG. 11F) of the oscillation point detection circuit 31 indicates that when the pilot frequency of the reproduced pilot signal S2 is ₁ , ₂ , ₃ , ₄ , the pilot frequency of the reference pilot signal S31 is ₄ , 1, ₄ . ₂ , ₃ , the difference frequency components _ΔB , _ΔA , _ΔB , _ΔA are obtained, and as a result, the oscillation point detection signal S24
The level becomes negative as shown in FIG. 11H. In this case, since the oscillation point error signal S24 of the level detection circuit 44 has not exceeded the threshold level SH, the output signal S25 of the level detection circuit 44 does not become logic "H", and thus the skip signal S27 is sent out. Not done. As a result, the tracking control device as a whole continues the tracking control operation.

On the other hand, when the tracking control device starts operating, as shown in FIGS. 12B and 12D, the pilot frequency of the reproducing pilot signal S2 changes with respect to the circulation of the pilot frequency of the reference pilot signal S11 sent from the reproducing switch circuit main body 17A. is 1/2
If the capstan servo system is started at the oscillation point position of the tracking control device (phase position T2 in FIG. 10) with a difference in cycle period, then Since the difference frequency component of the output S12 (FIG. 12E) does not deviate from _ΔA or _ΔB , the error signal S3 (FIG. 12G) maintains the 0 level.
On the other hand, the multiplication output S2 of the oscillation point detection circuit 31
1 (FIG. 12F), difference frequency components _ΔA , _ΔB , _ΔA , and _ΔB are generated at the timing when the reproduced pilot signal S2 reaches the pilot frequencies ₁ , ₂ , ₃ , and ₄ , so an oscillation point error signal is generated. The level of S24 takes the maximum value (FIG. 12H). Therefore, since the oscillation point error signal S24 has exceeded the threshold level SH, the level detection circuit 44 sends out the oscillation point detection signal S26 of logic "H" level.

The logic level of this oscillation point detection signal S26 is "H"
is written to the first stage when the write clock signal S28 is applied from the write clock forming circuit 53 to the judgment data storage circuit 51 at the rising or falling edge thereof when the head is switched.

However, when the head is at the oscillation point position T2, the error signal forming circuit 3 outputs the 10th signal.
As described above with respect to the curve K1 in the figure, an error signal S3 is sent that causes the head position to track to the resonance point position T0 or T4. ) to variably control the running of the tape. However, in reality, the ATF phase servo system including the capstan motor is composed of a mechanical servo loop, so its response characteristics depend on the head switching frequency (i.e., the head switching signal).
It is very slow compared to the frequency of RF-SW (30H [Hz]), at most a few [Hz].

Therefore, from the state where the head is at the oscillation point position until the servo rises and the head actually moves away from the oscillation point position and begins to move toward the lock-in state, the head must repeatedly scan the same track for at least several fields. As a result, the oscillation point detection signal S25 sent from the oscillation point detection circuit 31 while several pulses are given to the judgment data storage circuit 51 from the write clock forming circuit 53.
The level of is maintained at "H".

As a result, when logic "H" data is written in each stage of the judgment data storage circuit 51, the output S26 of the output judgment circuit 52 becomes logic "H".
The skip signal S from the hold circuit 46 rises to
27 is sent out.

At this time, switch 1 of switch circuits 17 and 32
Since terminals 7C and 32D are switched from terminal a1 to a2 side, reference pilot signals S11 and S3
The circulation order of the pilot frequency of S11 is forcibly shifted from the state of FIGS. 12B and C by 1/2 circulation period (FIGS. 13B and C), and the rotation of the pilot frequency of the reproduction reference pilot signal S11 is The order is synchronized with the reproduced pilot signal S2 (FIG. 13D), and the multiplication output S12 (FIG. 13E) no longer produces a difference frequency component, and the error signal S3
(FIG. 13G) maintains the 0 level.
On the other hand, the multiplication output S21 (FIG. 13F is the first
As in the case of Fig. 1, when the pilot frequencies of the reproduced pilot signal S2 are ₁ , ₂ , ₃ , and ₄ , difference frequency components _ΔB , _ΔA , _ΔB , and _ΔA are generated in synchronization with these, so the oscillation point error occurs. Signal S24 (Figure 13H)
becomes a negative level. This state is the 11th
This is the same state as the threshold tracking state described above with respect to the figure, and thus the tracking control device performs tracking control correctly.

In this embodiment, since a hold circuit 46 is provided, even if the oscillation point detection signal S25 cannot be obtained due to the skip operation, the hold circuit 46 continues to output the skip signal S27.
A normal tracking state is maintained by sending the . The hold state of the hold circuit 46 is reset when the recording mode signal REC arrives after the reproduction mode ends and the mode is switched to the recording mode.

The above operation has been described for the case where the tape is at the oscillation point of the tracking control device when the VTR starts playing, but the detection range shown in Figure 10 is not limited to this.
2α, the tracking control device changes the reference pilot signal S for 1/2 cycle period by the same operation as described above with respect to FIGS. 12 and 13.
11 and S31 are skipped.

Therefore, according to the configuration shown in FIG. 6, the lock-in time when the VTR starts playing can be significantly reduced. (Probably, the lock-in time can be reduced by half.) Incidentally, if the skip component shown in FIG. 6 were not present, if the tape position at the start of playback was at the oscillation point T2 in FIG. 10, the value of the error signal S3 of the error signal forming circuit 3 would be 0, but it would not be stable. , First, the capstan servo system is mechanically accelerated or decelerated, and thereby the error signal curve rises in the positive direction and crosses the 0 point at the point T0 or T.
In contrast, according to the configuration shown in FIG. 6, by electrically skipping the pilot reference signals S11 and S31 at the start of playback, the tracking control device is immediately brought into a stable state. It can be locked into the servo.

In addition, in this way, even if, for example, pulse-like noise is mixed into the oscillation point detection signal S25 of the level detection circuit 44, there is no possibility that the switch circuit bodies 17A and 32A will be erroneously caused to perform a skip operation. Incidentally, if the oscillation point detection signal S25 is directly given as a skip signal to the switches 17C and 32D, for example, at the initial startup of the VTR, even though the head is not located at or near the oscillation point, noise may appear in the output signal S25. If this occurs and the hold circuit 46 performs a hold operation, the reference pilot signals S11 and S31 will be skipped even though the head is near the resonance point, and the head will return to a position far from the resonance point. The lock-in time will become longer.

On the other hand, according to the configuration shown in FIG. 6, even if the oscillation point detection signal S25 temporarily becomes a logic "H", this will not continue for five fields, so the judgment data storage circuit 51 If logic "H" data is not stored in all bits of the head and the head is near the resonance point, the skip permission determination circuit 50 will not allow a skip.
It is possible to quickly enter the lock-in state without disturbing the ATF tracking operation.

In addition, in the case of a VTR that has multiple playback modes with different tape speeds, if playback is started at a tape speed different from the tape speed at the time of recording, the tape speeds will be changed to the same speed using a separate mode switching device. As shown, the ATF error signal S3 and the oscillation point error signal S24 undulate until the playback mode is switched, and if the level of this undulation exceeds the threshold level SH of the level detection circuit 44, the logic level of the output S25 changes. A periodic switching phenomenon occurs. Therefore, the oscillation point detection signal S
If 25 is used as a skip signal without passing through the skip permission determination circuit 50, there is a possibility that a correct skip operation may not be executed.

Regarding the wave of the ATF error signal, please refer to the specification of Japanese Patent Application No. 57-141975 (Japanese Unexamined Patent Publication No. 59-031456).
No.).

Incidentally, when a skip signal is generated periodically, the ATF servo system repeats the lock-in operation each time, so there is a risk that it will enter a kind of oscillation state. However, according to the configuration shown in Figure 6, the threshold level
For example, by selecting SH to be at a relatively high level, the period during which the oscillation point detection signal S25 maintains the logic "H" state can be made to fit within about 2 to 3 fields of the head switching signal RF-SW.
In this way, the oscillation point detection signal S2 is generated based on the waviness.
5 becomes logic "H", this does not cause all the bits of the judgment data storage circuit 51 to become logic "H", and as a result, the reproduction mode is changed to the recording mode by the operation of the skip permission judgment circuit 50. It is possible to prevent the skip operation from being executed unnecessarily when there is no match.

FIG. 14 shows another embodiment of the present invention, in which the configurations of the oscillation point detection circuit 31 and the oscillation point detection switch circuit 32 in FIG.
The purpose of this is to simplify the configuration of the tracking control device by using the following. In this case, the switch circuit main body 17A of the switch circuit 17 is the same as the switch circuit main body 17A in FIG. 6, except that it is controlled by control condition signals SEL1 and SEL2 generated by a switch control circuit 61 having a logic circuit configuration. have the same configuration.

The switch control circuit 61 time-divides the 1/4 circulation period section M into an oscillation point detection section _m1 and a reproduction error signal generation section _m2 as shown in FIG. 15, and for the oscillation point detection section _m1, as shown in FIG. As described above, the control condition signals SEL1 and SEL2 given to the switch circuit main body 32A are set to each pilot frequency ₄ ,
Logical level "00" assigned to ₁ , ₂ , ₃ ,
"11", "01", and "10" are applied to the switch circuit 17A in each 1/4 circulation period section M. On the other hand, the control condition signal given to the switch circuit main body 17A in _FIG .
Set SEL1 and SEL2 to pilot frequencies ₁ , ₂ ,
Logical level "11" assigned to ₃ , ₄ ,
``01'', ``10'', and ``00'' are sequentially given every 1/4 circulation section M.

In this way, the reference pilot signal S42 for the oscillation point detection operation and reproduction error signal generation operation is generated.
is generated in the switch circuit main body 17A in a time-division manner (FIG. 15B). In order to generate such a time division control condition signal, the switch control circuit 61 as a skip control circuit receives a head switching signal RF-.
SW is applied, the frequency is divided by the 1/2 frequency divider circuit 62, and the signal is applied to the switch control circuit 61, and the head switching signal RF-SW is applied to the time division signal generation circuit 63, which is made up of, for example, a mono-multivibrator. Every time the switching signal RF-SW changes its logic level (i.e., rises and falls), the generation circuit 63 is triggered to send a time-sharing signal S41 having a time width corresponding to the oscillation point detection section _m1 to the switch control circuit 61. give.

In addition, in the same way as described above with reference to FIG.
The switch control circuit 61 receives the skip signal S27 generated in the switch control circuit 61 and outputs the reproduction and oscillation point detection control condition signals SEL1 and oscillation point detection in the same manner as in the case of FIG.
SEL2 is formed. Thus, the oscillation point detection/reproduction pilot signal S42 as shown in FIG. 15B is applied from the switch circuit main body 17A to the multiplication circuit 14 of the error signal forming circuit 3.

In this embodiment, the oscillation point detection signal forming circuit 64
The circuit has an amplifier 43 and a level detection circuit 44 as indicated by the same reference numerals in corresponding parts to those in FIG. 6, but the other configurations are the same as those of the error signal forming circuit 3. That is, the multiplication output S12 of the multiplication circuit 14 is obtained by multiplying the pilot reference signal portion for oscillation point detection that arrives in the oscillation point detection section m ₁ (FIG. 15B) of the reference pattern signal S42 by the reproduced pilot signal S2 (FIG. 15C). _The difference frequency signal part x ₁ obtained by
x ₂ (Figure 15D). Thus, the output S16 of the switch 25 of the error signal forming circuit 3 provides an oscillation point detection output portion in the oscillation point detection section _m1 , and this is sampled and held in the sampling and holding circuit 65. On the other hand, the playback error signal generation section of the output signal S16
The signal portion of m ₂ is sampled and held in the sampling and holding circuit 66 of the error signal forming circuit 3.

In this way, the sampling hold circuit 65
The output of is used as the oscillation point error signal S24 via the amplifier circuit 43 of the oscillation point detection signal forming circuit 64, and the output of the sampling hold circuit 66 is sent out via the amplifier circuit 27 as the reproduction error signal S3. In this way, the oscillation point detection interval m ₁
In order to hold the signal portion of the reproduction error signal generation section m ₂ in the sampling hold circuit 65 and hold the signal portion of the reproduction error signal generation section m 2 in the sampling hold circuit 66, the time division signal S41 of the time division signal generation circuit 63 is outputted by the inverter 67. The signal S41 is inverted and given to the sampling and holding circuit 65 as a sampling pulse, and the signal S41 is also given directly to the sampling and holding circuit 66 as a sampling signal.

According to the configuration shown in FIG. 14, the main parts of the error signal forming circuit 3 are configured to obtain an oscillation point detection signal by processing the oscillation point detection operation and the reproduction error signal generation operation in a time-sharing manner. In addition, the switch circuit main body 17A can be shared in the same way. Therefore, according to the configuration shown in FIG. 14, the configuration shown in FIG. 6 can be realized with an even simpler configuration.

FIG. 16 shows still another embodiment of the present invention, in which the oscillation point detection switch circuit 32 of FIG. 6 can be omitted. In this case the 6th
Difference frequency detection circuit 36 of the oscillation point detection circuit 31 shown in the figure
The configuration differs from the configuration shown in FIG. 6 in that a _ΔC detection circuit 71 and a _ΔD detection circuit 72, which are constructed of bandpass filters that pass the difference frequencies _ΔC and _ΔD , are used in place of ΔC and ΔD.

Here, _ΔC and _ΔD are selected as shown in FIG. In Fig. 17, the difference frequency _ΔA between pilot frequencies ₁ and ₂ is selected as a predetermined reference frequency _H , the difference frequency _ΔD between pilot frequencies ₂ and ₄ is selected as _2H , and the difference frequency between pilot frequencies ₄ and ₃ is selected as 2H. The frequency _ΔA is selected to be _H.
Therefore, the difference frequency ΔB between pilot frequencies ₁ to ₄ and ₂ to ₃ is _3H , and the difference frequency _ΔB between pilot frequencies 1 to 4 and 2 to ₃ is 3H.
The difference frequency _ΔC of ₃ becomes _4H . Thus, if there is a difference frequency component of frequencies ₁ to ₂ and ₄ to ₃ in the multiplication output S12, this will be detected through the _ΔA detection circuit 20, and if there is a difference frequency component of frequencies ₁ to ₄ and ₂ to ₃ , this will be detected by Δ It is detected through the _B detection circuit 21, and if there is a difference frequency component of frequencies ₁ to ₃ , this is detected through the _ΔC detection circuit 71.
Furthermore, if there is a difference frequency component of frequencies ₂ to ₄ , this will be detected through the _ΔD detection circuit 72.

In the configuration shown in FIG. 16, when the tracking control device is performing normal tracking operation, as shown in FIG. 18B), and therefore the multiplication output S of the multiplication circuit 14
12 (FIG. 18D), no difference frequency component occurs. Therefore, since no detection output is obtained from the detection circuits 20, 21, 71, and 72, the error signal S3 (E in FIG. 18) of the error signal forming circuit 3 maintains the 0 level and the oscillation of the oscillation point detection circuit 31 is suppressed. The point error signal S24 (FIG. 18F) also maintains the 0 level.

On the other hand, if the playback head is located at the oscillation point of the tracking control device at the time when the VTR starts playback operation, the circulation order of the pilot frequencies of the playback pilot signal S2 (Fig. 19C) will be the standard. 1/2 for the circulation order of the pilot frequency of the pilot signal S11 (Fig. 19B)
Since the phase is delayed by a circulation period (that is, two tracks), the multiplication output S12 (FIG. 19D) has the pilot frequency ₁ of the reference pilot signal S11,
Δ _C , Δ _D , Δ _C when ₂ , ₃ , and ₄ occur, respectively
，
A difference frequency signal of _ΔD is generated, which is detected by the detection circuits 71 and 72, and as a result, the oscillation point error signal S24 of the oscillation point detection circuit 31 is generated.
(FIG. 19F) exceeds the threshold level S _H of the level detection circuit 44 and becomes the maximum value. Therefore, a skip signal S27 is sent from the hold circuit 46, and the switch 17C of the switch circuit 17 is connected to the contact a2.
By switching to the side, the switch circuit body 17A
The reference pilot signal S11 sent from the first
As shown in FIGS. 20A to 20F corresponding to FIGS. It will lock into the tracking state.

In this way, the configuration shown in FIG. 16 also provides the same effect as described above with respect to FIG. 6, and the oscillation point detection switch circuit 32 can be omitted compared to the configuration shown in FIG. , the overall configuration can be further simplified.

In addition, in the above, when detecting the oscillation point,
The determination is made based on whether the error signal exceeds a predetermined level, but instead, the determination may be made based on whether the error signal crosses the zero point with a slope in the negative direction. .

Furthermore, in the above description, the case where the number of tracks for skipping is selected to be two stages (that is, one adjacent track), but this number of stages can be selected to any value as necessary.

Furthermore, in the embodiment shown in FIG. 14, the time division signal S11 and the skip signal S27 are given to the switch control circuit 61 to time division control the control condition signals SEL1 and SEL2 for the switch circuit body 17A, thereby checking the oscillation from the switch circuit body 17A. The output/reproduction reference signal S42 is formed, but instead of this, the signals S11 and S26 are applied to the switch circuit main body 17A.
The oscillation point detection/reproduction reference signal S42 may be formed by a gate circuit provided at 7A.

Furthermore, in the above description, the skip permission determination circuit 50 is sequentially configured to generate the oscillation point detection signal S25 using the write clock signal S28 obtained by the rise and fall of the head switching signal RF-SW in the write clock forming circuit 53. The configuration is such that the judgment data is read into the judgment data storage circuit 51 and the judgment output S26 is sent from the output judgment circuit 52 to the hold circuit 46 based on the logical product of the contents of all bits. It may also be realized by a calculation operation of a computer.

〔Effect of the invention〕

As described above, according to the present invention, when the reproducing head is at a position outside the lock-in range of the tracking control device (that is, at the oscillation point position), the circulation order of the pilot frequency of the reference pilot signal is skipped by a predetermined number of stages. This allows the tracking control device to lock into the VTR's phase servo system in a relatively short time. Therefore, for example, when the tracking control device is operated to lock in at the start of VTR playback, the lock-in time can be statistically halved. It can be shortened to

In this way, the content of the logic level of the oscillation point detection signal is determined for each predetermined field based on each field section of the reproduced signal to determine whether or not to skip. A lock-in operation can be performed stably and reliably even when the tape playback mode does not match the recording mode.

[Brief explanation of drawings]

Fig. 1 is a characteristic curve diagram showing the characteristics of an ATF type tracking control device, Fig. 2 is a block diagram showing the principle configuration of the ATF type tracking control device, and Fig. 3 is a schematic diagram showing its tape pattern.
Figure 4 is a schematic diagram showing the signals of each part in Figure 2;
The figure is a characteristic curve diagram showing the characteristics of a CTL type tracking control device, FIG. 6 is a block diagram showing an embodiment of the tracking control device according to the present invention, and FIG.
Figure 8 is a diagram showing the configuration of the switch circuit, Figure 8 is a schematic diagram showing the signals of each part of the switch circuit in Figure 6, Figure 9 is a diagram showing the circulation order of the pilot frequency, and Figure 10 is a diagram showing the signal of each part of the switch circuit in Figure 6. The characteristic curve diagram showing the characteristics of the oscillation point detection circuit shown in Fig. 6, and Figs.
14 is a block diagram showing another embodiment of the present invention; FIG. 15 is a schematic diagram showing signals of each part;
FIG. 16 is a block diagram showing still another embodiment of the present invention, FIG. 17 is a schematic diagram showing the relationship between the difference frequencies of the difference frequency detection circuit, and FIGS. 18 to 20 are the operations of FIG. 16. FIG. 2 is a schematic diagram showing signals of each part for explanation. 1... Pilot signal detection circuit, 3... Error signal forming circuit, 14, 35... Multiplication circuit, 16...
...Pilot signal generation circuit, 17...Switch circuit, 17A...Switch circuit main body, 17C...Skip control switch, 20, 21... _ΔA ,
_ΔB detection circuit, 31...Oscillation point detection circuit, 32...
...Oscillation point detection switch circuit, 32A...Switch circuit main body, 32D...Skip control switch, 44...Level detection circuit, 46...Hold circuit, 50...Skip permission determination circuit, 51...
Judgment data storage circuit, 52... Output judgment circuit, 5
3...Write clock formation circuit, 61...Switch control circuit, 63...Time division signal generation circuit, 64...
...Oscillation point detection signal forming circuit, 65, 66...Sampling hold circuit, 71, 72... _ΔC ,
_ΔD detection circuit.

Claims (1)

[Scope of Claims] 1. A reproducing pilot obtained by recording a recording pilot signal whose frequency changes cyclically in a predetermined order in field units on a recording track, and reproducing the recording pilot signal when reproducing the recording track. The signal is multiplied by a reference pilot signal whose frequency changes sequentially and cyclically in field units,
A tracking control device configured to control the tracking position of the playback head by detecting a difference frequency component generated in the multiplication output, a detection output for each field when the frequency difference component is not within a predetermined lock-in range. A lock-in error detection means that generates a lock-in error, a storage means that stores detection outputs of the lock-in error detection means for a plurality of predetermined fields, and whether or not the outputs of the storage means for the plurality of fields all match. skip permissibility determining means for detecting and determining permission or disapproval of the skip operation based on the detected output; and skip control means for skipping the circulation order of the reference pilot signal by a predetermined number of steps based on the output of the skip permissible determining means. A tracking control device comprising: