JPH0554263B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of making contact between a gate electrode and a diffusion layer wiring.

[Prior art and its problems]

In conventional LSI, diffusion layers, polysilicon, and
Wiring between elements is performed using Al wiring or the like. For example, in the case of a diffusion layer and polysilicon, these wirings are interconnected through direct contact. However, the conventional direct contact method has various problems, and new technical improvements have been desired. The problems of the prior art will be explained below with reference to the drawings.

Figure 1a has direct contact
1 is a plan view showing a part of an LSI, in which a gate electrode 101 made of polysilicon, wiring 102, etc. are arranged. Reference numerals 103 and 104 are diffusion layer wirings, which also serve as the source and drain of a MOS transistor whose gate electrode is 101. For example, this corresponds to a circuit diagram such as that shown in FIG. 1b. Polysilicon wiring 102 and diffusion layer wiring 104
Electrical contact with the direct contact 10
5. 2A to 2D are cross-sectional views taken along p-p' of the circuit element shown in FIG. 1, and schematically depict the manufacturing process thereof.

For example, a gate oxide film 20 is formed on a P-type Si substrate 201.
2 is formed by thermal oxidation, for example, to a thickness of about 200 Å. Next, the masks are aligned and the direct contact part 2
The oxide film of No. 03 is removed by etching under NH ₄ to expose the Si substrate surface (second
Diagram a). Next, CVD polysilicon 204 on the entire surface.
The phosphorus is deposited over the entire surface by a method such as a method, and phosphorus is diffused over the entire surface by, for example, performing POCl ₃ diffusion. At this time, in the direct contact part, phosphorus is diffused into the silicon substrate to form a diffusion layer 205 (second
Figure b).

Next, a photoresistor 206 is left on the gate electrode and wiring portion by masking, and the polysilicon 204 is removed by etching using this as a mask. This etching can be performed, for example, by reactive ion etching using CCl ₄ or the like, but in this case, in the transistor part, the Si etching is not sufficient to remove the oxide film 2.
However, since there is no oxide film in the direct contact area, a groove 207 is formed in the silicon substrate as shown in FIG. 2c. Next, the gate oxide film 202 is removed, and the As
×10 ¹⁵ cm ^-2 ions are implanted and then annealed at, for example, 1000° C. for about 30 minutes to form source/drain and diffusion layer wiring 208. At this time, an N ⁺ diffusion layer is also formed in the trench by ion implantation, and the polysilicon wiring 209 and the diffusion layer wiring 208 are
electrically connected. However, the depth and shape of the groove are not constant and vary greatly depending on the etching conditions, over-etching time, etc., so the resistance value varies greatly in the groove. Furthermore, if the groove is large and circular, the diffusion layer 208 and the polysilicon wiring 209 will be electrically isolated from each other because the diffusion layer will not be connected at the groove portion, as shown in FIG. 2e. The above-mentioned problems become more important as the junction depth becomes shallower with the miniaturization of devices, and have been the cause of a significant decrease in LSI yields. Furthermore, crystal defects generated in the grooves due to reactive ion etching increase junction leakage in the diffusion layer, resulting in a reduction in device performance.

The above describes the case of an N-channel transistor formed on a p-type substrate, but the so-called
CMOS circuits have the following important issues.
In other words, if N ⁺ polysilicon is used, direct contact cannot be made in the region where the P channel transistor is formed. For example, as shown in Figure 3a, the source/drain/diffusion layer wiring is made of a P ⁺ diffusion layer into which boron is ion-implanted, but if the process is similar to that shown in Figures 2a to d, the direct collect area is made of N. ⁺ Since a p-n junction cannot be formed between polysilicon and an n-type substrate, it will be shot with the substrate. Further, for example, if the gate 310 of the transistor is first formed and ^the P ⁺ diffusion layer is formed as shown in ^FIG. polysilicon 3
A pn junction is formed in the direct contact portion between the P + diffusion layer 308 and the P ⁺ diffusion layer 308, making it impossible to establish ohmic contact.

For the above reasons, for example, in a CMOS circuit using N ⁺ polysilicon wiring, direct contact cannot be made in the P channel transistor region.

These problems have placed great constraints on circuit design.

[Purpose of the invention]

The present invention has been made in view of the above points, and it is an object of the present invention to provide a contact method that is excellent in yield and can increase the degree of freedom in designing an LSI.

[Summary of the invention]

The present invention includes a process of forming a first insulating film in a region surrounded by a field insulating film of a semiconductor substrate, and forming wiring and a gate electrode of a MIS transistor using the semiconductor film on the first insulating film, and a process of forming these wirings. and forming a second insulating film on the sidewalls of the gate electrode, leaving the second insulating film on the sidewalls of the gate electrode and removing the second insulating film on the sidewalls of the wiring, and forming the field insulating film on the sidewalls of the wiring. A step of growing a metal or metal semiconductor compound from the surface of a conduction type region formed by doping an impurity into a substrate in a region surrounded by a film and the surface of the wiring, and connecting these conductivity type regions and the wiring. It is characterized by being prepared.

〔Effect of the invention〕

According to the present invention, an insulating thin film is formed in a region surrounded by a field insulating film, and then wiring and gate electrodes using a semiconductor film are provided, so that the substrate is prevented from being etched during patterning of the wiring film. This can be prevented and yields can be improved. In addition, the substrate wiring layer and the wiring film are separated by an insulating film formed in the element formation region, and are interconnected by a metal or metal-semiconductor compound film, so that contact can be established regardless of the conductivity type of the two. It becomes possible,
The degree of freedom in LSI design will be greatly improved.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 4a, a gate oxide film 40 with a thickness of 50 to 1500 Å, for example 200 Å, is formed on a p-type substrate 401, for example.
2, a gate electrode 4 made of polysilicon is formed.
10 and wiring 409 are formed. This polysilicon may be, for example, so-called doped polysilicon to which phosphorus or arsenic is added during formation, or it may be doped with impurities by POCl ₃ diffusion or ion implantation after polysilicon is deposited on the entire surface. or,
Impurities may be doped simultaneously with the subsequent formation of the source and drain. Then, for example, As
Source/drain and diffusion layer wiring 408 are formed by implanting ions of 3 to 5×10 ¹⁵ cm ⁻² at 50 KV. This ion implantation may be performed through the gate insulating film, or may be performed after removal. A thick field insulating film (not shown) is formed in the field region (corresponding to the region other than the diffusion layer in FIG. 1a). Next, the ion-implanted As is activated by annealing in an oxidizing atmosphere or N ₂ atmosphere at 1000° C., for example. Next, CVD/
SiO ₂ 411 is deposited (FIG. 4b). Next, the entire surface is subjected to directional ion etching. For example CF ₄ and H ₂
The diffusion layer 408 is etched by etching SiO ₂ using reactive ion etching using gas.
At the same time as exposing the surface, SiO ₂ 412 is left on the side walls of the gate electrode 410 and the polysilicon wiring 409 (FIG. 4c). Next, photoresist 41
3 selectively install at least polysilicon wiring 4
A portion making electrical contact between 09 and the diffusion layer wiring is exposed. Then, etching is performed under, for example, NH ₄ to remove the oxide film on the side walls of the polysilicon wiring (FIG. 4d). Next, a Pt film with a thickness of approximately 500 Å is formed on the entire surface by vacuum evaporation.
After annealing for 30 minutes, PtSi (platinum silicide) 414 is formed only in the portions where the Pt film is in contact with silicon or polysilicon. Thereafter, the unreacted Pt film is removed by treatment in aqua regia, and the structure shown in FIG. 4e is obtained. Pt silicide 414 is the source/drain and diffusion layer 40
8, the top surface of the gate electrode 410, and the top surface and sidewalls of the polysilicon wiring 409. At this time, polysilicon wiring, PtSi on the sidewall
and PtSi on the diffusion layer 408 are interconnected and formed continuously.

Figure 4 f to g are enlarged views of this part where PtSi414 is formed between the Pt film, polysilicon 409 and the diffusion layer.
a state in which a layer is forming (FIG. 4f), and
This shows the state in which the PtSi formation reaction has been completed (Fig. 4g). As is clear from the figure, the polysilicon wiring and the diffusion layer 408 are electrically insulated by the approximately 200 Å thick gate oxide film 402, but are connected by the interconnection of the silicides formed on their respective surfaces. In this way, since the gate oxide film is not removed by etching before installing polysilicon at the contact area between the polysilicon wiring and the diffusion layer wiring, the etching of the polysilicon can be stopped on the gate oxide film. Unlike the conventional example, there is no possibility that the previously exposed silicon substrate is etched and a groove is formed. This not only solves the problem of the contact resistance changing depending on the polysilicon overetching time or the failure to make contact, but also eliminates defects caused by the reactive ion etching process in the substrate silicon and causing diffusion. Problems such as an increase in leakage current at the PN junction of the layers are also eliminated. Furthermore, since the polysilicon wiring and the substrate silicon are separated by an oxide film, for example, even if P ⁺ polysilicon is used instead of N ⁺ polysilicon, there is no chance of the wiring being shot with the substrate as in the conventional example.

The above has described the case where the gate electrode 410 and the wiring 409 are formed at the same time, but for example, as shown in FIG.
After forming the source/drain and diffusion layer,
Formed by ion implantation, then polysilicon wiring 4
After selectively installing 09 through the oxide film 416, the same steps as those described in FIGS. 4b to 4e may be performed. In this case, for example, even if the impurity of the polysilicon 409 is P-type boron, there is no PN junction with the N-type diffusion layer 408 because of the presence of the oxide film 416. Also, since ohmic contact can be made between silicide and N ⁺ and P ⁺ silicon, ohmic contact can always be made between the polysilicon wiring and the diffusion layer.

Although the above description is limited to the case of a p-type substrate, it can be applied in exactly the same way even if an n-type substrate is used, or to the manufacture of a CMOS circuit having both p-type and n-type substrates at the same time. In particular, direct contact between P ⁺ wiring layer - N ⁺ polysilicon and N ⁺ wiring layer - P ⁺ polysilicon is possible, and it is possible to connect both p ⁺ and n ⁺ polysilicon to either p-type or n-type substrates. Contact can also be made using wiring. Further, in this embodiment, only the case where both the gate electrode and the wiring are made of polysilicon has been described, but this is, for example, a two-layer structure of polysilicon and silicide. The same applies to so-called polycide. Even in this case, silicide can be further grown on the silicide in the step shown in FIG. 4e. Also, in the process shown in Figure 4b
Instead of depositing CVD SiO ₂ , the entire surface may be thermally oxidized. In addition, although we have only described the case where Pt silicide is formed by thermal annealing, Pd, Ni, W, Mo, Ta,
It may be a silicide of any metal other than Co. The formation method may also be ion beam mixing using ion implantation, or annealing using a laser or electron beam. Ion beam mixing using phosphorus, As, etc. allows silicide formation and impurity doping to be performed simultaneously. In this case, if the insulator on the side walls of the gate is doped with impurities in advance, the area around the gate end can be doped. Furthermore, the conductive film selectively provided in FIG.
It does not have to be silicide. The metal may be deposited by reacting the metal fluoride gas in a reducing atmosphere at a temperature lower than the temperature at which metal silicide is formed. For example, WF ₆ and H ₂ gas at 400℃~
If W is deposited by the CVD method by reacting in a temperature range of 600° C., it can be selectively deposited only on the silicon and polysilicon surfaces. For example, FIG. 5 shows a cross-sectional shape of an element according to a second embodiment of the present invention carried out in this manner. A mixed gas of MoF ₆ and H ₂ can also be used.

The various modifications described in the first embodiment can all be performed in the same way by replacing the entire Pt silicide formation step with this metal selective deposition step. Further, in the embodiments of the present invention, the thickness of the insulating thin film is preferably 50 to 1500 Å in order to form a continuous film. Alternatively, instead of selective growth, after forming electrodes and wiring, an insulating film may be deposited on the entire surface, contact holes may be opened, and the two may be connected using a compound film with metal or semiconductor.

As explained above, according to the present invention, it is possible to obtain a contact manufacturing method that has an excellent yield and can greatly increase the degree of freedom in LSI design.

[Brief explanation of drawings]

Fig. 1a is a top view illustrating a direct contact, Fig. 1b is a circuit diagram thereof, Figs. 5 is a process cross-sectional view explaining the first embodiment of the present invention, and FIG. 5 is a cross-sectional view explaining the second embodiment of the present invention. In the figure, 101, 210, 310, 410,
510...gate electrode, 102, 209, 30
9,409,509...Polysilicon wiring, 10
3,104,208,308,408,508...
...diffusion layer, 105...direct contact,
414...PtSi (platinum silicide), 500...
...W (tungsten).

Claims (1)

[Claims] 1. A step of forming a first insulating film in a region surrounded by a field insulating film of a semiconductor substrate, and forming wiring and a gate electrode of a MIS type transistor using a semiconductor film on the first insulating film, and forming a first insulating film on the first insulating film in a region surrounded by a field insulating film of a semiconductor substrate. forming a second insulating film on the side wall of the gate electrode, leaving the second insulating film on the side wall of the gate electrode and removing the second insulating film on the side wall of the wiring, and a step of growing a metal or a metal semiconductor compound from the surface of a conductivity type region formed by doping an impurity on the substrate in a region of the conductivity type and the surface of the wiring, and connecting these conductivity type regions and the wiring. A method for manufacturing a semiconductor device, characterized by: