JPH0555242A - Manufacture of semiconductor element - Google Patents

Abstract

(57) [Abstract] [Purpose] In the manufacturing process of semiconductor elements such as transistors, in order to correct the deviation of the electrical characteristic (hFE) value from the target value at the stage after the electrode formation where the element manufacturing is completed. , Or follow the changed required grade with respect to the original schedule. [Structure] The impurity diffusion layer is displaced by heating the wafer in a state where an electric field is applied to the emitter base after the electrode of the semiconductor element is formed by using an electric field applying jig, thereby changing the base width. Fine adjustment is performed to control the electrical characteristics of the device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device,
In particular, the present invention relates to a technique for controlling electric characteristics associated with impurity diffusion after forming electrodes of a semiconductor element.

[0002]

2. Description of the Related Art Generally, semiconductor elements such as transistors are
It is formed by forming a plurality of impurity diffusion regions on one main surface of a semiconductor substrate at the wafer stage, and it is desirable that the electrical characteristics of these semiconductor elements be known at an early stage of the manufacturing process. For example, in the manufacturing process of a silicon transistor, the hFE (current amplification factor) of the transistor is usually controlled by changing the diffusion processing time in the emitter region forming step. The hFE control technique is described in Japanese Patent Publication No. 56-6143.

That is, in the silicon transistor manufacturing process, the conventional method of hFE control is shown in FIG.
Is shown in the process flow chart of FIG. Process sectional views corresponding to the respective processes of FIG. 1 are shown in FIGS.
As an initial stage of the process, as shown in FIG. 2, a P-type impurity diffusion layer (region) 2 is formed on the surface of one main surface of an N-type silicon wafer (substrate) 1 and is used as a base region. Reference numeral 4 is a thermal oxide film (silicon dioxide film) formed on the wafer surface by the oxidation or diffusion process. As shown in FIG. 3, an N-type impurity diffusion layer (region) 3 is formed by using a photoresist obtained by forming an emitter hole in a part of the thermal oxide film by a photoresist technique as an emitter region.

As shown in FIG. 4, an electrode hole 5 is formed in a part of the thermal oxide film 4 by a photoresist technique. After that, the measuring needle is brought into contact with the semiconductor surface through the emitter hole and the base hole, and the collector region surface (the back surface of the wafer) is brought into contact with the sample stage (connected to the collector electrode) to obtain the device characteristics (hF
Check E). In order to match the value of hFE with the design value of the element, the depth of the N-type impurity diffusion layer (emitter) 3, that is, the base width is adjusted. This is generally done by changing the emitter diffusion process time. Then, as further shown in FIG. 5, Al (aluminum)
By forming the electrode 8, the basic structure of the device is completed. In this state, hFE and other electrical characteristics are inspected through the Al electrode 8.

[0005]

The conventional method of forming a transistor element and the conventional method of controlling hFE have the following problems. The hFE value in the characteristic inspection (A) in the process of FIG. 1 is caused by the imperfect contact of the measuring needle with the base / emitter surface and the collector surface (back surface of the wafer) in the step shown in FIG. The measurement accuracy is not sufficient in some cases, and due to various fluctuation factors in the subsequent process, for example, the final characteristic inspection (B) through the Al electrode may show a changed value of hFE. That is, even an element or wafer that has been determined to be non-defective in the previous characteristic inspection (A) may be defective in the subsequent inspection (B).

In most cases, the hFE values of the transistors are subdivided into hFE grades, and each grade meets the customer's requirements. The required grade changes according to the customer's purpose. I often do it. Therefore, even if the initially aimed hFE value (hFE grade) is obtained in the characteristic inspection (B), it may not be possible to comply with it due to changes in requirements.

The problem to be solved is that since the basic element structure has been completed after the formation of the electrode of the semiconductor element, it is difficult to adjust the hFE value thereafter, and it is not possible to meet the demand change. That is. It is an object of the present invention to provide a technique capable of adjusting the hFE value even on a wafer after electrode formation.

[0008]

According to the present invention, a base / emitter region is formed by an impurity diffusion layer on one main surface of a semiconductor substrate, and an electrode is formed on the surface of the region by resistance connection. In the state where an appropriate electric field is applied to the junction part of, the heat treatment is performed at a temperature that does not damage the electrode, thereby displacing the impurity diffusion layer and controlling the electrical characteristics of the semiconductor element. To do. The heat treatment in the above method is 400 ° C. to 60 ° C.
The temperature and time are controlled in the temperature range of 0 ° C. In the above method, an electric field is applied and heat treatment is performed using an electrode jig in which a portion other than corresponding portions other than a plurality of electrodes for applying an electric field is covered with an insulating protective film. By taking such means, the bonding force between the silicon crystal lattices is reduced to make the impurity atoms move easily, the impurity diffusion layer is displaced by heat treatment at a relatively low temperature, and the hFE value is maintained even after the electrode formation. It becomes easy to adjust.

[0009]

FIG. 6 and FIG. 7 are cross-sectional views of main steps in one embodiment of a method of manufacturing a semiconductor device according to the present invention.
Prior to this main process, according to a conventional manufacturing process (see FIG. 1), formation of a base region, an emitter region, a characteristic inspection (A) through an electrode hole, and a characteristic inspection (B) after forming an Al electrode are performed as shown in FIG. Each step is completed as shown in the first half process. As shown in FIG. 6, the electric field applying jig 9 is used for the wafer 1 at this time, and the emitter connecting portion 10 of the electric field applying jig is brought into contact with the electrode 8 in the emitter region of the wafer. An electric field is applied to the wafer substrate (collector portion) 1 by applying an appropriate voltage, for example, 5 to 6 V, and at the same time, heat treatment at 400 ° C. is performed. The electric field is applied for as long as necessary to obtain the design value of the hFE characteristic of the semiconductor element.

FIG. 7 shows an example in which another type of the electric field applying jig 9 is used. This jig has a connecting portion 11 corresponding to the base electrode in addition to the connecting portion 10 corresponding to the emitter electrode. In this case, the two connecting parts 10 and 11 are brought into contact with the respective electrodes 8 of the emitter and the base, and a space between them is 5
A voltage of ˜6 V is applied to apply an electric field, and at the same time, the same heat treatment is performed. Also in this case, the required hFE value can be adjusted by changing the temperature and time of the heat treatment. FIG. 8 is a flow chart showing the characteristic (hFE) inspection (C) including the electric field application step and the heat treatment step according to the present invention added to the latter half process.

As shown in FIGS. 6 and 7, the electric field applying jig 9 is used.
At the emitter connection part 10 and the base connection part 11
Are electrically separated from each other by an insulating protective film 12, and each is mechanically protected. Further, the electric field applying jig 9 has a multi-electrode structure in which it is simultaneously connected to all the elements of the wafer, and also has a structure in which only the necessary elements are connected and the required number of elements can be applied. It can also be adopted.

[0012]

As described above, according to the method for manufacturing a semiconductor device of the present invention, after the Al electrode is formed, the electric field applied to the wafer promotes the diffusion of impurities in the semiconductor crystal structure. .. As a result, the base width also changes, and the hFE value can be finely adjusted even after the electrodes are formed.

Due to the above-mentioned reasons, a wafer (defective wafer) that is not targeted by hFE can be relieved, and even if an element having the desired characteristics for the initial request can be obtained, it will be performed later. In the case where the wafer concerned can contribute to the immediate production, it is possible to deal with the change due to the customer's request. Moreover, it is possible to sufficiently cope with a short delivery date without starting a new wafer process.

[Brief description of drawings]

FIG. 1 is a flow chart showing an example of a conventional manufacturing process of a transistor.

FIG. 2 is a process cross-sectional view when forming a base in a transistor manufacturing process.

FIG. 3 is a process cross-sectional view when forming an emitter in a transistor manufacturing process.

FIG. 4 is a process cross-sectional view during characteristic inspection (A) through an electrode hole in a transistor manufacturing process.

FIG. 5 is a process cross-sectional view during characteristic inspection (B) after forming an Al electrode in a transistor manufacturing process.

FIG. 6 is a process sectional view of an example of the present invention.

FIG. 7 is a cross-sectional view of main steps of another embodiment of the present invention.

FIG. 8 is a flow chart diagram (a part of the first half of the process is omitted) of the transistor manufacturing process including the main steps of the embodiment of the present invention.

[Explanation of symbols]

 1 N-type silicon substrate (wafer) 2 P-type impurity (base) diffusion layer 3 N-type impurity (emitter) diffusion layer 4 Thermal oxide film 5 Electrode hole 6 Emitter-base junction 7 Base-collector junction 8 Al electrode 9 Electric field application Jig 10 Emitter connection part 11 Base connection part 12 Insulating protective film

Claims (3)

[Claims] 1. An electric field is externally applied to the impurity diffusion layer through the electrode after forming an impurity diffusion layer on one main surface of a semiconductor substrate and forming an electrode for resistance connection on the surface of the impurity diffusion layer. A method for manufacturing a semiconductor element, wherein the impurity diffusion layer is displaced to control the electrical characteristics of the semiconductor element by performing heat treatment at a temperature that does not damage the electrode in the above state. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature and time of the heat treatment are adjusted in a temperature range of 400 ° C. to 600 ° C. in a state where an electric field is applied to the base / emitter junction of the bipolar transistor. 3. The method for manufacturing a semiconductor element according to claim 2, wherein an electric field is applied by using an electrode jig in which a portion other than the corresponding portion of the electric field applying electrode is covered with an insulating protective film, and
Perform heat treatment.