JPH0555363A - Element isolating method - Google Patents

Abstract

(57) [Abstract] [Purpose] The bird's beak is not generated in the dielectric film for element isolation, the junction capacitance of the diffusion layer is made small, the surface of the semiconductor substrate is made flat, and it is fine and has excellent characteristics. It enables the manufacture of highly reliable semiconductor devices. A mask layer and side walls thereof are formed on a portion of a semiconductor substrate 11 to be an element active region, and a channel stopper 17 is formed at the bottom of a groove 16 formed by using these mask layers and side walls as a mask. The groove 16 is formed and SiO ₂ is formed.
Fill with membrane 21. After removing the side wall, the groove 24 formed by using the mask layer as a mask is filled with the SiO ₂ film 25. Si
A device isolation region is formed by the O ₂ films 21 and 25, and a portion surrounded by these SiO ₂ films 21 and 25 becomes a device active region. The diffusion layer formed in the element active region and the channel stopper 17 are separated by the SiO ₂ film 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element separating method for electrically separating a plurality of elements arranged on one semiconductor chip.

[0002]

2. Description of the Related Art The most commonly used conventional method for element isolation is to selectively thermally oxidize only the surface of a portion of a semiconductor substrate to be an element isolation region to form an oxide film. , LOCOS method for dielectric isolation.

[0003]

[Problems to be Solved by the Invention] However, LOCOS
In the method, bird's beaks are formed at the ends of the oxide film for element isolation. Therefore, the element active region becomes smaller by the amount of the bird's beak, and it is necessary to secure a large element active region in advance, so that a fine semiconductor device cannot be manufactured.

Further, crystal defects due to stress are induced in the semiconductor substrate under the bird's beak, and moreover, the channel stopper formed under the oxide film in the element isolation region and the diffusion layer formed in the element active region are in contact with each other. The junction capacitance increases, and a semiconductor device with excellent characteristics cannot be manufactured. In addition, since the level difference between the element isolation region and the element active region is large and the flatness of the surface of the semiconductor substrate is low, a highly reliable semiconductor device cannot be manufactured.

[0005]

According to the element isolation method of the present invention, mask layers 13, 14, 22 are formed on a portion of a semiconductor substrate 11 to be an element active region, and the mask layers 13, 14, A step of forming a side wall 15 on a side portion of 22; a step of forming a first groove 16 in the semiconductor substrate 11 by using the mask layers 13, 14, 22 and the side wall 15 as a mask; Forming a channel stopper 17 at the bottom of the groove 16 and filling the first groove 16 with a first dielectric material 21, removing the side wall 15, and removing the mask layers 13, 14, 22 and the first layer. Forming a second groove 24 in the semiconductor substrate 11 exposed by the removal using the dielectric 21 as a mask; and forming a second groove 24 in the second groove 24
And filling with the dielectric 25.

[0006]

In the device isolation method according to the present invention, the first and second
Since the trenches 16 and 24 are filled with the first and second dielectrics 21 and 25 to form the element isolation region, the semiconductor substrate 11
The bird's beak does not occur in the dielectrics 21 and 25 as in the case where the surface of is thermally oxidized to form an oxide film for element isolation. Therefore, the element active region does not become small, and crystal defects are not induced in the semiconductor substrate 11.

Further, the second groove 24 is formed in the device active region and the first groove.
The second groove 24 is formed between the channel stopper 17 formed at the bottom of the first groove 16 and the diffusion layer formed in the element active region. There is no contact with. Therefore, the junction capacitance of the diffusion layer is small.

Further, as described above, the first and second grooves 16,
Since 24 is filled with the first and second dielectrics 21 and 25 to form the element isolation region, as compared with the case where the surface of the semiconductor substrate 11 is thermally oxidized to form an oxide film for element isolation,
The step difference between the element isolation region and the element active region is small. Therefore, the flatness of the surface of the semiconductor substrate 11 is high.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to the manufacture of MOS transistors will be described below with reference to FIGS.

In this embodiment, as shown in FIG.
The surface of the substrate 11 is oxidized to form the SiO ₂ film 12 for the pad. Then, a polycrystalline Si film 13 is deposited on the SiO ₂ film 12 by a CVD method, and the surface of the polycrystalline Si film 13 is oxidized to form a SiO ₂ film 14.

Next, as shown in FIG. 2, the SiO ₂ film 14 is formed only on the portion of the Si substrate 11 to be the element active region.
The SiO ₂ film 14 and the polycrystal Si film 13 are patterned so that the polycrystal Si film 13 and the polycrystal Si film 13 remain.

Next, as shown in FIG. 3, SiN is formed by the CVD method.
The film 15 is deposited on the entire surface, the entire surface of the SiN film 15 is etched back, and the side wall made of the SiN film 15 is made of polycrystalline S.
It is formed on the side portions of the i film 13 and the SiO ₂ film 14.

Next, as shown in FIG. 4, a polycrystalline Si film 13 is formed.
And the SiN film 15 are used as masks to etch the SiO ₂ film 12 to expose portions of the Si substrate 11 other than those under the polycrystalline Si film 13 and the SiN film 15. At this time, S
iO ₂ film 14 is also etched simultaneously, the SiO ₂ film 14 be a SiO ₂ film 12 is removed so as not removed, it keeps selecting the thickness of the SiO ₂ film 14.

Next, as shown in FIG. 5, the Si substrate 11 is anisotropically etched using the SiO ₂ film 14 and the SiN film 15 as a mask to form a groove 16 in the Si substrate 11.
Then, using the SiO ₂ film 14, the polycrystalline Si film 13, and the SiN film 15 as masks, impurities of the same conductivity type as the Si substrate 11 are ion-implanted into the Si substrate 11, and the channel stopper 17 is provided at the bottom of the groove 16. To form.

Next, as shown in FIG. 6, SiO is formed by the CVD method.
_{The 2} film 21 is deposited on the entire surface, and a resist (not shown) is applied on the SiO ₂ film 21 to flatten the surface. Then, under the condition that the etching rates of this resist and the SiO ₂ films 21 and 14 are equal to each other, these resist and Si
The O ₂ films 21 and 14 are etched back to form the groove 16 in Si.
Fill with the O ₂ film 21.

Next, as shown in FIG. 7, a polycrystalline Si film 13 is formed.
The surface of is oxidized and the SiO ₂ film 22 is formed on this surface. At this time, the surface of the SiN film 15 is also slightly oxidized,
The SiO ₂ film 23 is also formed on this surface.

[0017] Next, as shown in FIG. 8, the SiO ₂ film 23,22,21 etched to the extent that only the SiO ₂ film 23 is removed, further removing the SiN film 15 by etching. Then, to the extent that only the SiO ₂ film 12 existing under the SiN film 15 is removed, the SiO ₂ films 12, 22,
21 is etched to expose the portion of the Si substrate 11 that was under the SiN film 15.

Next, as shown in FIG. 9, the SiO ₂ film 21,
The Si substrate 11 is anisotropically etched using 22 as a mask to form a groove 24 deeper than the channel stopper 17 in the Si substrate 11.

Next, as shown in FIG. 10, a SiO ₂ film 25 is deposited on the entire surface by a plasma CVD method using TEOS as a raw material, and a resist (not shown) is applied on the SiO ₂ film 25. Flatten the surface. Then, the resist and the SiO ₂ films 25 and 22 are etched back under the condition that the etching rates of the resist and the SiO ₂ films 25 and 22 are equal to each other, so that the groove 24 is filled with the SiO ₂ film 25.

After that, the polycrystalline Si film 13 and the SiO ₂ film 1
2 are removed, and the SiO ₂ film 2 of the Si substrate 11 is removed.
The part surrounded by 5 and 21 is exposed. Since this portion is the element active region, the surface of the element active region is oxidized to form the gate oxide film of the MOS transistor.
The O ₂ film 26 is formed.

Then, a gate electrode (not shown) of the MOS transistor is formed on the SiO ₂ film 26 and the like, and a diffusion layer (not shown) serving as a source / drain is formed in the element active region, and the MOS transistor is formed. To complete.

[0022]

According to the element isolation method of the present invention, since the element active region does not become small, a fine semiconductor device can be manufactured. In addition, since crystal defects are not induced in the semiconductor substrate and the junction capacitance of the diffusion layer is small, a semiconductor device having excellent characteristics can be manufactured.
Moreover, since the surface of the semiconductor substrate has a high degree of flatness, a highly reliable semiconductor device can be manufactured.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a first step of an embodiment of the present invention.

FIG. 2 is a side sectional view showing a step that follows FIG.

FIG. 3 is a side sectional view showing a step that follows FIG.

FIG. 4 is a side sectional view showing a step that follows FIG.

5 is a side sectional view showing a step that follows FIG.

6 is a side sectional view showing a step that follows FIG.

7 is a side sectional view showing a step that follows FIG.

8 is a side sectional view showing a step that follows FIG. 7. FIG.

9 is a side sectional view showing a step that follows FIG.

FIG. 10 is a side sectional view showing a step that follows FIG.

[Explanation of symbols]

11 Si substrate 13 polycrystalline Si film 14 SiO ₂ film 15 SiN film 16 groove 17 channel stopper 21 SiO ₂ film 22 SiO ₂ film 24 groove 25 SiO ₂ film

Claims (1)

[Claims] 1. A step of forming a mask layer on a portion of a semiconductor substrate to be an element active region, and forming a sidewall on a side portion of the mask layer; and using the mask layer and the sidewall as a mask. Forming a first groove in the semiconductor substrate; forming a channel stopper at the bottom of the first groove and filling the first groove with a first dielectric; removing the sidewall; Forming a second groove in the semiconductor substrate exposed by the removal using the mask layer and the first dielectric as a mask; and filling the second groove with a second dielectric. An element isolation method having.