JPH0555836A - amplifier - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide an amplifier circuit suitable for use in a first stage or an intermediate stage of a differential output type high gain amplifier or a push-pull multistage amplifier. [Structure] In an amplifier 1 composed of a plurality of stages, at least an amplification stage 2 constituting an initial stage or an intermediate stage comprises a transconductor 2a for converting a potential change of an input signal into a differential current change, and the transconductor 2a. Loads 2b and 2c having a value of (1 / g _m3 ) connected to the respective outputs, and a differential output of the transconductor 2a so as to form a positive feedback loop with the differential output of the transconductor 2a as an input. And a differential input differential output transconductor 2d having a transconductance of g _m2 .

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to high gain amplifiers.

[0002]

2. Description of the Related Art Conventional differential output type amplifiers are Sudhir
M. Mallya et al., “Design Procedu-res for a Fully D
ifferential Folded-Dascode CMOS Operational Amplif
ier ”, IEEE JSSC Vol.24, Dec, 1989, Fig. 1 (1st
As shown in (Conventional example),
In order to realize high gain, the load transistors are cascode-connected. At this time, not only a bias circuit for generating the gate potential of the cascode-connected transistor is required, but also the maximum output amplitude becomes small. Maximum output amplitude is Rinaldo Ca
stello et al., “A High-Perrormance Micropower Switch
ed- Capacitor Filter ”, IEEE JSSC Vol.20, Dec, 1985
Although it can be improved by using the dynamic bias method described in FIGS. 7 and 8 (second conventional example), there is a drawback that the circuit scale becomes large.

In addition, in the conventional two-stage amplifier, John A. Fisher has described "A High-Perfo
rmance CMOS Power Amplifier ", IEEE JSSC Vol.20, D
A class AB source follower as explained in Fig. 2 (a) of ec, 1985 is generally used for the second stage (output stage), but it has a drawback that the maximum output amplitude becomes small. .. In order to avoid this, a push-pull configuration as shown in FIG. 2 (third conventional example) of USP4383223 has been proposed. However, in the circuit of the third conventional example, the path from the input to the first output transistor 18 has a two-stage configuration, but the path from the input to the second transistor 16 has a one-stage configuration, and It is not a push-pull configuration.

[0004]

As described above, there is no amplifier circuit suitable for the first stage or the intermediate stage suitable for the conventional high gain amplifier of the differential output type or the amplifier of the push-pull structure, and there is no desired amplifier circuit. In order to obtain the gain and output amplitude, the circuit scale becomes large, and a pseudo push-pull configuration is used.

Therefore, an object of the present invention is to provide an amplifier circuit suitable for a first stage or an intermediate stage of a differential output type high gain amplifier or push-pull amplifier.

[0006]

In order to achieve the above object, the amplifier of the present invention outputs a pair of current outputs whose levels change complementarily in accordance with the level of an input voltage signal from positive and negative output terminals. a first transconductor 2a having a transconductance of _m1 and first and second loads 2b having a value of (1 / g _m3 ) connected between the positive and negative output terminals of the first transconductor and ground, respectively. 2c
When, in g _{m @ 2} in which a pair of input terminals to generate a pair of current output whose level changes in a complementary manner according to the voltage difference between the respective connected to the input terminal to the positive and negative output terminal of the Symbol first transconductor A second transconductor 2d having a transconductance, and a positive feedback loop for returning each of the pair of current outputs of the second transconductor to each of the pair of input terminals of the second transconductor in phase. And

[0007]

According to the present invention, the transconductor 2d forms a positive feedback loop, and assuming that the transconductance of the transconductor 2a is g _m1 , the transfer characteristic of dc from the input of the transconductor 2a to the output of the transconductor 2d is ± g _m1 / (g _m2 −g _m3 ) By controlling this (g _m2 −g _m3 ), a differential output with a desired gain can be obtained. Therefore, by adding an output stage to each differential output terminal, a differential output type high gain amplifier can be easily configured without significantly increasing the circuit scale. Also, one output is inverted and level-shifted to P
The push-pull configuration can be easily realized by connecting the other output to the gate of the channel FET P1 and the gate of the N-channel FET N1 and connecting the drains of P1 and N1.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a differential output type high gain amplifier according to the present invention. The amplification stage 2 which constitutes, for example, the first stage of a multistage amplifier includes transconductors 2a and 2a.
d, and loads 2b and 2c. Each transconductor is a voltage signal-current signal converter that converts a potential change of the supplied differential input signal into a differential current change, and is configured by, for example, a current output type differential amplifier.
A differential input signal based on the input signals Vin- and Vin + is supplied between the positive and negative input terminals of the transconductor 2a. Loads 2b and 2c having a value of (1 / g _m3 ) are connected to the positive and negative output terminals of the transconductor 2a, respectively. The negative input terminal and the negative output terminal of the transconductor 2d are connected to the positive output terminal of the transconductor 2a. The positive output terminal and the positive output terminal of the transconductor 2d are connected to the negative output terminal of the transconductor 2a. Therefore, the transconductor 2d forms a positive feedback loop having the differential output of the transconductor 2a as an input. Also, the positive and negative output terminals of the transconductor 2a become the output terminals of the amplifier 2, and the output amplifier 3a of the next stage
And 3b are connected respectively. In such a configuration, assuming that the transconductance of the transconductor 2a is g _m1 and the transconductance of the transconductor 2d is g _m2 , the dc transfer characteristic of the amplifier 2 is ± g _m1 / (g _m2 −g _m3 ) as described later. expressed. Therefore, by controlling (g _m2 −g _m3 ), a differential output with a desired gain can be obtained.

When the parasitic conductance g ₀ is present at both outputs of the transconductor 2a, the transfer characteristic of dc is ±
g _m1 / (g _m2 −g _m3 −g ₀ ), but similarly (g _m2 −
It is possible to adjust the gain by controlling g _m3 ). At this time, the gain becomes maximum at g _m2 = g _m3 . Therefore,
By taking out the differential output of the amplification stage 2 via the output amplification stages 3a and 3b, the circuit scale is not significantly increased, and since the cascode connection is not used, a high output gain of the differential output type can be obtained. An amplifier can be constructed.

FIG. 2 shows an equivalent circuit of the amplifier 2, for example, "Analysis and Design of Analog Integra".
Half Circuits introduced in Chapter 3.4.4 of "Ted Circuits"
It is derived using it Concept. In FIG. 2, when v _id is a differential input (= V _{in +} −V _in− ), and vod is a differential output, (vod / 2) = {(− v _id g _m1 / 2) + (v _id g _m2 / 2)} / (
g _m3 + g ₀₎ is established, dc gain is determined by _{vod / v id = -g m1 /} (g m3 -g m2 + g 0). Therefore, when there is no conductance g _0, d
The c gain is -g _m1 / (g _m3 -g _m2 ) and g _m2 = g
_{At m3} , the gain is maximized at -g _m1 / g ₀ .

FIG. 3 is a concrete example of the embodiment shown in FIG. In the figure, current source i1 and transistors M1 and M1
2 constitutes the transconductor 2a, and the transistors M3 and M4 connecting between the gate and the drain are respectively (1 / g
_It constitutes loads 2b and 2c having a value of _m3 ). The transistors M5 and M6 and the current sources i2, i4a, i4b form a transconductor 2d. The transistor M8 and the current source i3a form the output stage 3a, and the transistor M7 and the current source i3b form the output stage 3b. A capacitor Cc1 connected between the gate and drain of the transistor M7
Also, the capacitor Cc2 connected between the gate and drain of the transistor M8 is a capacitor for phase compensation.

As described above with reference to FIG. 1, a differential output type high gain amplifier can be easily constructed without significantly increasing the circuit scale. Also, the output stage 3a
Alternatively, either 3b can be omitted and the amplifier can be used as a single output amplifier. Also, the transconductor 2d
The current sources i4a and i4b can be omitted.

[0013] In addition, the conductance g _m3 of load 2b and 2c is a g _m of each of the transistors M3 and M4,
The ratio of the width W and the length L of the transistor channel is W /
It is determined by the current flowing through the transistors M3 and M4 when L and the inputs Vin- and Vin + are balanced. Conductance g _{m @ 2} of the transconductor 2d in conductance g _m of the transistors M5 and M6, since it is determined by the current flowing through the W / L of the transistor M5 and M6, g
The control of _m3 and _gm2 is easy.

In the embodiment of FIG. 3, the transconductor 2
Since there is an output conductance added to the drains of the transistors M1 and M2 forming the a and an output conductance added to the drains of the transistors M5 and M6 forming the transconductor 2d, g _m2 = g
_{At m3,} the gain becomes maximum as described in FIG.

The embodiment of FIG. 4 is a modification in which the transistors M3 and M4 constituting the loads 2b and 2c are P-channel FETs, and the same effect as that of the embodiment shown in FIG. 3 can be obtained. ..

FIG. 5 shows an example in which the amplifier of the present invention is applied to a push-pull configuration. In FIG. 5, the gains of the two signal paths from the two input terminals to the two output terminals of the amplification stage 2 are equal and the phases are different by 180 degrees. One output of the amplification stage 2 is connected to the gate of the transistor P1 via the inverting level shift means 3c, the other output of the amplification stage 2 is connected to the gate of the transistor N1, and the drains of the transistors P1 and N1 are connected to each other. , And the sources of the transistors P1 and N1 are supplied with power sources Vdd and Vss, respectively.
The connection between the input terminal and the drain of N1 (output terminal) and the path from the input terminal to the drain of P1 (output terminal) have two stages, and the push-pull configuration can be easily realized.

FIG. 6 shows a concrete example of the embodiment shown in FIG. As described with reference to FIG. 3, the amplification stage 2 is composed of the transistors M1 to M6 and the current sources i1, i2, i4a and i4b. The transistors M3c1 and M3c2 form an inverting level shift means 3c, and the transistors P1 and N1 form a push-pull output stage. The capacitor Cc3 is a phase compensation capacitor.

Here, the current sources i1, i2, i4a and i4b
The currents I1, I2, I4a and I4b supplied by I2 / 2 = I4a = I4b are set and the transistors M1 to M6 (W / L) _M1 = (W / L) _M2 (W / L) _M3 = (W / L) _M4 (W / L) _M5 = (W / L) _M6 , and also [(W / L) _M3c1 * (W / L) _P1 / (W / L) _M3 / (W / L ) _M3c2 ] = [(W / L) _N1 / (W / L) _M4 ], so when Vin- = Vin +, the transistor M5
, M6, a current equal to I2 / 2 flows and current source i4a
And i4b, and I1 is applied to the transistors M1 to M4.
/ 2 equal current flows, so output transistor N1
A current of [(W / L) _N1 / (W / L) _M4 ] * I1 / 2 flows through P1 and P1.

When Vin->> Vin +, all the current I1 from the current source i1 flows to the transistor M2 side. At this time, the gate potential of the transistor M5 is lower than the gate potential of the transistor M6.
A current of + I2 / 2 flows, and no current flows through the transistor M3. No current flows through the transistor M5, which has a current mirror relationship with the transistor M3, and no current flows through the transistor P1. On the other hand, the transistor N1 has [(W / L) _N1 / (W / L) _M4 ] * (I1 + I2 / 2)
The current of the current flows. This is a current value that is more than twice the current value when Vin- = Vin +.

Similarly, when Vin-<< Vin +, no current flows in the transistor N1 and (W / L) _M3c1 * (W / L) _P1 / (W / L) _M3 / (in the transistor P1. W
L) _M3c2 * (I1 + I2 / 2) current and Vin- = Vin +
A current more than twice that at the time of flowing. In the case of the conventional one-stage amplifier without the transconductor 2d, that is, without the transistors M5 and M6 and the current sources i2, i4a and i4b, Vin- << Vin + or Vin- >>
At Vin +, the current flowing through the transistor P1 or N1 is twice that at Vin- = Vin +. Therefore, according to this embodiment, not only the gain but also the driving capability can be increased.

Further, when Vin- = Vin +, the current flowing through the transistor P1 or N1 increases, but the current sources i4a and i4b may be (I2 / 2) >> I4a = I4b. Further, the current sources i4a and i4b can be omitted.

FIG. 7 shows an example in which the present invention is applied to an amplifier having a folded cascode structure. In FIG. 7, the input impedances of the transistors M3 and M4 whose gates are grounded correspond to the loads 2a and 2b.
In such cases, the output amplitude cannot be improved, but
Since the amplification stage has a two-stage configuration, higher gain can be obtained.
Further, as described with reference to FIG. 6, by setting the current source as (I1 + I2) / 2 = I5a = I5b, the driving capability can be increased. As shown in FIG. 7, the operating point can be further stabilized by connecting the transistors MNL1 and MNL2 whose gates and drains are connected to each other between the sources of the transistors M3 and M4 for limiting the differential amplitude. ..

FIG. 8 shows an example of another amplifier. This is Ri
“A High-Performance” proposed by naldo Casterllo and others.
Micropower Switched-Capacitor Filter ", IEEE JSSC V
This is an example in which the present invention is applied to the class AB amplifier shown in FIG. 4 of ol. 20, Dec. 1985. The basic operation of the amplifier circuit is as described in the above document. Transistor MN
1, MN2, MP1 and MP2 are transconductors 2a
The differential output is provided in both the current outflow direction and the current suction direction. Transistor MN
B1, MNB2, MPB1 and MPB2 and the current sources iB1 and iB2 form a level shift circuit. This level shift circuit includes a transistor MN1 of the transconductor 2a.
The differential input voltage input to the gates of MN2 and MN2 is level-shifted by two diodes and the transistor MP
1 and the gate of MP2. The transistors MP3 and MP4 are loads on the differential output side in the current sink direction of the transconductor 2a, and the transistors MN3 and MN4 are loads on the differential output side in the current outflow direction. Transistors MP3 and MP5 are the first current mirror circuit, transistors MP4 and MP6 are the second current mirror circuit, and transistor M
N3 and MN5 are the third current mirror circuit, transistor MN
4 and MN6 form a fourth current mirror circuit. The output difference between the first and third current mirror circuits is the transconductor 2a.
Positive feedback is provided to the MP2 output terminal of. The output difference between the second and fourth current mirror circuits is positively fed back to the MP1 output terminal of the transconductor 2a. As a result, the first to fourth current mirror circuits perform the same function as the transconductor 2d as a feedback circuit. The capacitor Cc1 is for phase compensation.

In the case of this embodiment, the inversion level shift means 3c of FIG. 5 is not necessary, and the outputs of the transconductor 2a on both sides of the current outflow direction and the current suction direction are connected to the gates of the transistors P1 and N1, respectively. It is possible to obtain the same effect as that of the above-described embodiment.

FIG. 9 shows a level shift circuit for the positive feedback transconductors 2d and 2e in the embodiment shown in FIG. 8 for the transistors MP5 and MP6 and the gate inputs of the transistors MP1 and MP2 of the transconductor 2a. The current IB1 from the current sources iB1 and iB2
And IB2 are modified examples, and similar effects can be obtained.

In each of the above-described embodiments, the FET is used for the description, but a bipolar transistor may be used for the same purpose.

[0027]

As described above, by using the amplification stage having the positive feedback loop using the transconductor in the first stage or the intermediate stage of the multistage amplifier, the high gain amplifier of the differential output type and the push-pull configuration are realized. It is possible to realize the amplifier with a small circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of FIG.

FIG. 3 is a circuit diagram showing a specific circuit of the embodiment shown in FIG.

FIG. 4 is a circuit diagram showing another specific circuit of the embodiment shown in FIG.

FIG. 5 is a block diagram showing an example in which the present invention is applied to a push-pull configuration amplifier.

6 is a circuit diagram showing a specific example circuit of the embodiment shown in FIG.

FIG. 7 is a circuit diagram showing an example in which the present invention is applied to an amplifier having a folded cascode configuration.

FIG. 8 is a circuit diagram showing another embodiment of the present invention.

FIG. 9 is a circuit diagram showing another embodiment of the present invention.

[Explanation of symbols]

2 amplification stage 2a transconductor constituting amplification stage 2b load constituting amplification stage 2c load constituting amplification stage 2d transconductor for positive feedback constituting amplification stage 2f output conductance present in amplification stage 2g present in amplification stage Output conductance 3a Output stage 3b Output stage 3c Inversion level shift means P1 P-channel FET constituting the output stage of push-pull configuration N1 N-channel FET P2 constituting the output stage of push-pull configuration P2 Configuring the output stage of push-pull configuration P-channel FET N2 N-channel FET that constitutes the output stage of push-pull configuration Vin + Positive input terminal Vin- Negative input terminal Vout Output terminal Vout + Positive output terminal Vout- Negative output terminal VB Bias potential

Claims (5)

[Claims] 1. A first transconductor which outputs a pair of current outputs whose levels change complementarily in accordance with the level of an input voltage signal from positive and negative output terminals, and positive and negative output terminals of the first transconductor. A first and a second load respectively connected between the first and second loads, and a pair of input terminals connected to the positive and negative output terminals of the first transconductor, respectively, so that the levels are complementary according to the voltage difference between the input terminals. A second transconductor that generates a pair of current outputs that change to a positive current; and a positive feedback loop that feeds back each of the pair of current outputs of the second transconductor to each of a pair of input terminals of the second transconductor in phase. An amplifier comprising: 2. The amplifier according to claim 1, wherein the conductance values of the first and second loads and the conductance value of the second transconductor are different from each other. 3. The amplifier according to claim 1, wherein the first and second transconductors are formed by a differential transistor pair. 4. A current value of a first current path flowing from the first terminal to the fourth terminal and a current value of a second current path flowing from the second terminal to the third terminal are complementary according to the level of the input voltage signal. A first transconductor that is changed to a first transconductor, first and second loads that are respectively connected between first and second terminals of the first transconductor and ground, and third and fourth terminals of the first transconductor. The third and fourth loads respectively connected between the grounds, and the difference current between the current flowing into the first terminal and the current flowing out from the third terminal is given to the second or fourth terminal, An amplifier comprising a feedback circuit for providing a difference current between a current flowing into a terminal and a current flowing out from the fourth terminal to the first or third terminal. 5. The amplifier according to claim 1, wherein the load is an active element connected to a diode or an active element whose control terminal is grounded.