JPH0555896A - Input circuit - Google Patents

Abstract

PURPOSE:To reduce the number of required MOS transistors(TRs) to a half and to suppress the increment of a semiconductor chip area to its minimum by providing this input circuit with a pseudo latch circuit for latching either one of input level signals of 'H' and 'L' levels. CONSTITUTION:If a noise is mixed between a power supply VC and ground G at the time of outputting data, when the gate/source voltage VGS of an NMOS TR Q12 in an inverter circuit 11 exceeds a threshold voltage VT the TR Q12 is made conductive. Thereby the drain potential of the TR Q12 is turned to '0' level, and a '0' level output is inverted to '1' level, generating malfunction. However when a '0' level control signal phi1 is inputted to the pseudo latch circuit 1 at the timing of noise mixing, '1' level power supply VC is applied to a node A through the PMOS TRs Q11, Q12 to suppress the malfunction. Thus the number of required MOS TRs can be reduced to a half and the increment of the chip area can be suppressed to a minimum.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit, and more particularly to an M circuit.
The present invention relates to an input circuit of a semiconductor integrated circuit composed of an OS type field effect transistor.

[0002]

2. Description of the Related Art An input circuit in a semiconductor integrated circuit such as a memory sometimes malfunctions due to noise from inside or outside the circuit. As a countermeasure against this, conventionally, an input using a pseudo latch circuit as shown in FIG. The circuit was being used.

A conventional input circuit of this type, as shown in FIG. 5, has a pseudo latch circuit 3 and an input inverter circuit I.
1 and an inverter circuit I2 for output.

The pseudo latch circuit 3 is a P channel MOS.
Transistors Q31, Q32 and N-channel MOS transistors Q33, Q34 are connected in series, and the source of P-channel MOS transistor Q31 is connected to power supply VC and N
The source of the channel MOS transistor Q34 is grounded G
Are connected to each. Also, the gate of the P channel MOS transistor Q31 and the N channel M
The gate of the OS transistor Q34 is commonly connected, and this is further connected to the output side of the inverter circuit I2.
A control signal φ is input to the gate of the N-channel MOS transistor Q33, and a control signal φ is input to the gate of the P-channel MOS transistor Q32.
Input via 31. Further, the node A on the output side of the inverter circuit I1 is connected to the P-channel MOS transistor Q.
32 and the drains of the N-channel MOS transistor Q33 are connected to a common connection point.

The inverter circuit I1 is a P-channel MO.
This is a CMOS inverter circuit including an S transistor QI1 and an N channel MOS transistor QI2.

Next, the operation of the conventional input circuit will be described.

FIG. 6 is a time chart showing the operation of the conventional input circuit. In FIG. 6A, the input signal S is low ('0').
In the case of the level, (B) shows that the input signal S is high ('
The operation in the case of 1 ') level is shown respectively.

First, when the input signal S is at "0" level, as shown in FIG. 6A, the node A on the output side of the inverter circuit I1 is at "1" level and the output O of the inverter circuit I2 is at It becomes the "0" level. At this time, the control signal φ
Is set to "0" level, the pseudo latch circuit 3 becomes irrelevant to the operation of the input circuit and has no influence.

It is assumed that the power supply VC and the ground G of the semiconductor integrated circuit have noise as shown in the figure when data is output. Then, if the noise causes the gate-source voltage VGS of the N-channel MOS transistor QI2 of the inverter circuit I1 to become higher than the threshold voltage VT, the N-channel MOS transistor QI2 becomes conductive and, as a result, the drain potential of QI2 becomes “0”. Since it becomes the “level”, the output “0” level is reversed and the output becomes the “1” level, which causes a malfunction.

At this time, the P-channel MOS transistor Q3 is input to the pseudo latch circuit 3 by inputting the "1" level control signal φ at the timing of noise mixing.
Since the power supply level VC ('1' level) is supplied to the node A via 1 and Q32, malfunction is avoided. Here, it is assumed that the control signal φ is generated by a known address detection circuit or the like.

Next, when the input signal S is at "1" level, as shown in FIG. 6B, the node A on the output side of the inverter circuit I1 is at "0" level and the output O of the inverter circuit I2 is O. Is the '1' level. At this time, the control signal φ
Is set to "0" level, the pseudo latch circuit 3 becomes irrelevant to the operation of the input circuit and has no influence.

It is assumed that the power supply VC and the ground G of the semiconductor integrated circuit have noise as shown in the figure when data is output. Then, if the noise causes the gate-source voltage VGS of the P-channel MOS transistor QI1 of the inverter circuit I1 to become higher than the threshold voltage VT, the P-channel MOS transistor QI1 becomes conductive, and as a result, the drain potential of QI1 becomes equal to the power source VC. Therefore, the output "1" level is reversed and the output becomes "0" level, which causes a malfunction.

At this time, by inputting the control signal φ of "1" level to the pseudo latch circuit 3 at the timing of noise mixing, the N-channel MOS transistor Q3.
Since the ground level G ('0' level) is supplied to the node A via 3, Q34, a malfunction is avoided.

As described above, the conventional input circuit is designed to prevent malfunction due to noise regardless of the level of the input signal, that is, "1" level or "0" level. .. However, in an actual semiconductor integrated circuit, internally generated noise is the main noise source, and the timing of mixing into the input circuit due to internal noise is fixed, so either a "1" level or a "0" level is set. In most cases, only one is affected by the mixed noise. Therefore, in most cases, the object of noise removal may be limited to only one of the "1" level and the "0" level.

[0015]

In order to prevent malfunction due to noise in the above-described conventional input circuit, even if the level of the input signal is either high or low, P
Two channel MOS transistors and N channel MO
Since a minimum of four transistors, two S-transistors, is required, there is a drawback in that the chip area is greatly increased due to an increase in the number of input circuits accompanying the higher integration of semiconductor integrated circuits.

[0016]

In the input circuit of the present invention, a signal of one of the high level and the low level of an input signal having two levels of high level and low level is converted into a signal of this one level. It is configured to include a pseudo latch circuit for latching by a synchronized control signal.

[0017]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the input circuit of the present invention.

The input circuit of this embodiment corresponds to the case where the level of the input signal S is "0" level, and as shown in FIG. 1, the pseudo latch circuit 1, the input inverter circuit I1, And an inverter circuit I2 for output.

The pseudo latch circuit 1 is a P channel MOS.
The transistors Q11 and Q12 are connected in series, and the source of the P-channel MOS transistor Q11 is connected to the power supply VC.
The drain of Q12 is connected to the node A on the output side of the inverter circuit I1. The gate of the P-channel MOS transistor Q11 is connected to the output side of the inverter circuit I2. Also, P channel M
The control signal φ1 is input to the gate of the OS transistor Q12.

The inverter circuit I1 is a CMOS inverter circuit including a P-channel MOS transistor QI1 and an N-channel MOS transistor QI2, as in the conventional example described above.

Next, the operation of this embodiment will be described.

FIG. 2 is a time chart of the circuit of this embodiment shown in FIG.

First, when the input signal S is at "0" level, as shown in FIG. 2, the node A on the output side of the inverter circuit I1 is at "1" level and the output O of the inverter circuit I2 is O.
Will be at the '0' level. At this time, control signal φ1
When it is set to the 1'level, the pseudo latch circuit 1 becomes irrelevant to the operation of the input circuit and has no influence.

It is assumed that noise is mixed in the power source VC and the ground G of the semiconductor integrated circuit at the time of outputting data, as shown in the figure. Then, if the noise causes the gate-source voltage VGS of the N-channel MOS transistor QI2 of the inverter circuit I1 to become higher than the threshold voltage VT, the N-channel MOS transistor QI2 becomes conductive and, as a result, the drain potential of QI2 becomes “0”. Since it becomes the “level”, the output “0” level is reversed and the output becomes the “1” level, which causes a malfunction.

At this time, the P-channel MOS transistor Q1 is input to the pseudo latch circuit 1 by inputting the control signal φ1 of "0" level at the timing of noise mixing.
Since the power supply level VC ('1' level) is supplied to the node A via 1 and Q12, a malfunction is avoided. Here, it is assumed that the control signal φ is generated by a known address detection circuit or the like.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing a second embodiment of the input circuit of the present invention.

The input circuit of this embodiment corresponds to the case where the level of the input signal S is "1" level. The difference between this embodiment and the first embodiment shown in FIG. 1 lies in the pseudo latch circuit. Instead of 1, the pseudo latch circuit 2 having the opposite polarity is provided.

The pseudo latch circuit 2 is an N channel MOS.
The transistors Q21 and Q22 are connected in series, and the source of the 6-channel MOS transistor Q22 is connected to the ground G and Q
The drain of 11 is connected to the node A on the output side of the inverter circuit I1.
Are connected to each. Further, the gate of the N-channel MOS transistor Q22 is connected to the output side of the inverter circuit I2. Also, N channel MO
The control signal φ2 is input to the gate of the S transistor Q21.

Next, the operation of this embodiment will be described.

FIG. 4 is a time chart of the circuit of this embodiment shown in FIG.

First, when the input signal S is at "1" level, the node A on the output side of the inverter circuit I1 is at "0" level and the output O of the inverter circuit I2 is at O level, as shown in FIG.
Is the '1' level. At this time, control signal φ2
When set to 0'level, the pseudo latch circuit 2 becomes irrelevant to the operation of the input circuit and has no influence.

It is assumed that noise is mixed in the power source VC and the ground G of the semiconductor integrated circuit when outputting data, as shown in the figure. Then, if the noise causes the gate-source voltage VGS of the P-channel MOS transistor QI1 of the inverter circuit I1 to become higher than the threshold voltage VT, the P-channel MOS transistor QI1 becomes conductive, and as a result, the drain potential of QI1 becomes' 1. Since it becomes the "level", the output "1" level is reversed to cause the "0" level, which causes a malfunction.

At this time, the control signal .phi.2 of "1" level is input to the pseudo latch circuit 1 at the timing of noise mixing, whereby the N-channel MOS transistor Q2.
Since the ground level G (“0” level) is supplied to the node A via the terminals 1 and Q22, malfunction can be avoided.

[0036]

As described above, the input circuit of the present invention includes the pseudo latch circuit for latching the signal of either the high level or the low level of the input signal, so that the number of required MOS transistors can be increased. Since it can be reduced to half, there is an effect that the increase in the area of the semiconductor chip corresponding to the increase in the number of input circuits due to the high integration can be suppressed to the minimum.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an input circuit of the present invention.

FIG. 2 is a time chart showing an example of the operation of the input circuit of this embodiment.

FIG. 3 is a block diagram showing a second embodiment of the input circuit of the present invention.

FIG. 4 is a time chart showing an example of the operation of the input circuit of this embodiment.

FIG. 5 is a block diagram showing an example of a conventional input circuit.

FIG. 6 is a time chart showing an example of the operation of a conventional input circuit.

[Explanation of symbols]

1, 2, 3 Pseudo-latch circuit I1, I2, I31 Inverter circuit Q11, Q21, Q31, Q32, QI1 P-channel MOS transistor Q12, Q22, Q33, Q34, QI2 N-channel MOS transistor

Claims (4)

[Claims] 1. A pseudo latch circuit for latching a signal of one of the high level and low level of an input signal having two levels of high level and low level by a control signal synchronized with the signal of this one level. An input circuit, comprising: 2. The input circuit according to claim 1, further comprising a first inverter circuit that inverts the input signal and a second inverter circuit that inverts and outputs the output of the first inverter circuit. The latch circuit is a first MOS whose source is connected to a power supply and whose gate is connected to the output of the second inverter circuit.
A second MOS transistor in which the control signal is input to the gate, the drain is connected to the output of the first inverter circuit, and the source is connected to the drain of the first MOS transistor. Input circuit. 3. The input circuit according to claim 2, wherein the power supply is a power supply for a semiconductor integrated circuit, and the first and second MOS transistors are P-channel MOS transistors. 4. The input circuit according to claim 2, wherein the power source is a ground potential of a semiconductor integrated circuit, and the first and second MOS transistors are N-channel MOS transistors.