JPH0555909A - Digital aids draw loop circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide a digital phased locked loop circuit which operates at high speed with a circuit configuration in which the phase adjustment of a reproduced clock signal is simple. A phase comparator 11 compares the phase of a data signal with the phase of a recovered clock signal and outputs a phase error signal. The phase error accumulation counter 12 outputs a frequency division offset value selection signal from the phase error signal. Frequency division offset circuit 13
Determines the frequency division offset value from the frequency division offset value selection signal. The frequency division counter 14 loads the frequency division offset value as an initial value, divides the master clock, and outputs the reproduction clock signal, whereby a high-speed reproduction clock signal can be obtained with a simple circuit configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phased locked loop circuit (hereinafter referred to as a digital PLL) used for data judgment of a demodulator when performing digital communication such as computer communication and car telephone.

[0002]

2. Description of the Related Art In recent years, since communication means are required to have multi-functionality, confidentiality, stability and reliability, analog communication has been actively changed to digital communication. In digital communication, the clock recovery circuit of the demodulator is composed of a digital circuit, which has the advantage that no adjustment is required and the size can be reduced.

A conventional digital PLL will be described below. FIG. 3 shows a block diagram of a conventional digital PLL. In FIG. 3, reference numeral 1 is a phase comparator which inputs a data signal and a reproduction clock signal and outputs a phase error signal. 2 receives the phase error signal as input, carries signal,
Phase error accumulation counter that outputs borrow signal. Reference numeral 3 is a pulse generation circuit which inputs a carry signal, a borrow signal and a master clock and outputs a pulse train. Reference numeral 4 is a frequency dividing counter which inputs a pulse train and outputs a reproduction clock signal. The output of this reproduced clock signal is fed back to the phase comparator 1.

Digital PLL configured as described above
With respect to, the related operation of the constituent elements will be described below. First, the phase comparator 1 compares the phase of the data signal and the phase of the reproduced clock signal by exclusive OR, and outputs the phase error signal. When the phase of the reproduced clock signal and the phase of the data signal are synchronized, the phase error signal has the same high level / low level ratio (see FIG. 5A), but the phase of the reproduced clock signal is delayed. Shows that the low level ratio becomes large (see FIG. 5B), and the high level ratio becomes large when the phase of the reproduced clock signal is advanced (see FIG. 5C).

Next, the phase error accumulation counter 2 is composed of an up / down counter, and the output from the phase comparator 1 is given to D / U (down / up). Count up at level. Therefore, the phase error accumulation counter 2 counts up a lot when the reproduced clock signal is behind the data signal in phase, and conversely counts up when the phase leads. If the phase delay continues, a carry (uppermost carry) of the counter occurs and a carry signal is output. On the contrary, if the phase continues, a borrow (uppermost digit) of the counter occurs and a borrow signal is output.

When no pulse of the carry or borrow signal is input to the pulse generating circuit 3, 1/1 of the master clock
A pulse train of two cycles is output (see FIG. 4 (a)). When one pulse is input to the carry signal input, 1/2 cycle is added to the output of the pulse generation circuit 3 (see FIG. 4).
(See (b)). When one pulse is input to the borrow signal input, 1/2 cycle is deleted from the output of the pulse generation circuit 3 (see FIG. 4C).

Next, the pulse train output from the pulse generating circuit 3 is frequency-divided by the frequency dividing counter 4 (see FIG. 4 (d)). The frequency-divided signal is the reproduced clock signal, which is fed back to the phase comparator 1. By this series of operations, when the phase is delayed, a pulse is inserted in the pulse generation circuit 3 to raise the frequency of the reproduction clock signal,
When the phase is advanced, the pulse is deleted and the frequency of the reproduction clock signal is lowered. Therefore, the phase of the reproduced clock signal is continuously adjusted.

[0008]

However, in the above-mentioned conventional configuration, since complicated processing such as inserting and deleting 1/2 cycle in the output of the pulse generating circuit 3 is required, the circuit configuration becomes complicated and high-speed operation is required. It had a problem that it could not be processed.

The present invention solves the above-mentioned conventional problems, and a digital P that realizes high-speed processing with a simple circuit configuration.
The purpose is to provide LL.

[0010]

In order to achieve the above object, a digital PLL of the present invention has a frequency division offset circuit which outputs a frequency division offset value from a frequency division offset value selection signal and an initial value of the frequency division offset value. The frequency division counter is capable of setting an initial value.

[0011]

With the above structure, the frequency division value is changed by applying the frequency division offset value to the frequency division counter as an initial value from the frequency division offset circuit which receives the offset value selection signal indicating the phase shift of the reproduced clock signal. Then, the frequency of the reproduction clock can be changed. Therefore, a digital PLL capable of continuously performing high-speed processing can be realized.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the digital PLL of this embodiment.
2 is a block diagram of FIG. As shown in FIG. 1, 11 is a phase comparator that inputs a data signal and a reproduced clock signal and outputs a phase error signal, and 12 is a phase error signal and a master clock that are input and a frequency division offset value selection signal. Output phase error accumulation counter, 13
Is a frequency division offset circuit which inputs the frequency division offset value selection signal and outputs the frequency division offset value, and 14 is a frequency division counter which inputs the frequency division offset value and the master clock and outputs the reproduced clock signal. The output of this reproduction clock is fed back to the phase comparator 11.

Digital PLL configured as described above
The operation will be described. First, the phase comparator 11
Then, the phase of the data signal and the phase of the recovered clock signal are compared by exclusive OR, and the phase error signal is output. When the phase of the reproduced clock signal and the phase of the data signal are synchronized, the phase error signal has the same high level / low level ratio (see FIG. 5A), but the phase of the reproduced clock signal is delayed. Has a large low level ratio (see FIG. 5).
(See (b)), and when the phase of the reproduced clock signal is advanced, the high level ratio becomes large (see FIG. 5 (c)).

Next, the phase error accumulation counter 12 is composed of an up / down counter, and the output from the phase comparator 11 is given to D / U (down / up).
Counts down at high level and counts up at low level. Therefore, the phase error accumulation counter 1
In No. 2, when the reproduced clock signal is delayed in phase with respect to the data signal, the count-up increases, and when the reproduced clock signal advances in phase, the count-down increases. If the phase delay continues, a carry (uppermost carry) of the counter occurs and a carry signal is output. On the contrary, if the phase continues, a borrow (uppermost digit) of the counter occurs and a borrow signal is output. The carry and borrow signals are selection signals for frequency division offset values.

The frequency division offset circuit 13 is a part which determines a value to be loaded into the frequency division counter 14 from the frequency division offset value selection signal from the phase error accumulation counter 12. When the carry signal is output from the phase error accumulation counter 12, the offset value is S-T (where S and T are arbitrary integer values), and when the borrow signal is output, the offset value is S-T.
Set to + T. If neither output is available, the offset value is S
To The frequency division counter 14 is a frequency division offset circuit 13
The frequency division offset value from is loaded as the initial value, the initial value to the set value are counted, the master clock is divided, and the reproduced clock signal is output. If the set value is 4
2 shows the reproduced clock signal waveform in the case of the above. In this embodiment, S = 0 and T = 1. 2A shows a case where the offset value is ST, FIG. 2B shows a case where the offset value is S, and FIG. 2C shows a case where the offset value is S + T. FIG. 2D shows the reproduced clock signal waveform when the offset value changes. The phase of the reproduced clock signal is fed back to the phase comparator 11. Through this series of operations, the phase of the reproduced clock signal is continuously adjusted.

By changing S in the above configuration, the frequency division value can be easily changed. Further, by changing T, it is possible to easily change the following speed of the reproduction clock signal with respect to the data signal. It should be noted that S and T may be changed based on other data.

[0017]

As described above, the digital PLL of the present invention is used.
By providing a frequency dividing offset circuit and a frequency dividing counter capable of setting an initial value, it is possible to realize an excellent digital PLL capable of high-speed operation with a circuit configuration in which the phase adjustment of the reproduced clock signal is simple.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a digital PLL according to an embodiment of the present invention.

2A is a waveform diagram showing a reproduced clock signal at S-T in the embodiment. FIG. 2B is a waveform diagram showing a reproduced clock signal at S in the embodiment. FIG. 2C is an example. (D) is a waveform diagram showing the reproduced clock signal at S + T in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional digital PLL.

FIG. 4 (a) is a waveform diagram showing a pulse train when there is no 1/2 cycle insertion and deletion of the conventional example, and (b) is a waveform diagram showing a pulse train when the 1/2 cycle insertion of the conventional example. (c) is a waveform diagram showing a pulse train when 1/2 cycle of the conventional example is deleted. (d) is a waveform diagram in which a reproduced clock signal is output from the conventional pulse train.

5A is a waveform diagram showing an output of the phase comparator when the reproduced clock signal is in a synchronous state. FIG. 5B is a waveform diagram showing an output of the phase comparator when the reproduced clock signal is in phase advance. (C) is a waveform diagram showing the output of the phase comparator when the reproduced clock signal has a phase delay.

[Explanation of symbols]

 11 phase comparator 12 phase error accumulation counter 13 frequency division offset circuit 14 frequency division counter

Claims (1)

[Claims] 1. A phase comparator which inputs a data signal and a reproduction clock signal and outputs a phase error signal, a phase error accumulation counter which inputs the phase error signal and outputs a frequency division offset value selection signal, and the frequency division. A digital phased lock including a frequency division offset circuit which inputs an offset value selection signal and outputs a frequency division offset value, and a frequency division counter which inputs a master clock with the frequency division offset value as an initial value and outputs the reproduction clock signal. Troop circuit.