JPH0555949A - Local oscillation circuit employing direct digital synthesizer - Google Patents

Abstract

PURPOSE:To reduce power consumption in the standby state of a mobile communication terminal equipment employing a DDS (direct digital synthesizer) for the local oscillation circuit. CONSTITUTION:In the local oscillation circuit of PLL configuration using an output of the DDS for a reference frequency of a phase comparator, a variable frequency divider 7 is interposed to a pre-stage of the phase comparator 4, and a changeover switch 12 is provided on the DDS, by which a fixed frequency divider 9 is connected to a reference oscillator 10 of the DDS 8 and which selects an output of the DDS 8 or an output of the fixed frequency divider 9 and inputs the selected output to the phase comparator 4, furthermore, a control section 11 is provided to the circuit, which controls the frequency division ratio of the variable frequency divider 7, on/off of the DDS 8 and the switching state of the changeover switch 12 respectively and the current consumption of the circuit is reduced by turning off the DDS 8 and throwing the changeover switch 12 to the position of the fixed frequency divider 9 in the standby state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile communication terminal used in a TDMA system, and more particularly to a local oscillator circuit using DDS.

[0002]

2. Description of the Related Art A TDMA type mobile communication terminal is shown in FIG.
As shown in (4), in the communication channel (channel), the frequency is switched for about 6 ms during the idle period 23 after the reception slot 21 and the transmission slot 22 to monitor the adjacent cell, but this frequency is switched. Conventionally, a high-speed frequency switching synthesizer using DDS has been proposed. FIG. 2 is a block diagram of a local oscillation circuit using this DDS, which includes a VCO (voltage control oscillator) 1, a buffer amplifier 2, a fixed frequency divider 3, a phase comparator 4, a CP (charge pump) 5, and an LPF. (Low-pass filter)
6 forms a PLL loop. In DDS8, CH
The reference frequency corresponding to the carrier frequency is digitally created based on the fixed clock frequency from the reference oscillator 10, and is input to the phase comparator 4 of the PLL loop.

In this configuration, the output of the VCO 1 is frequency-divided by the fixed frequency divider 3 and input to the phase comparator 4, and the DDS 8
The phase frequency is compared with the reference frequency from 1 to drive CP5 and control the voltage value of VCO1 through LPF6 to generate the carrier frequency. Since it can also be set high comparison frequency of the phase comparator 4 in the channel switching of 25KH _Z interval by changing the reference frequency in accordance with the carrier frequency, thereby enabling high-speed frequency switching.

[0004]

DISCLOSURE OF THE INVENTION The conventional DDS described above
In the local oscillation circuit using the, the current consumption in the DDS digital frequency generator and the D / A converter that digitally generate a high-frequency reference frequency is large. Therefore, there is a problem that the power consumption of the entire terminal increases when the mobile communication terminal is actually used and the power consumption also increases when the terminal stands by. An object of the present invention is to provide a local oscillation circuit that reduces power consumption at least when the terminal is on standby.

[0005]

A local oscillator circuit according to the present invention comprises a variable frequency divider inserted in front of a phase comparator of a PLL loop, and a DDS for outputting a reference frequency of the phase comparator.
Fixed divider for dividing the output of the reference oscillator of, the changeover switch for selecting the output of the fixed divider and the output of the DDS and inputting them to the phase comparator, the division ratio of the variable divider, the DDS
And a control unit for respectively controlling the power on / off and the switching operation of the changeover switch. Here, the control unit operates to turn off the DDS, switch the changeover switch to the fixed frequency divider side, and set the variable frequency divider to a predetermined frequency division ratio when the communication terminal is on standby.

[0006]

According to the present invention, during standby, the DDS is turned off, the output signal of the reference oscillator divided by the fixed frequency divider is input to the phase comparator, and the variable frequency divider of the PLL loop is fixed. By setting the frequency division ratio corresponding to the frequency divider, it is possible to reduce power consumption while ensuring frequency synchronization in the standby state.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, 1 is a VCO, 2 is a buffer amplifier, 3 is a fixed frequency divider, 4 is a phase comparator, 5 is CP, and 6 is an LPF.
A PLL loop is configured by these, but a variable frequency divider 7 is interposed between the fixed frequency divider 3 and the phase comparator 4. On the other hand, the fixed frequency divider 9 is connected to the DDS 8 in parallel from the connection point with the reference oscillator 10, and the output of the DDS 8 and the fixed frequency divider 9 are selected and output to the phase comparator 4 of the PLL loop. A changeover switch 12 is provided for this purpose. Then, the frequency division ratio of the variable frequency divider 7 is changed,
A control unit 11 is provided for controlling each of the DDS 8 on / off and the changeover switch 12, and a CH designation signal 13 input to the DDS 8 is supplied to the control unit 1.
It is configured so that 1 is also input.

According to this structure, in the frequency synchronization in the call CH, the frequency dividing ratio of the variable frequency divider 7 is set to 1/1 by the control unit 11, and the DDS 8 side of the changeover switch 12 is selected. Therefore, the reference frequency created by the DDS 8 in accordance with the carrier frequency of CH is the changeover switch 12
Is input to the phase comparator 4 of the PLL loop. V
The output of CO1 is divided by the fixed frequency divider 3 and the variable frequency divider 7
Is input to the phase comparator 4 without being divided by
Phase comparison with the signal from 8 is performed, CP5 is driven, and L
The carrier frequency is generated by controlling the voltage value of VCO1 through PF6.

On the other hand, when the telephone is put into a standby state in which it is closed, the control section 11 sets the variable frequency divider 7 to a predetermined frequency division ratio, and at the same time, the changeover switch 12 is switched to the fixed frequency divider 9 side. As a result, the signal obtained by dividing the output of the reference oscillator 10 by the fixed frequency divider 9 is input to the phase comparator 4 as the reference frequency instead of the signal from the DDS 8. At this time, the DDS 8 is turned off by the control unit 11. Further, the variable frequency dividing circuit 7 designates the frequency dividing ratio from the control unit 11 according to CH, the output of the VCO 1 is frequency-divided, and the frequency is lowered to a constant comparison frequency and input to the phase comparator 4. The frequency synchronization of the control CH is performed by using a low fixed reference frequency as the comparison frequency of the PLL loop.

[0010]

As described above, according to the present invention, when the communication terminal is on standby, the power of the DDS is turned off, and at the same time, the signal of the reference oscillator is divided by the fixed divider in the phase comparator of the PLL loop. Since the input signal is input, it is possible to reduce the power consumption of the entire communication terminal by temporarily turning off the DDS that consumes a large amount of current while ensuring frequency synchronization during standby.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a local oscillator circuit of the present invention.

FIG. 2 is a block diagram of an example of a conventional local oscillation circuit.

FIG. 3 is a layout diagram of slots in the TDMA method.

[Explanation of symbols]

 1 VCO (Voltage Controlled Oscillator) 4 Phase Comparator 5 CP 6 LPF (Low-pass Filter) 7 Variable Frequency Divider 8 DDS (Direct Digital Synthesizer) 9 Fixed Frequency Divider 10 Reference Oscillator 11 Control Unit 12 Changeover Switch

Claims (2)

[Claims] 1. A local oscillation circuit in which an oscillation frequency signal from a DDS (Direct Digital Synthesizer) is used as a reference frequency of a phase comparator in a PLL loop, and an output signal of this PLL loop is used as a local oscillation signal of a mobile communication terminal. The variable frequency divider inserted before the phase comparator, the fixed frequency divider for dividing the output of the reference oscillator of the DDS, and the output of the fixed frequency divider and the output of the DDS are selected to perform the phase comparison. A direct digital synthesizer characterized by comprising: a changeover switch to be input to the variable frequency divider; and a control section for controlling the frequency division ratio of the variable frequency divider, the power on / off of the DDS, and the changeover operation of the changeover switch. There was a local oscillator circuit. 2. The control unit sets the DD when the communication terminal is on standby.
Turn off S and switch the selector switch to the fixed divider side,
A local oscillator circuit using the direct digital synthesizer according to claim 1, which operates to set the variable frequency divider to a predetermined frequency division ratio.