JPH0557680B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a writeable and erasable nonvolatile semiconductor memory device such as an EEPROM.

[Background technology]

For example, EPROM (erasable and programmable)
In ROM), stored information can be electrically written by accumulating charge in the floating gate of a MOS transistor with a floating gate structure that forms a memory cell, but if the writing time is not appropriate, various problems may occur. failure will occur.
For example, if the write time is too long, charge will accumulate excessively, making subsequent erasing difficult. Furthermore, in some cases, the cell may be destroyed or deteriorated. On the other hand, if the write time is too short, charge will not be sufficiently accumulated on the gate, resulting in what is called a write failure.

In addition, EEPROM (electrically erasable and
In the case of a programmable ROM, not only writing but also erasing can be performed electrically, but in this case, the erasing time must also be properly managed. The structures of the MOS transistors that make up EEPROM memory cells include floating gate structures and MNOS (Metal-Nitride-oxide-
There are two types (Semiconductor), but for both of them, if the erasing time is too long, normal writing will not be possible unless a longer writing time is taken than usual, just like in the case of writing. Become. Further, depending on the case, the cell may be destroyed or deteriorated. On the other hand, if the erasing time is too short,
The accumulated charges cannot be sufficiently released, resulting in what is called a state of insufficient erasing.

Therefore, when using this type of ROM, the writing and erasing times must be properly managed, which is a hassle. Furthermore, in this type of ROM, the writing or erasing time may be adjusted depending on the application. For example, if it is desired to give priority to the number of years the stored information is stored, the writing time is made longer, and if it is desired to give priority to the writing speed, the writing time is made shorter. At this time, if the erasing time before writing is too short, there is a risk of overwriting if the subsequent writing time is too long. Furthermore, after the erasing time is too long, a longer writing time than usual is required, making it impossible to write at high speed. In this way, in a nonvolatile semiconductor memory device that can be written and erased, time management for writing or erasing is very important, but time management also takes into account the mutual relationship between writing and erasing. had to be done, and was therefore extremely troublesome.

[Purpose of the invention]

This invention was made in view of the above problems, and its main purpose is to force the user to perform troublesome time management in a writable and erasable nonvolatile semiconductor memory device. To provide a non-volatile semiconductor memory device which can always achieve an appropriate writing or erasing time in each memory cell, thereby freeing it from the trouble of time management and making it extremely easy to use. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a nonvolatile semiconductor memory device that can be written to and erased has a built-in pulse generation circuit that generates a pulse signal having a fixed time width, and the above-mentioned data is generated by a control signal applied from the outside for writing or erasing. By activating the pulse generation circuit and using a constant width pulse from the pulse generation circuit as a control signal for writing or erasing inside the storage device,
It is possible to always achieve an appropriate writing or erasing time in a memory cell without forcing the user to perform troublesome time management, and this frees the user from the trouble of time management, making it extremely easy to use. This goal is achieved.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In addition, the same or corresponding parts are indicated by the same reference numerals in the drawings.

FIG. 1 shows an embodiment of a nonvolatile semiconductor memory device according to the present invention. The nonvolatile semiconductor memory device shown in the figure is configured as the aforementioned EEPROM, and can be electrically written and erased. The ROM shown in the figure is, first of all,
Memory matrix 10, XY decoder 12, address buffer 14, read circuit 16, write circuit 1
8, output buffer 20, and input buffer 22
has. Then, it operates with the power supply voltage Vcc,
Data stored in a memory cell selected by address data A0 to An is read out from a storage data input/output terminal I/O.
Furthermore, data stored in each memory cell can be written and erased by a gate write circuit 24, an erase circuit 26, a write/erase voltage generation circuit 28, an inverter 30, and a pulse generation circuit 32. It's summery. The pulse generation circuit 32 is
It is configured to be activated by a control signal, ie, a program signal Po, given from the outside for writing or erasing, and to emit a pulse signal Pi having a constant time width. Specifically, this pulse generation circuit 32 can be constructed using a monostable multivibrator MM.

Each memory cell making up memory matrix 10 is made up of a MOS transistor. As this MOS transistor, a floating gate structure or an MNOS structure in which charge is accumulated in a nitride film can be used. In this embodiment, a MOS transistor with a floating gate structure is used. In the case of a floating gate structure, writing of storage data is performed by accumulating charge on the gate. Moreover, the erasure is performed by releasing the gate accumulated charge. Accumulation of charge in the gate or release of charge from the gate is performed by the gate write circuit 2 using a high voltage generated by the write/erase voltage generation circuit 28.
4 or by the erase circuit 26.

FIG. 2 shows an example of the operation timing of the ROM shown in FIG. In the figure, when writing is first performed, a memory cell is selected using address data A0 to An, and data to be written is applied to the input/output terminal I/O. Furthermore, the chipper select signal is set to H level to enter the write state. Then, a program signal Po is given from the outside. At this time, the external program signal Po does not directly become a write control signal, but becomes an activation signal for the pulse generation circuit 32. As a result, the pulse generation circuit 32 generates a pulse signal with a constant time width wi.
Emit Pi. This signal Pi is applied to the gate write circuit 24 as an internal write/erase signal, that is, an internal program signal. Due to this, the writing time to the memory cell is determined by the time width Wi of the program signal Pi generated internally, regardless of the time width Wo of the externally applied program signal Po.
is always constant. Therefore, even if the time width of the externally applied program signal Po is too long or, conversely, too short, a proper write state can always be obtained. This frees the user from the hassle of time management, making it possible to provide a nonvolatile semiconductor memory device that is extremely easy to use.

In the case of erasing, the chip select signal is set to L level. In this case as well, the erasing time is kept constant by the time width Wi of the internal program signal Pi generated from the pulse generation circuit 32, regardless of the time width Wo of the external program signal Po. , or there is no need to worry about insufficient erasure. Of course, there is no fear of cell destruction or deterioration due to excessive writing or erasing.

Note that erasing may be performed in memory cell units, or may be performed in column units or all memory cells at once. Further, the high voltage for writing or erasing may be supplied from outside.

In addition, the above internal program signal Pi is set to the time width Wi
can be set arbitrarily depending on the purpose of the ROM. For example, if you want to give priority to the number of years the memory can be stored, set the time width Wi to a longer value. Also,
If you want to give priority to faster writing time, set it shorter. In this case, what should be noted in this embodiment is that the pulse generation circuit 32 is shared for both writing and erasing, so that the writing time and the erasing time are the same length and well balanced. This is something that is now being set. As a result, even if the writing time is made longer or shorter, erasing and writing can always be performed in an optimal state without excess or deficiency.

〔effect〕

As described above, in the nonvolatile memory device according to the present invention, even if the width of the pulse generated by the pulse generation circuit changes due to, for example, process variations, the writing time and erasing time can be maintained at the same length in a well-balanced manner. With this, a signal with a constant pulse width is generated internally without the user having to create a program signal with an accurate pulse width externally, eliminating the troublesome time management on the user's side. It is possible to always achieve an appropriate write or erase time in each memory cell without forcing it, and this makes it possible to be freed from the trouble of time management and to make it extremely easy to use.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and various changes can be made without departing from the gist thereof. Needless to say. For example, the pulse generating circuit 32 may be of a type other than the monostable multipipulator MM, such as one that generates pulses of a constant time width using an external clock.

[Application field]

The above explanation mainly describes the invention made by the present inventor and the field of application that is its background.
Although EEPROM has been explained, it is not limited to it. For example, EAROM (electrcally
alterable ROM) and ultraviolet erasable EPROM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a nonvolatile semiconductor memory device according to the present invention. FIG. 2 is a chart showing an example of the operation timing. 10... Memory matrix, 12... XY decoder, 14... Address buffer, 16... Read circuit, 18... Write circuit, 20... Output buffer, 22... Input buffer, 24... Gate write programming circuit, 26... erase circuit, 28... write/erase voltage generating circuit, 30... inverter, 32... pulse generating circuit (monostable multivibrator MM),
Vcc...power supply voltage, A0~An...address data, I/O...memory data input/output terminal, CS...
Chip select signal, Po... External writing/
Erase control signal (external program signal), Pi...internal write/erase signal (internal program signal), Wo...time width of external program signal, Wi
...Time width of internal program signal.

Claims (1)

[Claims] 1. In a non-volatile semiconductor memory device that is equipped with a write circuit that generates a write pulse to a memory cell and an erase circuit that generates an erase pulse to a memory cell and that can be electrically written to and erased, the timing of writing and erasing can be determined from the outside. an input terminal into which a trigger signal is input, and a pulse generation circuit that is activated in response to the trigger signal and generates a pulse signal having a fixed time width, and the pulse signal generated by the pulse generation circuit is A nonvolatile semiconductor memory device, characterized in that the pulse width of a write pulse and the pulse width of an erase pulse are supplied to the write circuit and the erase circuit so as to be the same.