JPH0557786B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention provides a clock signal generated by a digital phase locked loop (DPLL) and a fixed phase clock signal depending on the connection form between a subscriber premises network termination device and a subscriber terminal. This invention relates to a clock selection control system that automatically switches between the two clocks and the retiming clock signal to generate a retiming clock signal.

Prior Art and Problems In the Integrated Services Digital Network (ISDN), the connection form between the subscriber premises network termination equipment and the subscriber terminal is based on point-to-point connections as shown in Figure 1.
There are two types: a multi-point format and a point-to-point format as shown in FIG. The connection configuration shown in Figure 1 consists of a network termination device NT and multiple terminal devices.
TEa to TEn are connected by T and R lines in the form of a bus, and the maximum distance l1 between the network termination device NT and the terminal devices TEa to TEn is 100 to 150 m or less, according to the CCITT proposal. ing. Also the second
The connection configuration shown in the figure is a network termination device NT and a terminal device.
The TEs are connected one-to-one by the T line and the R line, and the maximum distance l2 between them is the first
It can be longer than the connection form shown in the figure, and according to the CCITT proposal, it is less than 1 km.

The frame structure on the T line and the R line is, for example, 64 Kb/s channels B1 and B, as shown in FIG.
2 and a 16 Kb/s channel D are multiplexed in a time division multiplex format and a frame synchronization signal F is added. Also, as a transmission code,
It is being considered to use a 100% AMI code ("1" is a 0, "0" is a code in which positive and negative pulses are alternately used) and a violation is used as a frame synchronization signal. For example, as shown in FIG. 4, the frame synchronization signal F is "0", "0", and the previous "0"
If is a positive polarity pulse, it will be treated as a positive polarity pulse and a negative polarity pulse, and if the previous "0" is negative polarity, it will be treated as a negative polarity pulse and a positive polarity pulse,
V indicates violation.

In the connection configuration shown in FIG. 1, a frame synchronization signal F is sent from the network termination device NT to the R line, each terminal detects the frame phase, creates its own frame, and connects the network via the T line. It is sent to the terminal device NT. Also, in the connection configuration shown in Fig. 2, the terminal device detects the frame synchronization signal F sent from the network termination device NT to the R line, creates a frame in the terminal device, and transmits the frame synchronization signal F to the network termination device via the T line. It is sent to NT. This second
In the case of the point-to-point format shown in the figure, at the network termination device NT and the terminal device TE,
A normal digital phase-locked loop (DPLL) can extract clock components from received data, but the points and points shown in Figure 1.
In the case of the two-multipoint format, extraction of the clock component at the network termination device NT is particularly problematic. In other words, the distance from the network termination device NT to each terminal device is different, and since the data is multiplexed on the T line, the data phase from each terminal device at the receiving point of the network termination device NT is different, and the clock is not clocked in the normal DPLL format. Extracting the components is technically extremely difficult, and it is better to use a fixed-phase clock signal that is created based on the transmission clock signal phase as a retiming clock signal in the network termination device NT.

For example, in Figure 5, a is the network termination device NT.
The transmission signal sent from to the R line, b is the network terminal equipment
The received signal of the terminal device TEa near the NT, c is the transmitted signal sent from the terminal device TEa to the T line, d is the received signal of the terminal device TEn far from the network termination device NT, e
is the transmission signal sent from the terminal device TEn to the T line, and for the sake of simplicity, channels B1 and B2 are each composed of 3 bits, channel D is 2 bits, and frame synchronization signal F is 1 bit. Frame synchronization signals are also added to the transmission signals of the terminal devices TEa to TEn, but the frame synchronization signals of the transmission signals of the terminal device TEa shown in c and the transmission signals of the terminal device TEn shown in e are omitted. ing. Further, T indicates a 1-bit width.

When channel B2 is assigned to a terminal device TEa that is close to the network termination device NT, and channel B1 is assigned to a terminal device TEn that is far away, the terminal device TEa:
Since the transmission signal from the network terminal device NT shown in a can be received with almost no time delay as shown in b, the data on b21, b22, and b23 are transmitted through channel B2 synchronized with the received frame synchronization signal F. The frame synchronization signal F from the network termination device NT is received with a delay corresponding to the distance, and the frame synchronization signal F from the network termination device TEn is received with almost no delay at the network termination device NT, as shown in e. Then, the data of b11, b12, and b13 are sent out by the channel B1 synchronized with the received frame synchronization signal F, and the network terminal device NT transmits the data to the terminal device.
Data b21, b22, b sent from TEa
23 and data b sent from the terminal device TEn
11, b12, and b13 partially overlap as shown in f.

Due to such overlap, the second half of data b13 and the first half of data b21 completely overlap to form an uncertain region y, but the first half of data b13 and the second half of data b21 are in a definite region x,
It becomes z. In the network terminal device NT, it is difficult to extract the clock component from the received data including such an uncertain region y using DPLL.

Therefore, as shown in g, retiming is performed using a fixed phase clock signal that is synchronized with the transmission frame synchronization signal F and starts from the phase of (3/4)T. That is, the fixed phase clock signal shown in g has a phase that avoids the uncertainty region y,
In addition, since the phase is relative to the definite regions x and z, even if they partially overlap like data b13 and b21, the definite region x of the first half of data b13 and
Retiming can be performed using the fixed area z in the latter half of the data b21.

In this way, by using the retiming clock signal with the phase shown in g, retiming can be performed even when data partially overlaps, but the amount of delay between terminal devices becomes large and the data overlaps. As the number of parts increases, the determined regions x and z become smaller, making it impossible to perform retiming. That is, in the case of the point-to-multipoint format using a fixed phase retiming clock signal, there is a limit on the distance between the network termination device NT and the terminal device TEn.

If it is necessary to increase the distance between the terminal devices and the network terminal device NT, connect the terminal devices in the point-to-point format shown in Figure 2 to shorten the distance between the terminal devices and connect multiple terminal devices. If it is necessary to connect a terminal device, the terminal device will be connected in a point-to-multipoint format as shown in FIG. In cases where the connection configurations are different in this way, it is necessary for the network termination device NT to select whether to use the DPLL output clock signal or a fixed phase clock signal as the retiming clock signal. In order to make such a selection, a configuration shown in FIG. 6 can be considered. In the figure, RCV is a receiver that receives signals from the T line, DPLL is a digital phase synchronization circuit, and RTM
is a retiming circuit, SEL is a selector, SC is a transmission control circuit, and SW is a changeover switch.

A fixed phase clock signal is applied from the transmission control circuit SC to the selector SEL, and the digital phase synchronization circuit DPLL extracts a clock signal from the received data, and this clock signal is applied to the selector SEL. The clock signal selected by this selector SEL is applied to the retiming circuit RTM,
It retimes the data received by the receiver RCV. In addition, the changeover switch SW can be changed manually; for example, when switched to the ground side, the selector SEL is switched to the digital phase synchronization circuit.
When the clock signal from the DPLL is selected and switched to the +V side, the selector SEL selects a fixed phase clock signal.In the case of the point-to-multipoint format shown in Figure 1, selector SEL selects the clock signal with a fixed phase. This means switching to the +V side, and in the case of the point-to-point type shown in FIG. 2, switching the changeover switch SW to the ground side.

As mentioned above, in the past, it was necessary to switch and select the clock signal for retiming using a changeover switch SW depending on the connection type, which had the disadvantage of being complicated in operation.

OBJECTS OF THE INVENTION It is an object of the present invention to enable a network termination device to automatically identify the connection form of a terminal device and select a retiming clock signal.

Structure of the Invention The present invention includes a sending means for sending a frame synchronization signal to a terminal device, a digital phase-locked circuit (DPLL) for extracting a clock signal based on data received from the terminal device, and a retiming circuit for the received data. A point-to-point type In a system in which terminal devices are connected in a multi-point format, based on the time difference between a frame phase pulse indicating the phase of the frame synchronization signal and a detection pulse that detects a violation of the frame synchronization signal from the terminal device. A shortest terminal distance identification circuit (LID) for identifying the shortest connection distance between the terminal device and the terminal device; and a selector (SEL) for selecting between the fixed phase clock signal and the clock signal extracted by the digital phase synchronization circuit. When the shortest terminal distance identification circuit (LID) provided in the network termination device (NT) identifies that the shortest connection distance between the network termination device and the terminal device is less than or equal to a predetermined distance, the selector When the fixed phase clock signal is selected by the selector (SEL) and it is identified that the shortest connection distance between the network termination device and the terminal device exceeds the predetermined distance, the selector (SEL) selects the fixed phase clock signal. ) selects the clock signal output from the digital phase synchronization circuit, and retiming the received data from the terminal device according to the clock signal selected by the selector (SEL);
Examples will be described in detail below.

Embodiment of the Invention FIG. 7 is a block diagram of essential parts of an embodiment of the present invention, in which the same reference numerals as in FIG. 6 indicate the same parts, and LID is a shortest terminal distance identification circuit. This shortest terminal distance identification circuit LID is the network terminal equipment NT.
Based on the time difference between the frame phase pulse indicating the phase of the transmit frame synchronization signal sent from the network terminal device NT and the detection pulse that detects a violation of the receive frame synchronization signal received from the terminal device,
It is determined whether the shortest connection distance between the terminal device and the terminal device is less than a predetermined distance, and if it is less than the predetermined distance, it is determined that the connection is in the point-to-multipoint format shown in Figure 1. , a fixed phase clock signal from the transmission control circuit SC is selected by the selector SEL, and the clock signal is supplied to the retiming circuit RTM to perform retiming. If it is determined that the distance is not less than the predetermined distance, it is determined that the point-to-point format shown in Figure 2 is used, and the selector SEL selects the clock signal of the output of the digital phase-locked circuit DPLL, and retiming is performed. The clock signal is supplied to the circuit RTM to perform retiming.

FIG. 8 is a block diagram of the main parts of the shortest terminal distance identification circuit LID according to the embodiment of the present invention, where VDT is a violation detection circuit, MMV is a mono multivibrator, G1 is an AND circuit, and FF1 and FF2 are flip-flops. be. FIG. 9 is an explanatory diagram of the operation, in which a frame phase pulse a indicating the phase of the transmission frame synchronization signal F sent from the network terminal device NT is shown.
is sent out from the transmission control circuit SC at a constant cycle as shown in a in FIG. Each can be added. The output signal b of the mono-multivibrator MMV is triggered by the frame phase pulse a and outputs a signal with a predetermined time width, as shown in FIG. 9b. Also, violation detection circuit VDT
9, a violation of the received frame synchronization signal F is detected and a detection pulse c is output. When the detection pulse c is output at the timing shown in c in FIG. 9, the output of the AND circuit G1 is "1". Then, the output signal of the AND circuit G1 becomes the flip-flop FF
1 is applied to the set terminal S, the flip-flop FF1 is set, and the Q terminal output d becomes "1".
becomes. That is, it becomes what is shown in d of FIG. Since this Q terminal output d is applied to the data terminal D of flip-flop FF2, flip-flop FF2 is set by the next frame phase pulse a.
The Q terminal output e is as shown in e of FIG. This Q terminal output e serves as a switching signal for the selector SEL.

In this way, when the switching signal becomes "1",
Since this indicates that the shortest terminal distance is less than a predetermined distance, the connection is in the point-to-multipoint format shown in Figure 1, and the fixed phase clock signal from the transmission control circuit SC is selected using the selector SEL. and add it to the retiming circuit RTM.

In addition, the violation detection circuit VDT detects a violation in the received frame synchronization signal from the terminal device, and if the detected pulse c is not within the output signal of the mono multivibrator MMV as shown in FIG. , the output signal of the AND circuit G1 remains “0”, and the flip-flop FF
Since 1 and FF2 are not set, the Q terminal output of flip-flop FF2 remains at "0" as shown in g in FIG. The output clock signal is selected and applied to the retiming circuit RTM.

In other words, the shortest connection distance between the network termination device NT and the terminal device is longer in the case of point-to-multipoint format than in the case of point-to-point format, so The time difference between the detection pulse that detects a violation and the frame phase pulse a is large, and therefore the signal is not output within the time of the output signal b of the mono-multivibrator MMV. The switching signal of the Q terminal output e becomes “0”, and the selector SEL
The clock signal output from the digital phase synchronization circuit DPLL, that is, the clock signal extracted from the received data, is applied to the retiming circuit RTM.

FIG. 10 is a block diagram of the violation detection circuit VDT according to the embodiment of the present invention.
CMP2 is the receiver RCV comparator, FF3 to FF6
is a flip-flop, SR1 and SR2 are shift registers, G2 to G5 and G10 are NAND circuits, and G6 to
G9 is an OR circuit. Also, c1K is a high-speed clock signal, TH1 and TH2 are CMP1 and CMP to the comparators.
The threshold voltage of 2, 1 to 14 indicate the signals of each part, and examples of the signals 1 to 14 of each part are shown with the same symbols in the operation explanatory diagram of FIG. 11, and V in 1 indicates the violation. This shows that.

When received data 1 shown in 1 in Fig. 11 is input to the receiver RCV via the T line, the comparator CMP
1, CMP2 compares the threshold voltages TH1 and TH2, and the positive pulse is sent from the comparator CMP1 to the first
The pulses are output as shown at 2 in FIG. 1, and the negative pulses are output from the comparator CMP2 as shown at 3 in FIG. Also, the high-speed clock signal c1K is applied to the clock terminals C of flip-flops FF3 to FF6 and the clock terminals of shift registers SR1 and SR2, and the output signal 2 of the comparator CMP1 is applied to the data terminal D of the flip-flop FF3, and the output signal 2 of the comparator CMP1 is applied to the data terminal D of the flip-flop FF3. Output signal 3 of is flip-flop FF5
are applied to the data terminals D of the respective data terminals.

Output signal 2 or 3 of comparator CMP1 or CMP2
When is "1", the Q terminal output of flip-flop FF3 or FF5 becomes "1", and the next high-speed clock signal c1K causes the Q terminal output of flip-flop FF4 or FF6 in the next stage to become "1".
The NAND circuit G2 has flip-flops FF3 and FF.
Since the Q terminal outputs of flip-flops FF5 and FF6 are added to the NAND circuit G3, the output signal 4 or 7 of the NAND circuit G2 or G3 becomes "0" with the pulse width of the high-speed clock signal c1K. ” becomes. 4 and 7 in FIG. 11 indicate the aforementioned output signals 4 and 7. These output signals 4 and 7 correspond to differential signals of the rising edges of the output signals 2 and 3 of the comparators CMP1 and CMP2.

Shift registers SR1 and SR2 are NAND circuits G
2, output signals 4 and 7 of G3 to high-speed clock signal c
It is shifted by 1K and output after a time of 1 bit width, and its output signals 5 and 8 are as shown at 5 and 8 in FIG. Shift register SR1
The output signal 5 of the flip-flop FF3 and the terminal output of the flip-flop FF3 are applied to the OR circuit G6, and the output signal 6 of the OR circuit G6 becomes the one shown at 6 in FIG. That is, since the terminal output of the flip-flop FF3 and the output signal 5 of the shift register SR1 do not become "0" at the same time, the output signal 6 of the OR circuit G6 continues to be "1".

Also, the output signal 8 of the shift register SR2 and the terminal output of the flip-flop FF5 are connected to an OR circuit G9.
The output signal 9 of this OR circuit G9 is as shown in 9 in FIG. That is, at the timing when the terminal output of flip-flop FF5 and the output signal 8 of shift register SR2 simultaneously become "0", the output signal 9 of OR circuit G9 becomes "0".

Furthermore, the signals inputted from the shift registers SR1 and SR2 to the NAND circuits G4 and G5 can be, for example, the output signals of the flip-flops in the first stage of the shift registers SR1 and SR2, and are input by the high-speed clock signal c1K. Since the signals are shifted, the time delay with respect to the output signals 4 and 7 of the NAND circuits G2 and G3 is negligible.
Therefore, the output signals 10, 1 of the NAND circuits G4, G5
1 is shown at 10 and 11 in FIG.
This output signal 10 and the output signal 7 of the NAND circuit G3
The output signal 13 of the OR circuit G8 is a series of "1"s, as shown at 13 in FIG. Further, the output signal 11 of the NAND circuit G5 and the output signal 4 of the NAND circuit G4 are input to the OR circuit G7, and the output signal 12 is as shown in 12 in FIG. 11 when the output signal 11 is "0". When the output signal 4 becomes "0", it becomes "0".

Each output signal 6, 12, 1 of OR circuit G6 to G9
When either 3 or 9 becomes “0”, the NAND circuit G
The output signal 14 of 10 becomes "1" as shown at 14 in FIG. This output signal 14 becomes a violation detection signal. That is, the first violation V at 1 in FIG. 11 occurs when a positive pulse is input next to a positive pulse, and the output signal 11 of the flip-flop consisting of NAND circuits G4 and G5 becomes "0". "When,
Since the output signal 4 of the NAND circuit G2, which is a differential pulse of the rising edge of the positive pulse, becomes "0", the output signal 12 of the OR circuit G7 becomes "0", and thereby the violation detection signal 14 becomes "1". becomes.

Also, if a negative pulse is input successively after a negative pulse, when the Q terminal output of flip-flop FF5 is "0", the shift register SR
Since the output signal 8 of the OR circuit G9 becomes "0" and therefore the output signal 9 of the OR circuit G9 becomes "0", the violation detection signal 14 becomes "1".

As mentioned above, a violation with consecutive pulses of the same polarity is caused by flip-flops FF3 and FF5.
It can be detected that the output signals 6 and 9 of the OR circuits G6 and G9 become "0" based on the terminal output of and the output signals 5 and 8 of the shift registers SR1 and SR2, and pulses of the same polarity are detected at intervals. A violation occurs when the output signals 13 and 12 of the OR circuits G8 and G7 become "0" due to the output signals 10 and 11 of the NAND circuits G4 and G5 that constitute the flip-flop, and the output signals 7 and 4 of the NAND circuits G3 and G2. ”
It can be detected by

FIG. 12 is a block diagram of an example of a mono-multivibrator MMV, and shows a case where it is configured with a counter CTR. FIG. 13 is an explanatory diagram of the operation, and the frame phase pulse a is the 13th
As shown in a in the figure, when input to the load terminal L of the counter CTR, the initial value A is input to the counter CTR.
is set, so that the output terminal CA of the counter CTR becomes "0". Therefore inverter INV
The output signal b becomes "1", and the output signal b is applied to the count enable terminal EN of the counter CTR, and the high-speed clock signal c1K starts counting. Output terminal CA depending on the predetermined count contents.
becomes “1”, so the output signal b of the inverter INV becomes “0” and the count enable terminal
Since "0" is also input to EN, counting of the high speed clock signal c1K is stopped. Therefore, the first
An output signal b shown in FIG. 3b is obtained.

The time width of this output signal b can be arbitrarily set by selecting the initial value A. That is, the shortest terminal distance can be identified by setting the time width to correspond to the propagation time corresponding to the shortest distance from the network terminal device NT.

Note that, as the configuration of the multivibrator MMV, in addition to the above-described embodiments, it is of course possible to adopt a configuration using a well-known CR time constant.

Effects of the Invention As explained above, the present invention identifies the connection form of a terminal device using the shortest terminal distance identification circuit LID, and this identification is performed using the frame phase pulse and the violation detection pulse of the received frame synchronization signal. This is done based on the time relationship between If so, the system determines that the format is point-to-point, selects the clock signal extracted by the digital phase-locked circuit DPLL, and retimes the received data using the selected clock signal. The retiming clock signal for received data can be automatically identified and selected according to the connection type. Therefore, there is an advantage that operability is improved.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams for explaining the connection configuration of terminal equipment, Figure 3 is a diagram for explaining the frame structure, Figure 4 is a diagram for explaining frame synchronization signal violation, and Figure 5 is the connection configuration of Figure 1. 6 is a block diagram of the main part of the conventional example, FIG. 7 is a block diagram of the main part of the embodiment of the present invention, and FIG. 8 is a diagram of the shortest terminal distance identification circuit of the embodiment of the present invention. 9 is an explanatory diagram of its operation, FIG. 10 is a block diagram of a violation detection circuit according to an embodiment of the present invention, FIG. 11 is an explanatory diagram of its operation, and FIG. 12 is an example of a mono-multivibrator. The block diagram in FIG. 13 is an explanatory diagram of its operation. NT is a network termination device, TE, TEa to TEn are terminal devices, RC is a receiver, RTM is a retiming circuit,
DPLL is a digital phase synchronization circuit, SC is a transmission control circuit, SEL is a selector, LID is a shortest terminal distance identification circuit, VDT is a violation detection circuit,
MMV is a mono-multivibrator.

[Claims]

1. An apparatus for enabling a plurality of devices capable of synchronous and asynchronous communication to gain access to time slots on a common communication medium, the apparatus: 1. assigning priority information, including variable information, to each means to assign to the device (e.g. 1003,
1020); and 2. means (e.g. 1004) for granting access to a time slot by evaluating priority information assigned to the device contentioning for the time slot; 1003,
1020) depends on (a) whether the type of communication requested by the device is synchronous or asynchronous, and (b) whether said synchronous communication is occurring for the first time or is ongoing. 4. forming the variable part according to the priority assigned to the asynchronous communication;

Claims (1)

provided in the network termination device, and when the shortest terminal distance identification circuit identifies that the shortest connection distance between the network termination device and the terminal device is less than or equal to a predetermined distance, the selector causes the fixed Select the phase clock signal,
When it is determined that the shortest connection distance between the network termination device and the terminal device exceeds the predetermined distance, the clock signal output from the digital phase synchronized circuit is selected by the selector; A clock selection control method characterized in that data received from the terminal device is retimed by a clock signal selected by a selector.