JPH0560265B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a method for manufacturing a semiconductor device,
In particular, the present invention relates to a technology that is effective when applied to an insulated gate field effect transistor (hereinafter referred to as MISFFT) having an LDD (Light Doped Drain) structure.

[Background technology]

In a semiconductor device having a MISFET, the impurity concentration gradient of the source/drain layer, which has a conductivity type opposite to that of the substrate, becomes steep at the end of the gate electrode, and the electric field is concentrated in this part. This causes the generation of hot carriers that deteriorate device characteristics. The technology to prevent this hot carrier generation was introduced in 1982Sump VLSI Technol., Digest.
of Technical Papers, page 42.
In this method, in addition to the conventional source/drain layer, an impurity layer with a lower concentration than the source/drain layer is formed near the surface of the relatively shallow gate edge (hereinafter referred to as LDD (Light Doped Drain) structure). ]. If a low concentration region is formed at the end of the gate, concentration of the electric field will be reduced and the generation of hot carriers will be suppressed. A concrete example of such a technique is shown in FIG.

In FIG. 1, a gate electrode 6 and source/drain layers are formed in a region defined by a field insulating film 4 on a semiconductor substrate 1. The source/drain layer is formed of two layers: an N ⁺ impurity layer 2 and an N ^-- impurity layer 3. In this structure technique, the low concentration impurity layer 3 is formed to protrude by a length l in the direction of the gate electrode.
Therefore, it is possible to reduce the electric field concentration in the source/drain layer at the end of the gate. Therefore, compared to the case where the source/drain layer is formed only with the impurity layer 2, the generation of hot carriers can be sufficiently prevented.

However, the present inventor discovered that the source/drain layer of the above structure has the following serious drawbacks. That is, since the low concentration impurity layer 3 protrudes by l towards the gate side, the resistance becomes high by the area l, and the mutual conductance (gm) of the MISFET deteriorates. Therefore, there is a problem in that the operating speed of the device is greatly affected.

[Purpose of the invention]

The purpose of the present invention is to provide a MISFET with an LDD structure.
An object of the present invention is to provide a technique for preventing a decrease in mutual conductance (gm) and improving device characteristics.

Another object of the present invention is to provide a technique having a MISFET structure that prevents hot carriers.

Another object of the present invention is to provide a technique for preventing short channel effects in MISFETs.

Another object of the present invention is to provide an effective technique for miniaturizing elements.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, after sequentially forming a field insulating film, a gate insulating film, and a gate on a semiconductor substrate of a first conductivity type, a first impurity of a second conductivity type having a conductivity type opposite to that of the semiconductor substrate is introduced using the gate as a mask. a step of forming a sidewall on a side wall of the gate, and then introducing a second impurity of a second conductivity type at a higher concentration than the first impurity using the gate and the sidewall as a mask; A first impurity and the second impurity are stretched and diffused by heat treatment to form a first impurity layer having one end extending below the gate, and one end near an end of the first impurity layer below the gate. forming a second impurity layer having a bottom extending deeper than the bottom of the first impurity layer and having a higher impurity concentration than the first impurity layer; A step of introducing a third impurity of a second conductivity type having a smaller diffusion coefficient than the second impurity as a mask at a higher concentration than the second impurity, and stretching and diffusing the introduced third impurity by heat treatment, By forming a third impurity layer surrounded by the second impurity layer and having a higher impurity concentration than the second impurity layer, and making the impurity concentration distribution at both ends of the gate electrode gentle, a low concentration layer with high resistance is formed. MISFET by reducing the impurity layer area
The device characteristics are improved by improving the mutual conductance (gm) of the device.

〔Example〕

An embodiment according to the present invention will be described below.

Figure 2 shows a MISFET manufactured according to the present invention.
FIG.

On the P-type silicon semiconductor substrate 1, each
A field insulating film 4 made of silicon oxide (SiO ₂ ) is formed to separate the MISFETs, and the active region partitionedly surrounded by the field insulating film is
MISFETQ ₁ exists. MISFETQ ₁ has a gate 6 made of polysilicon, and a substrate 1 and gate 6.
A gate insulating film 5 made of SiO ₂ is formed to insulate the two. The N type source/drain region is 2
It consists of three layers: (N ⁺ layer), 3 (N ^-- layer), and 12 (N ^- layer), each of which is in ohmic contact with aluminum wiring 10 and through hole 14 .
Furthermore, the gate 6 is covered and protected by a SiO ₂ film 7 and a sidewall 8 made of SiO ₂ . The interlayer insulating film 9 is a final insulation film.

In the present invention, the source/drain layers are N ⁺
It is characterized by being formed of three layers: a type impurity layer 2, an N ^- type impurity layer 12, and an N ^-- type impurity layer 3. The N ^- type impurity layer 12 is formed to surround the N ⁺ type impurity layer 2, and the N ^-- type impurity layer 3 is of a type that protrudes the N ^- type impurity layer at the end of the gate electrode. It is formed near the substrate surface. The concentration difference in the impurity layer is N ⁺ >N ^- >N ^-- . The difference from the one in FIG. 1 is that an N ^- type impurity layer 12 is formed between an N ⁺ type impurity layer 2 and an N ^-- type impurity layer 3. Therefore, the concentration distribution of the source/drain layer is N ^-- type impurity layer 3,
The N ⁻ type impurity layer 12 and the N ⁺ type impurity layer 2 increase in this order. Since the long low-concentration region l shown by l as shown in Fig. 1 does not exist in the present invention, it does not become a high-resistance region, and the transconductance (gm) of MISFETQ ₁
will not decrease.

The impurity concentration distribution of the source/drain region according to the present invention will be explained in more detail as shown in the graph (channel direction position vs. impurity concentration distribution graph from the gate end) in FIG. The solid line indicates the source of MISFETQ ₁ in the present invention.
This is the drain impurity concentration distribution. The dotted line has the LDD structure shown in Figure 1.
This is the source/drain impurity concentration distribution of MISFET. The distribution of MISFETQ ₁ in the present invention is shown by the dotted line due to the presence of the N ^- type impurity layer 12.
It is shaped so that it bulges in the center and has less steep overall shape than the curve of the LDD structure. Furthermore, as shown by the dotted line, low concentration regions such as the region (a) are reduced. Therefore, an appropriate concentration distribution without any bias in the concentration gradient can be obtained.
Moreover, high resistance regions such as the region (a) are almost completely eliminated. Therefore, the transconductance (gm)
The deterioration of the device is suppressed, and the deterioration of the operating speed of the element is also eliminated.

Hereinafter, the manufacturing method of the present invention will be explained using FIGS. 3 to 7.

First, a P ^- conductivity type silicon substrate 1 having a (100) plane is prepared, and a field insulating film 4 is selectively formed on the surface of the substrate using a well-known technique. Next, a thin oxide film 5 that will become a gate insulating film is formed in the region defined by the field insulating film 4, and then the oxide film 5 is
After making the polysilicon layer formed thereon conductive, it is etched using a well-known technique and its surface is oxidized to form a silicon oxide film 7 for gate protection, thereby forming a gate 6 as shown in FIG. form. Next, in order to form the N ^-- type impurity layer (first impurity layer) 3 shown in FIG. Amount approx. 1
Introduce it by driving it in at about ×10 ¹² /cm. The region 13 is the part into which the N-type impurity is introduced. in this case,
A thin oxide film 5 is applied to protect the silicon substrate surface.
N-type impurities are introduced through the .

Next, after a SiO ₂ film with a thickness of about 400 Å is deposited over the entire surface, the SiO ₂ film is anisotropically etched to form a sidewall 8, which is a residue of the SiO ₂ film, on the side surface of the gate 6. Next, after depositing a thin SiO ₂ film 15 in the region where the source/drain will be formed, an N ^- type impurity layer 12 shown in FIG. 2 is deposited using the sidewall 8 and gate electrode 6 as a mask.
In order to form an N-type impurity, for example, phosphorus (P) is introduced into the substrate at an implantation energy of about 50 KeV and a dose of about 1×10 ¹⁴ /cm ² . Among the ion implantation layers 13 shown in FIG. 4, those indicated by short dotted lines become the N ^- type impurity layer 12. Since the sidewall 8 is used as a mask, from the impurity implanted to form the N ^-- type impurity layer 3 (the dotted line reaching the gate 6),
Distributed in a narrow area. After introducing impurities as described above, a high temperature diffusion treatment is performed to stretch out the introduced impurities. The structure thus formed is as shown in FIG. After this, in order to further form the N ⁺ type impurity layer 2,
Similarly, an N-type impurity layer is introduced into the silicon substrate using the sidewall 8 and gate electrode 6 as a mask. As shown in FIG. 2, the N ⁺ type impurity layer 2 is
It must be formed so that it exists inside the N ^- type impurity layer 12 and has a higher concentration. Therefore, an N ^- type impurity having a property that the diffusion coefficient is smaller than that of the impurity for forming the N-type impurity layer 12,
For example, arsenic (As) is introduced. Arsenic is
Implant energy approximately 80KeV, dose amount 5×
It is implanted under conditions of approximately 10 ¹⁵ /cm ² , and is appropriately diffused by high-temperature treatment to form a shape as shown in FIG. In this way, the source/drain layer consists of three layers: N ⁺ type impurity layer 2, N ^- type impurity layer 12, and N ^-- impurity layer 3.
In particular, at the end of the gate, N ^-- type layer 3, N ^- type layer 12, N ⁺
The mold layers 2 are formed in order of increasing concentration. Therefore, the generation of hot carriers at the gate end is significantly reduced and the number of high resistance regions is reduced, thereby preventing deterioration of mutual conductance and improving device characteristics.

After forming as described above, an interlayer insulating film 9 is formed of phosphosilicate glass (PSG) or the like, and a contact hole 14 is formed as shown in FIG. 7. After this, using a well-known technique, aluminum wiring 1
4. A financial spacing film 11 is formed to complete the process as shown in FIG.

〔effect〕

(1) In the present invention, the source/drain layer is
It is formed from three layers: an N ^-- type impurity layer, an N ^- type impurity layer, and an N ⁺ type impurity layer, and the impurity concentration gradient at the gate edge becomes gentle and prevents electric field concentration, which significantly reduces the generation of hot carriers. It is possible to reduce the amount.

(2) Similar to (1) above, the impurity concentration gradient is gentle and there are few high resistance regions, so deterioration of the mutual inductance (gm) of the MISFET can be prevented.
Therefore, the operating speed is improved.

(3) Since the sidewalls formed on the sides of the gate are used to form the N ^- type impurity layer and the N ⁺ type impurity layer, there is a short channel effect (a phenomenon where the channel becomes shorter than the actual gate width). can be prevented.

(4) Since the short channel effect can be prevented, device miniaturization can be realized.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the gate 6 may be made of silicide or metal, and the Al wiring may be made of another metal. In addition to PSG, SiO ₂ or the like can also be used for the interlayer insulating film and final passivation film.

[Application field]

The above explanation mainly describes the invention made by the present inventor and the field of application that is its background.
Although the case where the present invention is applied to a method for manufacturing a MISFET semiconductor device has been described, the present invention is not limited thereto, and can be applied to, for example, complementary MISFETs, bipolar complementary MISFETs, and the like.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a MISFET having an LDD structure, which is the premise of the present invention, FIG. 2 is a cross-sectional view of a MISFET manufactured according to the present invention, and FIGS. FIG. 8 is a cross-sectional view showing the manufacturing process of , and is a graph showing the position in the channel direction from the gate end and the impurity concentration distribution. 1...P ^- type semiconductor substrate, 2...N ⁺ -type source/
Drain layer, 3...N ^-- type source/drain layer,
4... Field insulating film (SiO ₂ ), 5... Gate insulating film (SiO ₂ ), 6... Gate (polysilicon),
7... Silicon oxide film (SiO ₂ ) for gate protection, 8... Side wall (SiO ₂ ), 9...
Interlayer insulation film (PSG), 10... Aluminum wiring, 11... Final packaging film, 1
2...N ^- type source/drain layer, 13... Arsenic implantation layer, 14... Contact hole, 15...
...Silicon oxide film (SiO ₂ ) for substrate protection.

Claims (1)

[Claims] 1. After sequentially forming a field insulating film, a gate insulating film, and a gate on a first conductivity type semiconductor substrate,
a step of introducing a first impurity of a second conductivity type opposite to that of the semiconductor substrate using the gate as a mask; and after forming a sidewall on a side wall of the gate, a second impurity using the gate and the sidewall as a mask; A step of introducing a second impurity of a conductivity type at a higher concentration than the first impurity, and stretching and diffusing the introduced first impurity and the second impurity by heat treatment so that one end thereof extends below the gate. forming a first impurity layer, one end of which extends to near an end of the first impurity layer below the gate;
forming a second impurity layer whose bottom extends deeper than the bottom of the first impurity layer and has a higher impurity concentration than the first impurity layer; A step of introducing a third impurity of a second conductivity type having a smaller diffusion coefficient than the impurity at a higher concentration than the second impurity, and stretching and diffusing the introduced third impurity by heat treatment to form the second impurity layer. forming a third impurity layer surrounded by and having a higher impurity concentration than the second impurity layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first impurity and the second impurity are phosphorus, and the third impurity is arsenic.