JPH0561815B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a test circuit for a multi-frame synchronization circuit, and more specifically, to a test circuit for a multi-frame synchronization circuit in a digital transmission interface that transfers transmission path monitoring information input to an exchange. This invention relates to a circuit that tests the normality of a synchronous circuit.

(Prior art) Conventionally, this type of circuit has been described in "D70 automatic switchboard [I] hardware (1)," Telecommunications Mutual Aid Association, February 1, 1980, p.320-p.364, There is something disclosed in "D70 Automatic Exchange [Hardware (2)]" Telecommunications Mutual Aid Association, February 1, 1981, p.320-p.329. FIG. 3 shows an example of the configuration of a conventional circuit, which will be explained below.

First, an example of a digital multiplex interface frame format used in the circuit shown in FIG. 3 for transferring circuit monitoring information detected in a transmission system will be explained with reference to FIGS. 4 and 5. Figure 4 is
The 8M highway format is shown in Figure 5, and the 2M highway format is shown in Figure 5. In these figures, the symbol HG is the unit of line setting (Handling).
group), and one signal bit is assigned to each HG. Each HG signal bit takes a multi-frame, and a multi-frame consists of 8 frames. The multi-frame synchronization bit F has a pattern that repeats "0" and "1" at the bit position every 8 frames under normal conditions, and the HG is asynchronous. The V frame is a violation of "1". Also, * indicates a device alarm, and "0" indicates normality and "1" indicates abnormality.
Abnormal transmission conditions are 1. Input disconnection, 2. Frame synchronization loss (FSO). The direction from the transmission terminal station to the exchange side is defined as upstream.

When a fault occurs in the uplink line, the transmission terminal station detects this, fixes the F bit (first frame) to "1", and notifies the exchange. The monitoring information transferred in this way is called TNR1, and is used to prevent the exchange from seizing the faulty line.

Furthermore, when a failure occurs on the downlink transmission path, the monitoring information is transferred through the paired uplink transmission path.
This information is transferred using the bit defined in the 8th frame of the multiframe.
It is called TNR2 and, like TNR1, is used to prevent the exchange from seizing a faulty line. TNR2
is "1" when normal, and "0" when abnormal.

Next, the circuit configuration and operation of FIG. 3 will be described. The circuit shown in Figure 3 tests the normality of the circuit that detects TNR1 and TNR2.
2, a transmission section 13 and a transmission highway interface (HWIFS) 14.

Receiving highway interface (HWIFR) 1
1 receives four 2M highways, and after phase synchronization is multiplexed to the 8M highway. The multiplex rule is shown in Figure 6. On the other hand, the outgoing highway interface (HWIFS) 14 connects the 8M highway.
It is separated into four 2M highways. The separation law is also shown in FIG. Each time slot (hereinafter sometimes abbreviated as TS) of the 8M highway multiplexed by the receiving highway interface (HWIFR) 11 has a TSO (accommodating HG1 to HG5) shown in Fig. 5.
is accommodated. However, 2MHWO in Figure 6
TSO is defined as a self-turnback time slot, and is used as a dedicated time slot for testing the normality of the TNR1, 2 detection circuit 12-5, which will be described later.

The receiving unit 12 includes a selector (SELA) 12-1,
(SELB) 12-2, selection signal generator for these selectors (TIMA) 12-3, (TIMB) 12
-4, and a TNR1, 2 detection circuit 12-5.
The TNR1, 2 detection circuit 12-5 is the TNR1, 2 of each HG output from the selector (SELA) 12-1.
This is a circuit that detects TNR2.

In order to detect TNR1 and 2, as shown in Figure 4,
Signal bits are extracted using the multi-frame synchronization function for each HG. As mentioned above, TNR1 forcibly inserts a synchronization pattern other than the multiframe synchronization pattern at the position of multiframe synchronization, so that synchronization loss can be detected. Also,
TNR2 can be detected by the converted code as described above.

The transmitter 13 includes a memory 13-1 and an MF pattern insertion circuit 13-2. The memory 13-1 is
Each HG has a capacity for 8 frames, and any data can be set from the 1st frame to the 8th frame, read out in synchronization with multi-frames, and MF
The pattern insertion circuit 13-2 inserts a multi-frame synchronization bit (“0”,
Insert an alternating number of “1”). The output of the MF pattern insertion circuit 13-2 is connected to the transmission highway interface (HWIFS) 14, while a self-return route is connected to the reception section 12 in order to test the normality of the TNR1, 2 detection circuit 12-5. 15.

Selector (SELA) 12-1 is for self-loopback
It is controlled by a selection signal generator (TIMA) 12-3 so that input 1 is selected at the TS position, and input 0 is selected at other TS positions.

When testing the normality of the TNR1 detection circuit, the selection signal generator (TIMB)
12-4, the self-loopback TS is fixed at logic "1", and the TNR1, 2 detection circuit 12
-5 to detect TNR1. The normality of the TNR1 detection circuit can be tested by the above operation.

When testing the normality of the TNR2 detection circuit, selector (SELB) 12-
2 is controlled by a selection signal generator (TIMB) 12-4 so as to select input 0. Logic “0” indicating TNR2 in HG of self-loopback TS
In order to set, a logic "0" is written to the corresponding address of the memory 13-1 (HG where the 8th frame is accommodated). With the above operation, the TNR1 and 2 detection circuits can detect TNR2 at the HG position of the self-loopback TS, and test the normality of the TNR2 detection circuit.

(Problem to be solved by the invention) However, the circuit configuration for testing the normality of the TNR1 and TNR2 detection circuits described above uses 1TS for self-loopback, and requires memory to set TNR2. It is. In this way, the conventional method of testing the TNR1 and TNR2 detection circuits uses only one TS defined on the multiplexed highway, requires a large amount of hardware including memory, and requires complex timing control. There was a problem.

This invention is based on the self-folding TS described above.
TNR2 settings do not require memory, require a small amount of hardware, and can be used on multiplexed highways for testing purposes only.
The purpose is to provide an excellent test circuit for multi-frame synchronization circuits that does not require TS.

(Means for Solving the Problems) According to the present invention, monitoring bits indicating the line monitoring status are multiplexed into a fixed length transmission frame as a multi-frame configuration, and multi-frame synchronization of the plurality of transmission frames is achieved. Accordingly, the circuit that tests the normality of the detection circuit that detects line monitoring information is the upstream and downstream line monitoring information.
A test bit for performing a pseudo-normal test to confirm the normal operation of the TNR1 and TNR2 detection circuits is allocated in the transmission frame, and a multi-frame pattern for the pseudo-normal test is inserted at the timing position of the pseudo-normal test bit. A first means (corresponding to the selection circuit), a second means (corresponding to the MF synchronization pattern part) that generates a regular multi-frame pattern, and a second means that generates a pseudo-normal test pattern for TNR1 (TNR1 pseudo-normal setting). TNR1 pseudo-normal test pattern generating means (corresponding to the TNR2 pseudo-normal setting section); TNR2 pseudo-normal test pattern generating means (corresponding to the TNR2 pseudo-normal setting section) generating a TNR2 pseudo-normal test pattern; and an output pattern of the second means. a third means (corresponding to gate 1) for applying the output pattern of the TNR1 pseudo-normal test pattern generating means to the second means; (corresponding to) fourth means.

(Function) For the multi-frame pattern from the MF synchronization pattern section, gate 1 is TNR1 pseudo-normal and TNR1
The pseudo-normal test pattern is set independently for Gate 2, and the TNR2 pseudo-normal test pattern is set at the timing position of the pseudo-normal test bit in the transmission frame as a multi-frame pattern for the pseudo-normal test. insert. and
The test is performed by detecting errors using the TNR1 and TNR2 detection circuits. Therefore,
No memory is required for setting TNR2, and there is no need to use a dedicated time slot on the multiplexed highway, thus solving the problems of the prior art.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of the present invention, which includes a highway multiplexer (MUX) 1, a selection circuit (SEL) 2, an MF synchronization pattern generator 3, and a gate (1) 4. , gate (2) 5, AND circuit 6,
It is composed of a TNR1 pseudo-normal setting section (R1TST) 7, a TNR2 pseudo-normal setting section (R2TST) 8, and a TNR1, 2 detection circuit 9.

The highway multiplex unit (MUX) 1 accommodates eight 8M highways in the format shown in Figure 4.
Multiplex HG1 to HG20 for each highway. The format after multiplexing is shown in FIG. Bits 0 to 11 of each HW in the format shown in FIG. 2 are reserved bits. Bit8 of HW7 is used as a pseudo-normal test bit.

The MF synchronization pattern generator 3 has a pattern in which the multiframe is composed of eight frames, the first frame is "0" and "1" alternating for each multiframe, and the second to eighth frames are fixed at "1". is generated and output to gate (1)4. Also, from the generation unit 3, the 8th
An inter-frame pulse logic "1" (timing pulse T1) is output to the gate (2) 5.

The TNR1, 2 detection circuit 9 detects highway HW0~
This is a circuit that detects HG1 to HG20 of HW7 and TNR1 and TNR2 of the multi-frame pattern for pseudo-normal testing.

The function of detecting TNR1, 2 of the TNR1, 2 detection circuit 9 is to detect TNR1, 2 after extracting the monitoring bit at each HG or the test bit at the pseudo-normal test position in Fig. 2, which will be described later. However,
The function of extracting TNR1 and TNR2 thereafter is the same as that of the detection circuit 12-5 in FIG.

The selection circuit (SEL) 2 uses timing pulse logic “1” to select the multi-frame pattern (input 1) for the pseudo-normal test at the pseudo-normal test position (bit 8 of HW7) of the multiple format shown in Figure 2. ” is being supplied. The output (input 0) of the highway multiplexer (MUX) 1 is selected at locations where the timing pulse is not logic "1".
Except when the timing pulse becomes "1", the output of the highway multiplexer 1 is sent to the TNR1, 2 detection circuit 9. Input 1 of selection circuit (SEL) 2 ANDs the outputs of gate (1) 4 and gate (2) 5.
This is the AND condition in circuit 6.

The gate (1) 4 is an OR circuit which receives the regular multi-frame pattern from the MF synchronization pattern generation section 3 and the output of the TNR1 pseudo-normal setting section (R1TST) 7. Gate (2) 5 is timing pulse T1
This is a NAND circuit whose input is the output of the TNR2 pseudo-normal setting section (R2TST) 8.

The TNR1 pseudo-normal setting section (R1TST) 7 and the TNR2 pseudo-normal setting section (R2TST) 8 set pseudo-normality for TNR1 and TNR2 by setting the logic to "1".

When setting TNR1 pseudo-normal, TNR1 pseudo-normal setting section (R1TST) 7 becomes logic “1” and gate (1) 4
The first frame of the multiframe is “1” under the condition of
The multi-frame pattern for the pseudo-normal test is fixed at "1" from the first frame to the eighth frame, and the TNR1, 2 detection circuit 9 detects TNR1.

When setting TNR2 pseudo-normal, TNR2 pseudo-normal setting section (R2TST) 8 becomes logic “1” and gate (2) 5
Under the conditions, the output becomes logic “0” at the position of timing pulse T1, TNR2 is set, and TNR1, 2
The detection circuit 9 detects TNR2.

With the above TNR1 and TNR2 pseudo-normal settings,
TNR1, 2 detection circuit 9 detects an error,
This means that the normality of the TNR1 and TNR2 detection circuits has been tested.

Although the above embodiment has been described using a specific frame configuration, it goes without saying that the present invention is applicable even if the number of monitoring signals, arrangement, pseudo-normal test timing position, etc. are different from the above embodiment.

(Effects of the Invention) As described above in detail, according to the present invention, in order to test the normality of the TNR1 and TNR2 detection circuits, TNR1 and TNR2 detection circuits can be detected without defining a test TS on the multiplexed highway. a first circuit that allocates test bits for a pseudo-normal test and inserts a multi-frame pattern for a pseudo-normal test at a pseudo-normal test position;
In order to set TNR1 and TNR2 independently, there is a first gate that causes TNR1 to occur when TNR1 is pseudo-normal, and TNR2.
Since we provided a second gate that causes TNR2 to occur under pseudo-normal conditions, it becomes possible to set TNR1 and TNR2 under pseudo-normal settings. Therefore, there is no need for memory for setting TNR2 used in the conventional technology, and a reduction in the amount of hardware and simplification of control can be expected. Furthermore, TNR1,
There is no need to use a dedicated time slot on the multiplexed highway for the TNR2 pseudo-normal test, and the time slot on the highway can be expected to be used effectively.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a diagram showing the format after multiplexing, Fig. 3 is a configuration diagram of a conventional circuit, Fig. 4 is a diagram showing an example of the 8M highway format, FIG. 5 is a diagram showing an example of the 2M highway format, and FIG. 6 is an explanatory diagram of the multiplexing rule and separation rule. 1...Highway multiplex unit (MUX), 2...Selection circuit (SEL), 3...MF synchronization pattern generation unit,
4, 5...gate, 7, 8...TNR1, TNR2 pseudo-normal setting section, 9...TNR1, 2 detection circuit.

Claims (1)

[Claims] 1. Detection for detecting line monitoring information by multiplexing monitoring bits indicating the line monitoring status into a fixed length transmission frame as a multi-frame configuration, and performing multi-frame synchronization of the plurality of transmission frames. In the circuit testing the normality of circuit 9, this is line monitoring information in the upstream and downstream directions.
A test bit for performing a pseudo-normal test to confirm the normal operation of the TNR1 and TNR2 detection circuits is allocated in the transmission frame, and a multi-frame pattern for the pseudo-normal test is inserted at the timing position of the pseudo-normal test bit. a first means 2 for generating a normal multi-frame pattern; and a second means 2 for generating a regular multi-frame pattern.
means 3, and TNR1 that generates a pseudo-normal test pattern of TNR1.
Pseudo-normal test pattern generation means 7 and TNR2 for generating a pseudo-normal test pattern of TNR2
a pseudo-normal test pattern generating means 8; a third means 4 for giving the output pattern of the pseudo-normal test pattern generating means 7 an output pattern of TNR1 to the output pattern of the second means 3; A test circuit for a multi-frame synchronous circuit, characterized in that a fourth means 5 for providing an output pattern of the pseudo-normal test pattern generating means 8 is provided.