JPH0561817A - Semiconductor device and electronic equipment - Google Patents

Abstract

(57) [Summary] [Purpose] In the bus release function of the microprocessor,
By providing a bus release function dedicated to the in-circuit emulator (ICE), the object is to reduce the number of parts, reduce cost, downsize, and respond to high-speed operation. [Configuration] In the bus release function of the microprocessor,
An ICE-dedicated bus release request signal line, an ICE-dedicated bus release response signal line, a flip-flop, and a gate circuit for determining priority are added to the conventional technology (single bus release function), and the program is written in the emulation memory. A semiconductor device configured to bring a microprocessor into a bus release state when downloading a file. Alternatively, an electronic device to which this semiconductor device is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to improvement of a bus releasing function of a microprocessor.

[0002]

2. Description of the Related Art In a conventional semiconductor device, in a bus release function of a microprocessor, as shown in FIG. 3, a bus release request signal line 301, a flip-flop 302, a bus release response signal line 303, a latch 304, and It is composed of the second reference clock 305.

When the bus release request signal line 301 is asserted from the outside, the flip-flop 302 sampling the bus release request signal line 301 in synchronization with the reference clock detects the enabled state, and the bus release response signal line is detected. Enable 303. Next, the gate of the latch 304 which is normally in the through state (missing data cylinder) is negated to stop the second reference clock 305, and control is performed so that the bus can be released.

As described above, the microprocessor detects the enable state of the bus release response signal line 303 and negates the bus driver, so that the high impedance state of the bus is realized.

[0005]

However, the above-mentioned conventional technique has only one set of the bus release request signal line and the bus release response signal line, so that the following problems occur.

In-circuit emulator (hereinafter referred to as IC
When performing program debugging of a microprocessor on (abbreviated as E), it is usually necessary to download the program to the emulation memory on the ICE. At this time, the ICE disconnects the microprocessor from the bus and directly writes the program in the emulation memory. However, since the bus release request signal line and the bus release response signal line are normally opened to an external DMA controller or the like, the ICE The bus release function cannot be used. Therefore, by providing a tri-state buffer between the microprocessor and the emulation memory and negating the tri-state buffer, the ICE can access the emulation memory. Therefore, tri-state buffers for the number of buses are required, and there are problems that the cost of ICE increases, the mounting area is consumed, and the delay of the buffer hinders high-speed operation of the microprocessor.

Therefore, the present invention solves such a problem, and an object of the present invention is to provide a semiconductor device which can realize cost reduction, downsizing, and high-speed operation in realizing ICE. It is in.

[0008]

The semiconductor device of the present invention comprises:
In the bus release function of a microprocessor, a) two or more bus release request signal lines, b) two or more flip-flops sampling the two or more bus release request signal lines, and c) the two or more. A gate circuit that determines the output priority of the flip-flop, and d) two or more bus release response signal lines whose priority is determined and output by the gate circuit, and e) a reference based on the output signal of the gate circuit. A latch for stopping the clock; and f) a second reference clock output from the latch.

[0009]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 1 is a diagram of a semiconductor device of the present invention. 10
Reference numeral 1 is a bus release request signal line A for issuing a bus release request from the ICE. A bus release request signal line B 102 issues a bus release request from an external DMA controller or the like. 103 and 104 are the bus release request signal lines A101 and A101, respectively.
And a flip-flop A and a flip-flop B for sampling the state of the bus release request signal line B102. Reference numeral 105 denotes a gate circuit that determines the priority of the bus release request signal line A101 and the bus release request signal line B102. Reference numeral 106 denotes a bus release response signal line A output from the gate circuit 105. 107 is the gate circuit 1
Bus release response signal line B output from 05. A latch 108 is coupled to the gate circuit 105 and stops the reference clock when the bus is released. 109 is the second reference clock output from the latch. The semiconductor device of the present invention is configured as described above.

As shown in the timing chart of FIG.
First, when the bus release request signal line A101 is asserted, the state is sampled by the flip-flop A103, and the gate circuit 105 causes the bus release response signal line A1 to be sampled.
06 is output as an enable state. At this time, only the bus release response signal line A106 is enabled.

Next, the bus release request signal line A101 is negated and the bus release request signal line B102 is asserted. Similarly to the above, this time, the bus release request signal line B102 is sampled by the flip-flop B104, and the bus release response signal line B107 is output from the gate circuit 105 in the enabled state. At this time, only the bus release response signal line B107 is enabled.

Further, the bus release request signal line A10
1 and the bus release request signal line B102 are asserted at the same time, the respective signals are flip-flop A1.
03 and the flip-flop B104. At this time, the gate circuit 105 determines the priority of each input signal and outputs only the bus release response signal line A106 as an enabled state.

All of the above three operations are coupled to the gate circuit 105 when either the bus release response signal line A106 or the bus release response signal line B107 is enabled. Latch 1
The 08 gate signal is disabled. As a result, the latch 108 enters the hold state, and the second reference clock 109 stops.

Therefore, the microprocessor operating on the basis of the second reference clock 109 stops its operation as a CPU, and the bus release response signal line A106 or the bus release response signal line B107 is also enabled. Then, the bus is released.

[0016]

As described above, according to the present invention, two sets of the bus release request signal line and the bus release response signal line, which are one pair in the related art, are provided.
By providing more than one group and further providing them with priority, the bus release function of the microprocessor can be assigned to the ICE. Due to the above, all tristate buffers (bus buffers) between the microprocessor and emulation memory, which were indispensable in the past, can be deleted, resulting in cost reduction, downsizing, and high-speed operation. Becomes

[Brief description of drawings]

FIG. 1 is a semiconductor device diagram of the present invention.

FIG. 2 is a timing chart of a semiconductor device of the invention.

FIG. 3 is a diagram of a conventional semiconductor device.

[Explanation of symbols]

 101. Bus release request signal line A 102. Bus release request signal line B 103. Flip-flop A 104. Flip-flop B 105. Gate circuit 106. Bus release response signal line A 107. Bus release response signal line B 108. Latch 109. Second reference clock 301. Bus release request signal line 302. Flip-flop 303. Bus release response signal line 304. Latch 305. Second reference clock

Claims (2)

[Claims] 1. In a bus release function of a microprocessor, a) two or more bus release request signal lines, b) two or more flip-flops sampling the two or more bus release request signal lines, and c. ) A gate circuit that determines the output priority of the two or more flip-flops, d) Two or more bus release response signal lines whose priority is determined and output by the gate circuit, and e) the gate circuit. And a second reference clock output from the latch, the semiconductor device comprising: 2. An electronic device to which the semiconductor device according to claim 1 is applied.