JPH0561817B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission system in a digital circuit, and more particularly to a synchronous clock generation circuit necessary for multiplexing and demultiplexing data.

[Prior art] When resetting a counter that divides a clock into 1/2 ⁿ at another period with an unknown phase relationship, when the rising edge of the clock is within the valid period of the reset pulse (the case shown in Fig. 8). There are two possible situations: (1) and (2) a case where this is not the case (the case shown in FIG. 9).

However, the reset timing is based on the clock cycle.
It is assumed that the counter is multiplied by ^2k (k<n), and the counter advances at the rising edge of the input and returns to 0 upon reset.

[Problems to be solved] If the reset timing period is an integer multiple of the clock period, depending on the timing at which the circuit is initially started up, in most cases it will end up in either the state shown in Figure 8 or Figure 9, but unfortunately If the trailing edge of the reset pulse exactly overlaps with the rising edge of the clock (strictly speaking, if it approaches less than the delay time of the circuit elements), slight fluctuations in the input signal or circuit operation may cause the rising edge of the clock to coincide with the falling edge of the reset pulse. Since the earlier state (see FIG. 10) and the later state (see FIG. 11) are not constant, a stable synchronized clock cannot be obtained.

SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide a synchronous stabilization circuit that can solve the above-mentioned conventional problems and provide a constantly stable synchronous clock.

[Means for Solving Problems] The present invention divides the frequency of one clock using a counter that returns to its initial value by a reset pulse, and extracts this counter from another timing that has a constant period that is an integral multiple of the period of the clock. In the synchronization stabilizing circuit which obtains a clock signal synchronized with this timing as a counter output by returning the clock to its initial value using a reset pulse, the circuit constantly monitors whether or not the clock rises within the valid period of the reset pulse. , if the clock rises within the valid period of the reset pulse, the width of the subsequent reset pulse is widened, and if the clock does not rise within the valid period of the reset pulse, the width of the subsequent reset pulse is increased. The configuration is such that the width of the reset pulse is narrowed.

[Example] Hereinafter, the present invention will be specifically described with reference to an illustrated example.

FIG. 1 is a block circuit diagram of one embodiment of the synchronous stabilizing circuit of the present invention.

In the figure, this circuit divides the first clock a by a counter 1 and resets the counter 1 at the rising edge of the second clock b.
It generates a synchronous clock c synchronized with the second clock b.

If a reset pulse is created at the rising edge of the second clock b and the counter 1 is simply reset with that pulse, a synchronized clock c can be obtained, but the phase relationship between the first clock a and the second clock b is is optional, so the above-mentioned figure 8 or 9
Synchronous clock c
A situation may occur in which the waveform becomes unstable.

This circuit widens the width of the reset pulse h if there is a rising edge of the clock a while the reset pulse h is resetting the counter 1, and narrows the width if there is no rising edge of the clock a. This prevents a situation in which the falling edge of the reset pulse h approaches the rising edge of the first clock a and the phase of the synchronous clock c becomes unstable.

In the example of the circuit of this embodiment, the frequency of the first clock a is 2 ⁿ times that of the synchronous clock c, the frequency of the synchronous clock c is three times that of the second clock b, and the counter 1 is used to increase the frequency of the first clock a by 1/1. ²ⁿ to obtain the synchronous clock c (see Figure 2).

Here, the counter 1 counts up at the rising edge of the first clock a input to the ck input terminal, and counts up at the rising edge of the first clock a input to the ck input terminal.
When is HIGH, the counter value returns to 0 regardless of the ck input.

In the shift register 2, the D input is shifted to QA, QB, QC, . . . at the rising edge of the ck input and output.

This shift register 2, and gate 3,
4. The circuit combining inverters 5 and 6 is
At the rising edge of the second clock b, two types of pulses with different widths are generated (see FIG. 7).

One of the two types of pulses is selected depending on the state of the second D-type flip-flop (hereinafter abbreviated as FF) 11 and outputted as a reset pulse h, thereby resetting the counter 1.

The state of the second F.F. 11 is controlled by the inverter 12, AND gates 13 and 14, the inverter 15, and the output of the first F.F.

It is assumed that a high-speed clock having a frequency approximately 16 times that of the first clock a is applied to the ck terminal of the shift register 2.

Here, at the rising edge of the first clock a, a narrow pulse d is output from the AND gate 13, and if the reset pulse h is HIGH at that time, the AND gate 14 is opened and the first F.F10 is activated. It will be destroyed. The first F.F10 is a reset pulse h
If returns to LOW, it will be cleared, but at the falling edge of pulse g, the state of the first F.F10 changes to the second F.F.
F.F11 is latched, and i, the Q output of the second F.F11, becomes HIGH, and the one with the wider reset pulse width is selected (see FIG. 3).

At the rising edge of the first clock a, when the reset pulse h is LOW, the first F.F10 is not struck, and the pulse i, which is the Q output of the second F.F11, becomes LOW, and as the reset pulse h. A narrow pulse will be selected (fourth
(see figure).

Figure 5 shows a timing chart showing the moment when the falling edge of the reset pulse h approaches the rising edge of the pulse d and the width of the pulse h changes.
It is shown in FIG.

FIG. 5 shows how the width of the subsequent pulse h becomes narrower because the pulse d goes outside the pulse h.
FIG. 6 shows how the width of the subsequent pulse h becomes wider because the pulse d enters the pulse h.

In FIG. 5a, the falling edge of pulse h is pulse d.
However, once the pulse d exits the pulse h, the pulse h immediately approaches the pulse h as shown in FIG. 5b.
As the width of the pulse h becomes narrower, the falling edge of the pulse h and the pulse d suddenly separate from each other, so that in order for the pulse d to enter the pulse h again, it has to come closer than before.

In FIG. 6a, once the pulse d enters the pulse h, the width of the pulse h immediately becomes wider as shown in FIG. Makes it difficult to go outside. In this way, due to a kind of hysteresis effect, the state shown in FIG. Become.

In this way, if there is a rising edge of the first clock a while the reset pulse h is resetting the counter 1, the width of the reset pulse h is widened, and if there is no rising edge, the width of the reset pulse h is narrowed. It is possible to prevent a situation in which the falling edge of h approaches the rising edge of the first clock a and the synchronous clock c becomes unstable.

Note that the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the gist of the present invention.

[Effects of the Invention] As explained above, according to the present invention, it is determined whether the rising edge of the clock is within the effective period of the reset pulse, and the rising edge of the clock is determined while the reset pulse is resetting the counter. By widening the width of the reset pulse if it exists, and narrowing it if it does not, it is possible to prevent a situation where the falling edge of the reset pulse approaches the rising edge of the clock, making the synchronous clock unstable.

Furthermore, by using the circuit of the present invention, for example, when data that changes at the rising edge of the first clock is multiplexed and output at a timing synchronized with the second clock, the falling edge of the reset pulse is always at the rising edge of the first clock. By sampling data using this timing, it is possible to avoid sampling timing approaching a data change point.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram of one embodiment of the synchronous stabilizing circuit of the present invention, Fig. 2 is a timing chart explaining the operation of counter 1 in Fig. 1, and Fig. 3 shows the generation of a wide reset pulse. FIG. 4 is a timing chart showing the generation of a narrow reset pulse. FIGS. 5 a and b are timing charts at the moment when the reset pulse width becomes narrow. FIGS. 6 a and b are reset pulse widths. FIG. 7 is a timing chart showing the relationship between the high-speed clock, second clock, and AND gate output to the shift register. FIGS. 8 to 11 are diagrams explaining the operation of a conventional counter. FIGS. 8 and 9 are timing charts showing when the rising edge of the clock is within the valid period of the reset pulse and when it is not, respectively.
FIGS. 10 and 11 are timing charts showing cases in which the rising edge of the clock pulse is before and after the falling edge of the reset pulse, respectively. 1...Counter, 2...Shift register, 3~
6... Gate circuit, 10, 11... D-type flip-flop, 12-18... Gate circuit, a... First clock, b... Second clock, c... Synchronous clock, h... Reset pulse.

Claims (1)

[Claims] 1. One clock is frequency-divided by a counter that returns to its initial value by a reset pulse, and this counter is divided by a reset pulse extracted from another timing with a constant period that is an integral multiple of the period of the clock. In a synchronization stabilizing circuit which obtains a clock signal synchronized with this timing as a counter output by returning the clock to its initial value, the circuit constantly monitors whether or not the clock rises within the valid period of the reset pulse. If the clock rises within the valid period of the reset pulse, the width of the subsequent reset pulse is widened, and if the clock does not rise within the valid period of the reset pulse, the width of the subsequent reset pulse is increased. A synchronous stabilization circuit characterized by narrowing the width.