JPH0562823B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a GaAs power transistor, in which metal film interconnects provided in an N active layer on a semi-insulating substrate intersect with each other in an air bridge structure. The present invention relates to a method of manufacturing a semiconductor device having a portion.

[Conventional technology]

For example, in a GaAs power transistor, there are parts where the metal film wiring on the surface must cross each other, but if the purpose is to use it in an ultra-high frequency band (1 GHz or higher), the stray capacitance between the wiring must be minimized. There must be. Generally, a so-called air bridge structure is used to spatially bridge this intersection.

In this case, it is necessary to reinforce the part of the metal film wiring that will become a bridge, and
A method of forming a plating layer of about 5 μm is adopted.

However, with conventional manufacturing methods, the resistivity is 10 ¹⁶ Ω.
Metal film wiring is formed after element isolation is performed by mesa-etching the N active layer grown on a semi-insulating substrate with a thickness of 1 cm or more, so it is not possible to supply power to each metal film wiring in this state. Therefore, each metal film wiring cannot be electrolytically plated.

To deal with this, it is possible to adopt an electroless plating method that does not require electrodes, but compared to the electrolytic plating method, it is inferior in terms of adhesion to the base metal and securing the plating thickness, and it is difficult to manage the plating solution. The problem is that it is difficult.

Therefore, conventionally, electrolytic plating is used, but some form of electrically conductive line must be provided so that power can be supplied to each metal film wiring.

FIGS. 2a and 2b are a plan view and a cross-sectional view, respectively, schematically showing the structure of a power supply line to metal film wiring in a conventional method.

The N active layer 2 formed on the GaAs semi-insulating substrate 1 is subjected to mesa etching, so that the portion within the broken line in FIG. Source and drain ohmic electrodes and gate electrodes are formed in the remaining parts, but this drawing only shows one metal film wiring 3 provided in the ohmic which has a bridge part that needs to be reinforced. .

Each metal film wiring 3 is provided with a metal pattern 4 for supplying power to the metal film wiring 3 during electrolytic plating, and each metal pattern 4 is gathered around the periphery of the wafer (not shown). An insulating film 5 is formed on the metal pattern 4 stretched horizontally and vertically on the wafer so that no plating layer is formed.

After a plating layer is formed on the metal film wiring 3 and the bridge portion is reinforced, the back side of the wafer is processed and the wafer is cut.

[Problem that the invention seeks to solve]

As described above, in the conventional method, it is necessary to extend the metal patterns 4 horizontally and vertically on the wafer as a power supply line to the metal film wiring 3 during electrolytic plating to reinforce the underlying metal film of the bridge portion. Furthermore, there was a problem in that an insulating film 5 for preventing adhesion of the plating layer had to be formed on the metal pattern 4.

In addition, since the metal pattern 4 for power feeding cannot be incorporated into the chip and must be discarded, there is a problem in that the yield of the chip is significantly lowered.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method that does not require a separate power supply line.

[Means for solving problems]

The manufacturing method of the present invention is characterized in that electrolytic plating is carried out using the N active layer as a power supply conductor to the metal film wiring that will become the bridge part in order to reinforce the metal film wiring that will become the bridge part.

[Embodiments of the invention]

The manufacturing method of the present invention will be explained below. FIGS. 1A, 1B, 1C, and 1D are sectional views schematically showing structures in the middle of the process sequence in the manufacturing method of the present invention.

N active layer 2 produced on GaAs semi-insulating substrate 1
Although source and drain ohmic electrodes and a gate electrode are formed in one chip region, FIG. 1 only shows one metal film wiring 3 provided in the ohmic which has a bridge portion that needs to be reinforced. And so.

The metal film wirings 3 ohmicly provided in each chip region of the N-type active layer 2 are electrically connected by the N-type active layer 2 .

The region of the N active layer 2 where the metal film 3 is not formed is covered with an insulating film 5a (the state shown in FIG. 1A).

At this stage, the electrode of the electrolytic plating device is brought into contact with the metal film wiring 3 on the periphery of the wafer, power is supplied to each metal film wiring 3 through the N active layer 2, and a plating layer is applied to each metal film wiring 3 by the electrolytic plating method. 6 (state in figure b).

Thereafter, a resist film 7 for mesa etching is formed (the state shown in FIG. c), and the insulating film 5a and the N active layer 2 are mesa etched (the state shown in FIG. d).

After element isolation by mesa etching is completed, the resist film 7 is removed, the back surface of the wafer is processed, and the wafer is cut.

In the above, the explanation is given using a GaAs power transistor as an example, but the explanation is not limited to a GaAs power FET, and the same can be said for a monolithic microwave IC. Furthermore, the substrate is not limited to a GaAs substrate.

〔Effect of the invention〕

As explained above, the present invention reduces material costs and increases chip yield compared to conventional methods, greatly contributing to reducing manufacturing costs.

[Brief explanation of the drawing]

FIGS. 1a, b, c, and d are cross-sectional views simulating the structure in the middle of the process order in the manufacturing method of the present invention,
FIGS. 2a and 2b are a plan view and a cross-sectional view, respectively, schematically showing the structure of a power supply line to an electrode pad in a conventional method. 1...Semi-insulating substrate, 2...N operating layer, 3...
Metal film wiring, 5a... Insulating film, 6... Plating layer,
7...Resist film.

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor device in which metal film wiring provided on an N active layer on a semi-insulating substrate has a portion where they intersect with each other in an air bridge structure, the N active layer is used as a power supply conductor to the metal film wiring having a bridge portion. A method of manufacturing a semiconductor device, comprising the step of plating and reinforcing the metal film wiring of the bridge portion using an electrolytic plating method.