JPH056307A - Address bus extending device - Google Patents

Abstract

PURPOSE:To improve durability and reliability by electrically executing the extension of every address bus. CONSTITUTION:Each of extended memory boards 5, 6 having the respectively different numbers of bits in address decoders is provided with a selection signal 9 for selecting one of plural address signals and a register 10 instructs the selection state of the selection signal 9. Namely the selecting instruction is executed by writing a selection value of each slot in the register 10 through a data bus 11. At the time of initializing or changing a system environment, a user writes a proper selection value in the register 10. Namely respective selection values are written in the register 10 so that the selection circuit 9 corresponding to a slot connecting a 20-bit decoding system extended memory board selects a MAB 191 signal and the selection circuit 9 corresponding to a slot connecting a 24-bit decoding type extended memory board selects an AB 191 signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address bus expansion device used in a computer in which an expansion memory board is connected to an expansion bus to expand the memory capacity.
In particular, the present invention relates to an address bus expansion device capable of expanding the memory capacity by connecting a plurality of expansion memory boards having different bit numbers for address decoding to the same expansion bus.

[0002]

2. Description of the Related Art When a plurality of expanded memory boards with different address decode bits are connected to the same expansion bus, an expanded memory board with a small number of address decode bits has a narrow address decode range. Multiple decoded images occur in the memory address space of the memory, causing a bus collision with the extended memory board that has a large number of bits for address decoding. For example, C
PU is a 32-bit PC number of bits of the (PC-9801XL ^2, etc.), the address bus is used expansion bus 24 bits, the same two types of expansion bus the number of bits of the address decoding different extended memory -A board can be connected. On the other hand, for example, if the CPU is 16
The number of bits of the address bus of the expansion bus used for the personal computer of 20 bits is 20 according to the address bus of the CPU.
Is a bit. Also, due to the development of memory device technology, it has become possible to mount a large amount of memory on the main body, and the CPU can be obtained by improving the performance of the extended memory board used in a 16-bit personal computer. It is no longer possible to support the expanded memory space. Therefore, an expansion memory board corresponding to the 24-bit address bus was developed, and as a result, there were two kinds of expansion memory boards. This 2
The specifications of the various expansion memory boards are as follows.

(1) First expansion memory board (C
16-bit PU expansion memory board for PC)
Decode 20 bits of AB <19:00> 1 (2
0-bit decoding method) Memory of extended memory
The address is from XXXC0000H to XXXCFFFF
H, or from XXXD0000H to XXXDFFFFFH
(X = don't care) is used (2) Second expansion memory board (expansion memory board for personal computer with 32-bit CPU) AB <2
Decoding 24 bits of 3:00> 1 (24-bit decoding method) Extended memory address is × 100
Use over 000H.

This first expansion memory board is a CPU
Since the number of bits of the address bus is 20 bits (address signal name AB <19:00> 1), the address decoder of the extended memory board is also a 20-bit decoding system. The second expansion memory board has a CPU address bus of 24 bits (address bus signal name AB
Since it is <23:00> 1), the address decoder of the expansion memory board is also a 24-bit decoding system.

By connecting these two types of expansion memory boards to the same expansion bus, for example, memory address ×× 1
When C0000H is accessed, the expansion memory board of 20-bit decoding system outputs the address signal AB <2.
Since 3:20> 1 is not decoded, it is determined that the memory address XX0C0000H has been accessed.
There is a bus collision with the bit-decoded extended memory board.

In a personal computer, in order to inherit compatibility, this 2
You need to be able to connect different types of expansion memory boards to the same expansion bus. Therefore, conventionally, a circuit for generating a plurality of dedicated address signals for each expansion memory board having a different number of bits for address decoding, and a selection for selecting one address signal among the plurality of address signals generated by this circuit. A switch and a cam attached to the expansion memory board to operate this selection switch are used to connect expansion memory boards with different address decode bits to the same expansion bus. It was

Referring to FIG. 2, in the conventional address bus expansion device, in the expansion, the address signal AB <23:20> 1 of the expansion portion from the 20-bit decoding system to the 24-bit decoding system, that is, the memory address ×
× 0C ×××× H, ×× 0D ×××× H, ×× FC ××
Address for decoding XXH, XXFD XXXXXH
20-bit decoding type memory space from the decoder 1 and the address signal AB <19:17> 1 signal, that is, memory address ×× 0C ×××× H, ×× 0D ××
The address decoder 2 that decodes XXH, XXFCXXXXXH, and XXFDXXXXXH and the logical product of the results of these two address decoders 1 and 2
AND circuit 3 which outputs the 191 signal, and MAB191 signal and AB for determining the number of bits of the address decoder.
A 24-bit decoder type expansion memory board 5 equipped with an address bus interface 8 including a changeover switch 4 for selecting one of the 191 signals and a cam 6 for operating the changeover switch 4 is attached to an expansion bus address 7 It was connected by mounting in a slot (not shown).

Next, the operation of the address bus expansion device having the above configuration will be described. First, two addresses
The AND circuit 3 takes the logical product of the address signals output from the decoders 1 and 2, and the logical product signal M
The AB191 signal is output. This MAB191 signal is selected by the change-over switch 4 and output as an AB191 signal to the 20-bit decoding type extended memory board. This MAB191 signal is sent to the address bus of the expansion bus at the memory address ×× 0C ×××× H, ×× 0D
×××× H, ×× FC ×××× H or ×× FD ×××
Drives "1" only when xH is output. For example, a memory address on the address bus of the expansion bus ×× 1
When C0000H is output, the expansion memory board of 24-bit decoding method has a memory address of × 1
The data of C0000H is output, and the MAB191 signal becomes "0" on the 20-bit decoding type expansion memory board.
It is decoded as H and no data is output. Therefore, it is possible to avoid a bus collision. Although only one changeover switch 4 is shown in the above-mentioned example, it is needless to say that it is necessary to prepare the same number of changeover switches 4 as the number of slots of the expansion bus.

[0009]

The above-mentioned conventional address bus expansion device has two types of address signals MAB191.
Since the selection between the signal and the AB191 signal is made mechanically by the changeover switch 4 and the cam 6, the cam mounting precision of the expansion memory board 5 and the mounting precision of the changeover switch on the backboard on which the changeover switch 4 is mounted are strictly controlled. There is a problem in the mounting technology that it has to be controlled.

Moreover, the use of mechanical cams and changeover switches has the problem of reducing the durability and reliability of the expansion device. The number of cams and changeover switches increases in proportion to the number of types of extended memory boards with different numbers of address decoding bits, and the reliability decreases in proportion to the square of that number.

[0011]

Addresses according to the present invention
The bus expansion device selects a plurality of dedicated address signal generating means for each expansion memory board having a different number of bits of the address decoder and one address signal among the plurality of address signals generated by the generating means. It has a selection circuit and a register for instructing a selection state of the selection circuit.

When the system environment is initialized or changed, the user sets up the type of the bit number of the address decode of the extended memory board in the register with the battery backup function, and the address signal is selected by the register.

In the address bus expansion device of the present invention, a selection circuit for selecting one address signal from a plurality of address signals is used instead of the conventional changeover switch, and the selection state of the selection circuit is used instead of the conventional cam. A register that indicates is used.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings with reference to the drawings.

Referring to FIG. 1, an embodiment of the address bus expansion device according to the present invention is provided with an AB191 signal for each expansion memory board 51 and 52 instead of the changeover switch 4 and the cam 6 of FIG. A plurality of selection circuits 9 for selecting the MAB 191 signal and AB for the selection circuits 9.
A register 10 with a battery backup function for instructing selection of the 191 signal and the MAB 191 signal is provided.
Otherwise, the configuration is the same as the conventional device of FIG.

Next, the operation of the address bus expansion device having the above configuration will be described. First, the address decoder 1 decodes the address signal AB <23:20> 1 and outputs a decoded signal, and the address decoder 2 decodes the address signal AB <19:17> 1 and outputs a decoded signal. Therefore, the AND circuit 3 calculates the logical product of these decode signals, so that the address bus 7 of the expansion bus has a memory address XX0C XXXXXH.
×× 0D ×××× H, ×× FC ×××× H or ×× F
The MAB 191 signal is driven to “1” when D ×××× H is output. On the other hand, the AB191 signal is the address signal of the address bus.

One of these two signals, that is, the AB191 signal and the MAB191 signal, is selected by the address signal selection circuit 9 prepared for each slot of the expansion bus.
The selection instruction is given by the CPU writing the selection value for each slot into the register 10 via the data bus 11. This register 10 is for the user to write an appropriate selection value at the time of initializing and changing the system environment.
That is, for the selection circuit 9 corresponding to the slot to which the 20-bit decoding type expansion memory board is connected, the selection circuit 9 corresponding to the slot to which the 24-bit decoding type expansion memory board is connected is selected so that the MAB191 signal is selected. The circuit 9 writes the selected value into the register 10 so as to select the AB191 signal.

[0018]

As described above, according to the address bus expansion device of the present invention, a selector circuit for selecting one address signal from a plurality of address signals is used instead of the conventional changeover switch. Since all the steps are performed electronically by using the register for instructing the selection state of the selection circuit instead of the cam, there is an effect that durability and reliability can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an address bus expansion device according to the present invention.

FIG. 2 is a block diagram showing a conventional address bus expansion device.

[Explanation of symbols]

1, 2 address decoder 3 AND circuit 5,51,52 Extended memory board 7 Extended address bus 8 address bus interface 9 Address signal selection circuit 10 Battery backup function register

Claims (3)

[Claims] 1. An address bus expansion device in which a plurality of expansion memory boards having different address decode bits are connected to the same expansion bus, and an address is provided for each expansion memory board having different address decode bits. The selection circuit includes a generation unit that generates a signal, a selection circuit that selects one address signal from a plurality of address signals generated by the generation unit, and a register that indicates a selection state of the selection circuit. An address bus expansion device, characterized in that the type of the number of bits for address decoding of the expansion memory board is judged by the output of the register to select the address signal. 2. The address bus expansion device according to claim 1, wherein the register is a register with a battery backup function. 3. A means for generating an address signal corresponding to an extended memory board having a different number of bits of an address decoder, and one of address signals generated by the means provided for each extended memory board. Selection circuit for selecting one address signal, a register with a battery backup function for instructing the selection state of the selection circuit, and the type of the number of bits for address decoding of the expansion memory board when the system environment is initialized or changed. An address bus expansion device comprising means for setting in the register.